1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Marvell 88E6xxx Switch Global (1) Registers support
4  *
5  * Copyright (c) 2008 Marvell Semiconductor
6  *
7  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
8  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9  */
10 
11 #include <linux/bitfield.h>
12 
13 #include "chip.h"
14 #include "global1.h"
15 
16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
17 {
18 	int addr = chip->info->global1_addr;
19 
20 	return mv88e6xxx_read(chip, addr, reg, val);
21 }
22 
23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
24 {
25 	int addr = chip->info->global1_addr;
26 
27 	return mv88e6xxx_write(chip, addr, reg, val);
28 }
29 
30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
31 			  bit, int val)
32 {
33 	return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
34 				  bit, val);
35 }
36 
37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
38 			   u16 mask, u16 val)
39 {
40 	return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
41 				   mask, val);
42 }
43 
44 /* Offset 0x00: Switch Global Status Register */
45 
46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
47 {
48 	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
49 				      MV88E6185_G1_STS_PPU_STATE_MASK,
50 				      MV88E6185_G1_STS_PPU_STATE_DISABLED);
51 }
52 
53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
54 {
55 	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
56 				      MV88E6185_G1_STS_PPU_STATE_MASK,
57 				      MV88E6185_G1_STS_PPU_STATE_POLLING);
58 }
59 
60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
61 {
62 	int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
63 
64 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
65 }
66 
67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
68 {
69 	int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
70 
71 	/* Wait up to 1 second for the switch to be ready. The InitReady bit 11
72 	 * is set to a one when all units inside the device (ATU, VTU, etc.)
73 	 * have finished their initialization and are ready to accept frames.
74 	 */
75 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
76 }
77 
78 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
79  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
80  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
81  */
82 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
83 {
84 	u16 reg;
85 	int err;
86 
87 	reg = (addr[0] << 8) | addr[1];
88 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
89 	if (err)
90 		return err;
91 
92 	reg = (addr[2] << 8) | addr[3];
93 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
94 	if (err)
95 		return err;
96 
97 	reg = (addr[4] << 8) | addr[5];
98 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
99 	if (err)
100 		return err;
101 
102 	return 0;
103 }
104 
105 /* Offset 0x04: Switch Global Control Register */
106 
107 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
108 {
109 	u16 val;
110 	int err;
111 
112 	/* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
113 	 * the PPU, including re-doing PHY detection and initialization
114 	 */
115 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
116 	if (err)
117 		return err;
118 
119 	val |= MV88E6XXX_G1_CTL1_SW_RESET;
120 	val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
121 
122 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
123 	if (err)
124 		return err;
125 
126 	err = mv88e6xxx_g1_wait_init_ready(chip);
127 	if (err)
128 		return err;
129 
130 	return mv88e6185_g1_wait_ppu_polling(chip);
131 }
132 
133 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
134 {
135 	u16 val;
136 	int err;
137 
138 	/* Set the SWReset bit 15 */
139 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
140 	if (err)
141 		return err;
142 
143 	val |= MV88E6XXX_G1_CTL1_SW_RESET;
144 
145 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
146 	if (err)
147 		return err;
148 
149 	return mv88e6xxx_g1_wait_init_ready(chip);
150 }
151 
152 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
153 {
154 	int err;
155 
156 	err = mv88e6250_g1_reset(chip);
157 	if (err)
158 		return err;
159 
160 	return mv88e6352_g1_wait_ppu_polling(chip);
161 }
162 
163 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
164 {
165 	u16 val;
166 	int err;
167 
168 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
169 	if (err)
170 		return err;
171 
172 	val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
173 
174 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
175 	if (err)
176 		return err;
177 
178 	return mv88e6185_g1_wait_ppu_polling(chip);
179 }
180 
181 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
182 {
183 	u16 val;
184 	int err;
185 
186 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
187 	if (err)
188 		return err;
189 
190 	val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
191 
192 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
193 	if (err)
194 		return err;
195 
196 	return mv88e6185_g1_wait_ppu_disabled(chip);
197 }
198 
199 /* Offset 0x10: IP-PRI Mapping Register 0
200  * Offset 0x11: IP-PRI Mapping Register 1
201  * Offset 0x12: IP-PRI Mapping Register 2
202  * Offset 0x13: IP-PRI Mapping Register 3
203  * Offset 0x14: IP-PRI Mapping Register 4
204  * Offset 0x15: IP-PRI Mapping Register 5
205  * Offset 0x16: IP-PRI Mapping Register 6
206  * Offset 0x17: IP-PRI Mapping Register 7
207  */
208 
209 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
210 {
211 	int err;
212 
213 	/* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
214 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
215 	if (err)
216 		return err;
217 
218 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
219 	if (err)
220 		return err;
221 
222 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
223 	if (err)
224 		return err;
225 
226 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
227 	if (err)
228 		return err;
229 
230 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
231 	if (err)
232 		return err;
233 
234 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
235 	if (err)
236 		return err;
237 
238 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
239 	if (err)
240 		return err;
241 
242 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
243 	if (err)
244 		return err;
245 
246 	return 0;
247 }
248 
249 /* Offset 0x18: IEEE-PRI Register */
250 
251 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
252 {
253 	/* Reset the IEEE Tag priorities to defaults */
254 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
255 }
256 
257 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
258 {
259 	/* Reset the IEEE Tag priorities to defaults */
260 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
261 }
262 
263 /* Offset 0x1a: Monitor Control */
264 /* Offset 0x1a: Monitor & MGMT Control on some devices */
265 
266 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
267 				 enum mv88e6xxx_egress_direction direction,
268 				 int port)
269 {
270 	int *dest_port_chip;
271 	u16 reg;
272 	int err;
273 
274 	err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
275 	if (err)
276 		return err;
277 
278 	switch (direction) {
279 	case MV88E6XXX_EGRESS_DIR_INGRESS:
280 		dest_port_chip = &chip->ingress_dest_port;
281 		reg &= MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
282 		reg |= port <<
283 		       __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
284 		break;
285 	case MV88E6XXX_EGRESS_DIR_EGRESS:
286 		dest_port_chip = &chip->egress_dest_port;
287 		reg &= MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
288 		reg |= port <<
289 		       __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
290 		break;
291 	default:
292 		return -EINVAL;
293 	}
294 
295 	err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
296 	if (!err)
297 		*dest_port_chip = port;
298 
299 	return err;
300 }
301 
302 /* Older generations also call this the ARP destination. It has been
303  * generalized in more modern devices such that more than ARP can
304  * egress it
305  */
306 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
307 {
308 	u16 reg;
309 	int err;
310 
311 	err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
312 	if (err)
313 		return err;
314 
315 	reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
316 	reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
317 
318 	return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
319 }
320 
321 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
322 				      u16 pointer, u8 data)
323 {
324 	u16 reg;
325 
326 	reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
327 
328 	return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
329 }
330 
331 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
332 				 enum mv88e6xxx_egress_direction direction,
333 				 int port)
334 {
335 	int *dest_port_chip;
336 	u16 ptr;
337 	int err;
338 
339 	switch (direction) {
340 	case MV88E6XXX_EGRESS_DIR_INGRESS:
341 		dest_port_chip = &chip->ingress_dest_port;
342 		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
343 		break;
344 	case MV88E6XXX_EGRESS_DIR_EGRESS:
345 		dest_port_chip = &chip->egress_dest_port;
346 		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
347 		break;
348 	default:
349 		return -EINVAL;
350 	}
351 
352 	err = mv88e6390_g1_monitor_write(chip, ptr, port);
353 	if (!err)
354 		*dest_port_chip = port;
355 
356 	return err;
357 }
358 
359 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
360 {
361 	u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
362 
363 	/* Use the default high priority for management frames sent to
364 	 * the CPU.
365 	 */
366 	port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
367 
368 	return mv88e6390_g1_monitor_write(chip, ptr, port);
369 }
370 
371 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
372 {
373 	u16 ptr;
374 	int err;
375 
376 	/* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
377 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
378 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
379 	if (err)
380 		return err;
381 
382 	/* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
383 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
384 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
385 	if (err)
386 		return err;
387 
388 	/* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
389 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
390 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
391 	if (err)
392 		return err;
393 
394 	/* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
395 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
396 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
397 	if (err)
398 		return err;
399 
400 	return 0;
401 }
402 
403 /* Offset 0x1c: Global Control 2 */
404 
405 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
406 				  u16 val)
407 {
408 	u16 reg;
409 	int err;
410 
411 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &reg);
412 	if (err)
413 		return err;
414 
415 	reg &= ~mask;
416 	reg |= val & mask;
417 
418 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
419 }
420 
421 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
422 {
423 	const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
424 
425 	return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
426 }
427 
428 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
429 {
430 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
431 				      MV88E6085_G1_CTL2_RM_ENABLE, 0);
432 }
433 
434 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
435 {
436 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
437 				      MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
438 }
439 
440 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
441 {
442 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
443 				      MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
444 }
445 
446 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
447 {
448 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
449 				      MV88E6390_G1_CTL2_HIST_MODE_RX |
450 				      MV88E6390_G1_CTL2_HIST_MODE_TX);
451 }
452 
453 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
454 {
455 	return mv88e6xxx_g1_ctl2_mask(chip,
456 				      MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
457 				      index);
458 }
459 
460 /* Offset 0x1d: Statistics Operation 2 */
461 
462 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
463 {
464 	int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
465 
466 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
467 }
468 
469 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
470 {
471 	u16 val;
472 	int err;
473 
474 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
475 	if (err)
476 		return err;
477 
478 	val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
479 
480 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
481 
482 	return err;
483 }
484 
485 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
486 {
487 	int err;
488 
489 	/* Snapshot the hardware statistics counters for this port. */
490 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
491 				 MV88E6XXX_G1_STATS_OP_BUSY |
492 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
493 				 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
494 	if (err)
495 		return err;
496 
497 	/* Wait for the snapshotting to complete. */
498 	return mv88e6xxx_g1_stats_wait(chip);
499 }
500 
501 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
502 {
503 	port = (port + 1) << 5;
504 
505 	return mv88e6xxx_g1_stats_snapshot(chip, port);
506 }
507 
508 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
509 {
510 	int err;
511 
512 	port = (port + 1) << 5;
513 
514 	/* Snapshot the hardware statistics counters for this port. */
515 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
516 				 MV88E6XXX_G1_STATS_OP_BUSY |
517 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
518 	if (err)
519 		return err;
520 
521 	/* Wait for the snapshotting to complete. */
522 	return mv88e6xxx_g1_stats_wait(chip);
523 }
524 
525 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
526 {
527 	u32 value;
528 	u16 reg;
529 	int err;
530 
531 	*val = 0;
532 
533 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
534 				 MV88E6XXX_G1_STATS_OP_BUSY |
535 				 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
536 	if (err)
537 		return;
538 
539 	err = mv88e6xxx_g1_stats_wait(chip);
540 	if (err)
541 		return;
542 
543 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, &reg);
544 	if (err)
545 		return;
546 
547 	value = reg << 16;
548 
549 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, &reg);
550 	if (err)
551 		return;
552 
553 	*val = value | reg;
554 }
555 
556 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
557 {
558 	int err;
559 	u16 val;
560 
561 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
562 	if (err)
563 		return err;
564 
565 	/* Keep the histogram mode bits */
566 	val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
567 	val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
568 
569 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
570 	if (err)
571 		return err;
572 
573 	/* Wait for the flush to complete. */
574 	return mv88e6xxx_g1_stats_wait(chip);
575 }
576