1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Global (1) Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 13 #include "chip.h" 14 #include "global1.h" 15 16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17 { 18 int addr = chip->info->global1_addr; 19 20 return mv88e6xxx_read(chip, addr, reg, val); 21 } 22 23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24 { 25 int addr = chip->info->global1_addr; 26 27 return mv88e6xxx_write(chip, addr, reg, val); 28 } 29 30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 31 bit, int val) 32 { 33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 34 bit, val); 35 } 36 37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 38 u16 mask, u16 val) 39 { 40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 41 mask, val); 42 } 43 44 /* Offset 0x00: Switch Global Status Register */ 45 46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 47 { 48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 49 MV88E6185_G1_STS_PPU_STATE_MASK, 50 MV88E6185_G1_STS_PPU_STATE_DISABLED); 51 } 52 53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 54 { 55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 56 MV88E6185_G1_STS_PPU_STATE_MASK, 57 MV88E6185_G1_STS_PPU_STATE_POLLING); 58 } 59 60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 61 { 62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 63 64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 65 } 66 67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 68 { 69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 70 71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 72 * is set to a one when all units inside the device (ATU, VTU, etc.) 73 * have finished their initialization and are ready to accept frames. 74 */ 75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 76 } 77 78 void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip) 79 { 80 const unsigned long timeout = jiffies + 1 * HZ; 81 u16 val; 82 int err; 83 84 /* Wait up to 1 second for the switch to finish reading the 85 * EEPROM. 86 */ 87 while (time_before(jiffies, timeout)) { 88 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 89 if (err) { 90 dev_err(chip->dev, "Error reading status"); 91 return; 92 } 93 94 /* If the switch is still resetting, it may not 95 * respond on the bus, and so MDIO read returns 96 * 0xffff. Differentiate between that, and waiting for 97 * the EEPROM to be done by bit 0 being set. 98 */ 99 if (val != 0xffff && 100 val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE)) 101 return; 102 103 usleep_range(1000, 2000); 104 } 105 106 dev_err(chip->dev, "Timeout waiting for EEPROM done"); 107 } 108 109 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 110 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 111 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 112 */ 113 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 114 { 115 u16 reg; 116 int err; 117 118 reg = (addr[0] << 8) | addr[1]; 119 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 120 if (err) 121 return err; 122 123 reg = (addr[2] << 8) | addr[3]; 124 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 125 if (err) 126 return err; 127 128 reg = (addr[4] << 8) | addr[5]; 129 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 130 if (err) 131 return err; 132 133 return 0; 134 } 135 136 /* Offset 0x04: Switch Global Control Register */ 137 138 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 139 { 140 u16 val; 141 int err; 142 143 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 144 * the PPU, including re-doing PHY detection and initialization 145 */ 146 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 147 if (err) 148 return err; 149 150 val |= MV88E6XXX_G1_CTL1_SW_RESET; 151 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 152 153 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 154 if (err) 155 return err; 156 157 err = mv88e6xxx_g1_wait_init_ready(chip); 158 if (err) 159 return err; 160 161 return mv88e6185_g1_wait_ppu_polling(chip); 162 } 163 164 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 165 { 166 u16 val; 167 int err; 168 169 /* Set the SWReset bit 15 */ 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 171 if (err) 172 return err; 173 174 val |= MV88E6XXX_G1_CTL1_SW_RESET; 175 176 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 177 if (err) 178 return err; 179 180 return mv88e6xxx_g1_wait_init_ready(chip); 181 } 182 183 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 184 { 185 int err; 186 187 err = mv88e6250_g1_reset(chip); 188 if (err) 189 return err; 190 191 return mv88e6352_g1_wait_ppu_polling(chip); 192 } 193 194 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 195 { 196 u16 val; 197 int err; 198 199 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 200 if (err) 201 return err; 202 203 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 204 205 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 206 if (err) 207 return err; 208 209 return mv88e6185_g1_wait_ppu_polling(chip); 210 } 211 212 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 213 { 214 u16 val; 215 int err; 216 217 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 218 if (err) 219 return err; 220 221 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 222 223 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 224 if (err) 225 return err; 226 227 return mv88e6185_g1_wait_ppu_disabled(chip); 228 } 229 230 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) 231 { 232 u16 val; 233 int err; 234 235 mtu += ETH_HLEN + ETH_FCS_LEN; 236 237 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 238 if (err) 239 return err; 240 241 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632; 242 243 if (mtu > 1518) 244 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632; 245 246 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 247 } 248 249 /* Offset 0x10: IP-PRI Mapping Register 0 250 * Offset 0x11: IP-PRI Mapping Register 1 251 * Offset 0x12: IP-PRI Mapping Register 2 252 * Offset 0x13: IP-PRI Mapping Register 3 253 * Offset 0x14: IP-PRI Mapping Register 4 254 * Offset 0x15: IP-PRI Mapping Register 5 255 * Offset 0x16: IP-PRI Mapping Register 6 256 * Offset 0x17: IP-PRI Mapping Register 7 257 */ 258 259 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 260 { 261 int err; 262 263 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 264 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 265 if (err) 266 return err; 267 268 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 269 if (err) 270 return err; 271 272 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 273 if (err) 274 return err; 275 276 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 277 if (err) 278 return err; 279 280 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 281 if (err) 282 return err; 283 284 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 285 if (err) 286 return err; 287 288 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 289 if (err) 290 return err; 291 292 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 293 if (err) 294 return err; 295 296 return 0; 297 } 298 299 /* Offset 0x18: IEEE-PRI Register */ 300 301 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 302 { 303 /* Reset the IEEE Tag priorities to defaults */ 304 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 305 } 306 307 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 308 { 309 /* Reset the IEEE Tag priorities to defaults */ 310 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 311 } 312 313 /* Offset 0x1a: Monitor Control */ 314 /* Offset 0x1a: Monitor & MGMT Control on some devices */ 315 316 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 317 enum mv88e6xxx_egress_direction direction, 318 int port) 319 { 320 u16 reg; 321 int err; 322 323 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 324 if (err) 325 return err; 326 327 switch (direction) { 328 case MV88E6XXX_EGRESS_DIR_INGRESS: 329 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK; 330 reg |= port << 331 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK); 332 break; 333 case MV88E6XXX_EGRESS_DIR_EGRESS: 334 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK; 335 reg |= port << 336 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 337 break; 338 default: 339 return -EINVAL; 340 } 341 342 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 343 } 344 345 /* Older generations also call this the ARP destination. It has been 346 * generalized in more modern devices such that more than ARP can 347 * egress it 348 */ 349 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 350 { 351 u16 reg; 352 int err; 353 354 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 355 if (err) 356 return err; 357 358 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 359 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 360 361 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 362 } 363 364 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 365 u16 pointer, u8 data) 366 { 367 u16 reg; 368 369 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 370 371 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 372 } 373 374 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 375 enum mv88e6xxx_egress_direction direction, 376 int port) 377 { 378 u16 ptr; 379 380 switch (direction) { 381 case MV88E6XXX_EGRESS_DIR_INGRESS: 382 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 383 break; 384 case MV88E6XXX_EGRESS_DIR_EGRESS: 385 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 386 break; 387 default: 388 return -EINVAL; 389 } 390 391 return mv88e6390_g1_monitor_write(chip, ptr, port); 392 } 393 394 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 395 { 396 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 397 398 /* Use the default high priority for management frames sent to 399 * the CPU. 400 */ 401 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; 402 403 return mv88e6390_g1_monitor_write(chip, ptr, port); 404 } 405 406 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 407 { 408 u16 ptr; 409 int err; 410 411 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 412 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 413 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 414 if (err) 415 return err; 416 417 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 418 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 419 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 420 if (err) 421 return err; 422 423 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 424 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 425 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 426 if (err) 427 return err; 428 429 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 430 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 431 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 432 if (err) 433 return err; 434 435 return 0; 436 } 437 438 /* Offset 0x1c: Global Control 2 */ 439 440 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 441 u16 val) 442 { 443 u16 reg; 444 int err; 445 446 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 447 if (err) 448 return err; 449 450 reg &= ~mask; 451 reg |= val & mask; 452 453 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 454 } 455 456 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 457 { 458 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 459 460 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 461 } 462 463 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 464 { 465 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 466 MV88E6085_G1_CTL2_RM_ENABLE, 0); 467 } 468 469 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 470 { 471 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 472 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 473 } 474 475 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 476 { 477 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 478 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 479 } 480 481 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 482 { 483 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 484 MV88E6390_G1_CTL2_HIST_MODE_RX | 485 MV88E6390_G1_CTL2_HIST_MODE_TX); 486 } 487 488 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 489 { 490 return mv88e6xxx_g1_ctl2_mask(chip, 491 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 492 index); 493 } 494 495 /* Offset 0x1d: Statistics Operation 2 */ 496 497 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 498 { 499 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 500 501 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 502 } 503 504 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 505 { 506 u16 val; 507 int err; 508 509 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 510 if (err) 511 return err; 512 513 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 514 515 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 516 517 return err; 518 } 519 520 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 521 { 522 int err; 523 524 /* Snapshot the hardware statistics counters for this port. */ 525 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 526 MV88E6XXX_G1_STATS_OP_BUSY | 527 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 528 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 529 if (err) 530 return err; 531 532 /* Wait for the snapshotting to complete. */ 533 return mv88e6xxx_g1_stats_wait(chip); 534 } 535 536 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 537 { 538 port = (port + 1) << 5; 539 540 return mv88e6xxx_g1_stats_snapshot(chip, port); 541 } 542 543 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 544 { 545 int err; 546 547 port = (port + 1) << 5; 548 549 /* Snapshot the hardware statistics counters for this port. */ 550 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 551 MV88E6XXX_G1_STATS_OP_BUSY | 552 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 553 if (err) 554 return err; 555 556 /* Wait for the snapshotting to complete. */ 557 return mv88e6xxx_g1_stats_wait(chip); 558 } 559 560 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 561 { 562 u32 value; 563 u16 reg; 564 int err; 565 566 *val = 0; 567 568 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 569 MV88E6XXX_G1_STATS_OP_BUSY | 570 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 571 if (err) 572 return; 573 574 err = mv88e6xxx_g1_stats_wait(chip); 575 if (err) 576 return; 577 578 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 579 if (err) 580 return; 581 582 value = reg << 16; 583 584 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 585 if (err) 586 return; 587 588 *val = value | reg; 589 } 590 591 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 592 { 593 int err; 594 u16 val; 595 596 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 597 if (err) 598 return err; 599 600 /* Keep the histogram mode bits */ 601 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 602 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 603 604 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 605 if (err) 606 return err; 607 608 /* Wait for the flush to complete. */ 609 return mv88e6xxx_g1_stats_wait(chip); 610 } 611