1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Global (1) Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 13 #include "chip.h" 14 #include "global1.h" 15 16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17 { 18 int addr = chip->info->global1_addr; 19 20 return mv88e6xxx_read(chip, addr, reg, val); 21 } 22 23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24 { 25 int addr = chip->info->global1_addr; 26 27 return mv88e6xxx_write(chip, addr, reg, val); 28 } 29 30 int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 31 { 32 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 33 } 34 35 /* Offset 0x00: Switch Global Status Register */ 36 37 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 38 { 39 u16 state; 40 int i, err; 41 42 for (i = 0; i < 16; i++) { 43 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 44 if (err) 45 return err; 46 47 /* Check the value of the PPUState bits 15:14 */ 48 state &= MV88E6185_G1_STS_PPU_STATE_MASK; 49 if (state == MV88E6185_G1_STS_PPU_STATE_DISABLED) 50 return 0; 51 52 usleep_range(1000, 2000); 53 } 54 55 return -ETIMEDOUT; 56 } 57 58 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 59 { 60 u16 state; 61 int i, err; 62 63 for (i = 0; i < 16; ++i) { 64 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 65 if (err) 66 return err; 67 68 /* Check the value of the PPUState bits 15:14 */ 69 state &= MV88E6185_G1_STS_PPU_STATE_MASK; 70 if (state == MV88E6185_G1_STS_PPU_STATE_POLLING) 71 return 0; 72 73 usleep_range(1000, 2000); 74 } 75 76 return -ETIMEDOUT; 77 } 78 79 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 80 { 81 u16 state; 82 int i, err; 83 84 for (i = 0; i < 16; ++i) { 85 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 86 if (err) 87 return err; 88 89 /* Check the value of the PPUState (or InitState) bit 15 */ 90 if (state & MV88E6352_G1_STS_PPU_STATE) 91 return 0; 92 93 usleep_range(1000, 2000); 94 } 95 96 return -ETIMEDOUT; 97 } 98 99 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 100 { 101 const unsigned long timeout = jiffies + 1 * HZ; 102 u16 val; 103 int err; 104 105 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 106 * is set to a one when all units inside the device (ATU, VTU, etc.) 107 * have finished their initialization and are ready to accept frames. 108 */ 109 while (time_before(jiffies, timeout)) { 110 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 111 if (err) 112 return err; 113 114 if (val & MV88E6XXX_G1_STS_INIT_READY) 115 break; 116 117 usleep_range(1000, 2000); 118 } 119 120 if (time_after(jiffies, timeout)) 121 return -ETIMEDOUT; 122 123 return 0; 124 } 125 126 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 127 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 128 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 129 */ 130 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 131 { 132 u16 reg; 133 int err; 134 135 reg = (addr[0] << 8) | addr[1]; 136 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 137 if (err) 138 return err; 139 140 reg = (addr[2] << 8) | addr[3]; 141 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 142 if (err) 143 return err; 144 145 reg = (addr[4] << 8) | addr[5]; 146 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 147 if (err) 148 return err; 149 150 return 0; 151 } 152 153 /* Offset 0x04: Switch Global Control Register */ 154 155 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 156 { 157 u16 val; 158 int err; 159 160 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 161 * the PPU, including re-doing PHY detection and initialization 162 */ 163 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 164 if (err) 165 return err; 166 167 val |= MV88E6XXX_G1_CTL1_SW_RESET; 168 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 169 170 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 171 if (err) 172 return err; 173 174 err = mv88e6xxx_g1_wait_init_ready(chip); 175 if (err) 176 return err; 177 178 return mv88e6185_g1_wait_ppu_polling(chip); 179 } 180 181 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 182 { 183 u16 val; 184 int err; 185 186 /* Set the SWReset bit 15 */ 187 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 188 if (err) 189 return err; 190 191 val |= MV88E6XXX_G1_CTL1_SW_RESET; 192 193 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 194 if (err) 195 return err; 196 197 return mv88e6xxx_g1_wait_init_ready(chip); 198 } 199 200 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 201 { 202 int err; 203 204 err = mv88e6250_g1_reset(chip); 205 if (err) 206 return err; 207 208 return mv88e6352_g1_wait_ppu_polling(chip); 209 } 210 211 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 212 { 213 u16 val; 214 int err; 215 216 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 217 if (err) 218 return err; 219 220 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 221 222 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 223 if (err) 224 return err; 225 226 return mv88e6185_g1_wait_ppu_polling(chip); 227 } 228 229 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 230 { 231 u16 val; 232 int err; 233 234 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 235 if (err) 236 return err; 237 238 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 239 240 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 241 if (err) 242 return err; 243 244 return mv88e6185_g1_wait_ppu_disabled(chip); 245 } 246 247 /* Offset 0x10: IP-PRI Mapping Register 0 248 * Offset 0x11: IP-PRI Mapping Register 1 249 * Offset 0x12: IP-PRI Mapping Register 2 250 * Offset 0x13: IP-PRI Mapping Register 3 251 * Offset 0x14: IP-PRI Mapping Register 4 252 * Offset 0x15: IP-PRI Mapping Register 5 253 * Offset 0x16: IP-PRI Mapping Register 6 254 * Offset 0x17: IP-PRI Mapping Register 7 255 */ 256 257 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 258 { 259 int err; 260 261 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 262 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 263 if (err) 264 return err; 265 266 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 267 if (err) 268 return err; 269 270 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 271 if (err) 272 return err; 273 274 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 275 if (err) 276 return err; 277 278 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 279 if (err) 280 return err; 281 282 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 283 if (err) 284 return err; 285 286 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 287 if (err) 288 return err; 289 290 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 291 if (err) 292 return err; 293 294 return 0; 295 } 296 297 /* Offset 0x18: IEEE-PRI Register */ 298 299 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 300 { 301 /* Reset the IEEE Tag priorities to defaults */ 302 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 303 } 304 305 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 306 { 307 /* Reset the IEEE Tag priorities to defaults */ 308 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 309 } 310 311 /* Offset 0x1a: Monitor Control */ 312 /* Offset 0x1a: Monitor & MGMT Control on some devices */ 313 314 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 315 { 316 u16 reg; 317 int err; 318 319 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 320 if (err) 321 return err; 322 323 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 324 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 325 326 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 327 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 328 329 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 330 } 331 332 /* Older generations also call this the ARP destination. It has been 333 * generalized in more modern devices such that more than ARP can 334 * egress it 335 */ 336 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 337 { 338 u16 reg; 339 int err; 340 341 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 342 if (err) 343 return err; 344 345 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 346 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 347 348 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 349 } 350 351 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 352 u16 pointer, u8 data) 353 { 354 u16 reg; 355 356 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 357 358 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 359 } 360 361 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 362 { 363 u16 ptr; 364 int err; 365 366 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 367 err = mv88e6390_g1_monitor_write(chip, ptr, port); 368 if (err) 369 return err; 370 371 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 372 err = mv88e6390_g1_monitor_write(chip, ptr, port); 373 if (err) 374 return err; 375 376 return 0; 377 } 378 379 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 380 { 381 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 382 383 return mv88e6390_g1_monitor_write(chip, ptr, port); 384 } 385 386 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 387 { 388 u16 ptr; 389 int err; 390 391 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 392 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 393 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 394 if (err) 395 return err; 396 397 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 398 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 399 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 400 if (err) 401 return err; 402 403 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 404 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 405 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 406 if (err) 407 return err; 408 409 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 410 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 411 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 412 if (err) 413 return err; 414 415 return 0; 416 } 417 418 /* Offset 0x1c: Global Control 2 */ 419 420 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 421 u16 val) 422 { 423 u16 reg; 424 int err; 425 426 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 427 if (err) 428 return err; 429 430 reg &= ~mask; 431 reg |= val & mask; 432 433 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 434 } 435 436 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 437 { 438 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 439 440 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 441 } 442 443 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 444 { 445 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 446 MV88E6085_G1_CTL2_RM_ENABLE, 0); 447 } 448 449 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 450 { 451 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 452 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 453 } 454 455 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 456 { 457 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 458 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 459 } 460 461 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 462 { 463 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 464 MV88E6390_G1_CTL2_HIST_MODE_RX | 465 MV88E6390_G1_CTL2_HIST_MODE_TX); 466 } 467 468 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 469 { 470 return mv88e6xxx_g1_ctl2_mask(chip, 471 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 472 index); 473 } 474 475 /* Offset 0x1d: Statistics Operation 2 */ 476 477 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 478 { 479 return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 480 MV88E6XXX_G1_STATS_OP_BUSY); 481 } 482 483 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 484 { 485 u16 val; 486 int err; 487 488 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 489 if (err) 490 return err; 491 492 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 493 494 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 495 496 return err; 497 } 498 499 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 500 { 501 int err; 502 503 /* Snapshot the hardware statistics counters for this port. */ 504 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 505 MV88E6XXX_G1_STATS_OP_BUSY | 506 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 507 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 508 if (err) 509 return err; 510 511 /* Wait for the snapshotting to complete. */ 512 return mv88e6xxx_g1_stats_wait(chip); 513 } 514 515 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 516 { 517 port = (port + 1) << 5; 518 519 return mv88e6xxx_g1_stats_snapshot(chip, port); 520 } 521 522 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 523 { 524 int err; 525 526 port = (port + 1) << 5; 527 528 /* Snapshot the hardware statistics counters for this port. */ 529 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 530 MV88E6XXX_G1_STATS_OP_BUSY | 531 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 532 if (err) 533 return err; 534 535 /* Wait for the snapshotting to complete. */ 536 return mv88e6xxx_g1_stats_wait(chip); 537 } 538 539 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 540 { 541 u32 value; 542 u16 reg; 543 int err; 544 545 *val = 0; 546 547 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 548 MV88E6XXX_G1_STATS_OP_BUSY | 549 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 550 if (err) 551 return; 552 553 err = mv88e6xxx_g1_stats_wait(chip); 554 if (err) 555 return; 556 557 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 558 if (err) 559 return; 560 561 value = reg << 16; 562 563 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 564 if (err) 565 return; 566 567 *val = value | reg; 568 } 569 570 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 571 { 572 int err; 573 u16 val; 574 575 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 576 if (err) 577 return err; 578 579 /* Keep the histogram mode bits */ 580 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 581 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 582 583 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 584 if (err) 585 return err; 586 587 /* Wait for the flush to complete. */ 588 return mv88e6xxx_g1_stats_wait(chip); 589 } 590