1 /* 2 * Marvell 88E6xxx Switch Global (1) Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/bitfield.h> 16 17 #include "chip.h" 18 #include "global1.h" 19 20 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 21 { 22 int addr = chip->info->global1_addr; 23 24 return mv88e6xxx_read(chip, addr, reg, val); 25 } 26 27 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 28 { 29 int addr = chip->info->global1_addr; 30 31 return mv88e6xxx_write(chip, addr, reg, val); 32 } 33 34 int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 35 { 36 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 37 } 38 39 /* Offset 0x00: Switch Global Status Register */ 40 41 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 42 { 43 u16 state; 44 int i, err; 45 46 for (i = 0; i < 16; i++) { 47 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 48 if (err) 49 return err; 50 51 /* Check the value of the PPUState bits 15:14 */ 52 state &= MV88E6185_G1_STS_PPU_STATE_MASK; 53 if (state != MV88E6185_G1_STS_PPU_STATE_POLLING) 54 return 0; 55 56 usleep_range(1000, 2000); 57 } 58 59 return -ETIMEDOUT; 60 } 61 62 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 63 { 64 u16 state; 65 int i, err; 66 67 for (i = 0; i < 16; ++i) { 68 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 69 if (err) 70 return err; 71 72 /* Check the value of the PPUState bits 15:14 */ 73 state &= MV88E6185_G1_STS_PPU_STATE_MASK; 74 if (state == MV88E6185_G1_STS_PPU_STATE_POLLING) 75 return 0; 76 77 usleep_range(1000, 2000); 78 } 79 80 return -ETIMEDOUT; 81 } 82 83 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 84 { 85 u16 state; 86 int i, err; 87 88 for (i = 0; i < 16; ++i) { 89 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 90 if (err) 91 return err; 92 93 /* Check the value of the PPUState (or InitState) bit 15 */ 94 if (state & MV88E6352_G1_STS_PPU_STATE) 95 return 0; 96 97 usleep_range(1000, 2000); 98 } 99 100 return -ETIMEDOUT; 101 } 102 103 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 104 { 105 const unsigned long timeout = jiffies + 1 * HZ; 106 u16 val; 107 int err; 108 109 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 110 * is set to a one when all units inside the device (ATU, VTU, etc.) 111 * have finished their initialization and are ready to accept frames. 112 */ 113 while (time_before(jiffies, timeout)) { 114 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 115 if (err) 116 return err; 117 118 if (val & MV88E6XXX_G1_STS_INIT_READY) 119 break; 120 121 usleep_range(1000, 2000); 122 } 123 124 if (time_after(jiffies, timeout)) 125 return -ETIMEDOUT; 126 127 return 0; 128 } 129 130 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 131 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 132 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 133 */ 134 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 135 { 136 u16 reg; 137 int err; 138 139 reg = (addr[0] << 8) | addr[1]; 140 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 141 if (err) 142 return err; 143 144 reg = (addr[2] << 8) | addr[3]; 145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 146 if (err) 147 return err; 148 149 reg = (addr[4] << 8) | addr[5]; 150 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 151 if (err) 152 return err; 153 154 return 0; 155 } 156 157 /* Offset 0x04: Switch Global Control Register */ 158 159 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 160 { 161 u16 val; 162 int err; 163 164 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 165 * the PPU, including re-doing PHY detection and initialization 166 */ 167 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 168 if (err) 169 return err; 170 171 val |= MV88E6XXX_G1_CTL1_SW_RESET; 172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 173 174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 175 if (err) 176 return err; 177 178 err = mv88e6xxx_g1_wait_init_ready(chip); 179 if (err) 180 return err; 181 182 return mv88e6185_g1_wait_ppu_polling(chip); 183 } 184 185 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 186 { 187 u16 val; 188 int err; 189 190 /* Set the SWReset bit 15 */ 191 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 192 if (err) 193 return err; 194 195 val |= MV88E6XXX_G1_CTL1_SW_RESET; 196 197 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 198 if (err) 199 return err; 200 201 return mv88e6xxx_g1_wait_init_ready(chip); 202 } 203 204 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 205 { 206 int err; 207 208 err = mv88e6250_g1_reset(chip); 209 if (err) 210 return err; 211 212 return mv88e6352_g1_wait_ppu_polling(chip); 213 } 214 215 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 216 { 217 u16 val; 218 int err; 219 220 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 221 if (err) 222 return err; 223 224 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 225 226 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 227 if (err) 228 return err; 229 230 return mv88e6185_g1_wait_ppu_polling(chip); 231 } 232 233 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 234 { 235 u16 val; 236 int err; 237 238 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 239 if (err) 240 return err; 241 242 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 243 244 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 245 if (err) 246 return err; 247 248 return mv88e6185_g1_wait_ppu_disabled(chip); 249 } 250 251 /* Offset 0x10: IP-PRI Mapping Register 0 252 * Offset 0x11: IP-PRI Mapping Register 1 253 * Offset 0x12: IP-PRI Mapping Register 2 254 * Offset 0x13: IP-PRI Mapping Register 3 255 * Offset 0x14: IP-PRI Mapping Register 4 256 * Offset 0x15: IP-PRI Mapping Register 5 257 * Offset 0x16: IP-PRI Mapping Register 6 258 * Offset 0x17: IP-PRI Mapping Register 7 259 */ 260 261 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 262 { 263 int err; 264 265 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 266 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 267 if (err) 268 return err; 269 270 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 271 if (err) 272 return err; 273 274 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 275 if (err) 276 return err; 277 278 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 279 if (err) 280 return err; 281 282 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 283 if (err) 284 return err; 285 286 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 287 if (err) 288 return err; 289 290 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 291 if (err) 292 return err; 293 294 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 295 if (err) 296 return err; 297 298 return 0; 299 } 300 301 /* Offset 0x18: IEEE-PRI Register */ 302 303 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 304 { 305 /* Reset the IEEE Tag priorities to defaults */ 306 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 307 } 308 309 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 310 { 311 /* Reset the IEEE Tag priorities to defaults */ 312 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 313 } 314 315 /* Offset 0x1a: Monitor Control */ 316 /* Offset 0x1a: Monitor & MGMT Control on some devices */ 317 318 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 319 { 320 u16 reg; 321 int err; 322 323 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 324 if (err) 325 return err; 326 327 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 328 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 329 330 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 331 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 332 333 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 334 } 335 336 /* Older generations also call this the ARP destination. It has been 337 * generalized in more modern devices such that more than ARP can 338 * egress it 339 */ 340 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 341 { 342 u16 reg; 343 int err; 344 345 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 346 if (err) 347 return err; 348 349 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 350 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 351 352 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 353 } 354 355 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 356 u16 pointer, u8 data) 357 { 358 u16 reg; 359 360 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 361 362 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 363 } 364 365 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 366 { 367 u16 ptr; 368 int err; 369 370 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 371 err = mv88e6390_g1_monitor_write(chip, ptr, port); 372 if (err) 373 return err; 374 375 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 376 err = mv88e6390_g1_monitor_write(chip, ptr, port); 377 if (err) 378 return err; 379 380 return 0; 381 } 382 383 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 384 { 385 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 386 387 return mv88e6390_g1_monitor_write(chip, ptr, port); 388 } 389 390 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 391 { 392 u16 ptr; 393 int err; 394 395 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 396 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 397 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 398 if (err) 399 return err; 400 401 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 402 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 403 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 404 if (err) 405 return err; 406 407 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 408 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 409 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 410 if (err) 411 return err; 412 413 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 414 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 415 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 416 if (err) 417 return err; 418 419 return 0; 420 } 421 422 /* Offset 0x1c: Global Control 2 */ 423 424 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 425 u16 val) 426 { 427 u16 reg; 428 int err; 429 430 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 431 if (err) 432 return err; 433 434 reg &= ~mask; 435 reg |= val & mask; 436 437 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 438 } 439 440 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 441 { 442 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 443 444 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 445 } 446 447 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 448 { 449 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 450 MV88E6085_G1_CTL2_RM_ENABLE, 0); 451 } 452 453 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 454 { 455 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 456 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 457 } 458 459 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 460 { 461 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 462 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 463 } 464 465 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 466 { 467 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 468 MV88E6390_G1_CTL2_HIST_MODE_RX | 469 MV88E6390_G1_CTL2_HIST_MODE_TX); 470 } 471 472 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 473 { 474 return mv88e6xxx_g1_ctl2_mask(chip, 475 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 476 index); 477 } 478 479 /* Offset 0x1d: Statistics Operation 2 */ 480 481 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 482 { 483 return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 484 MV88E6XXX_G1_STATS_OP_BUSY); 485 } 486 487 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 488 { 489 u16 val; 490 int err; 491 492 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 493 if (err) 494 return err; 495 496 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 497 498 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 499 500 return err; 501 } 502 503 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 504 { 505 int err; 506 507 /* Snapshot the hardware statistics counters for this port. */ 508 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 509 MV88E6XXX_G1_STATS_OP_BUSY | 510 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 511 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 512 if (err) 513 return err; 514 515 /* Wait for the snapshotting to complete. */ 516 return mv88e6xxx_g1_stats_wait(chip); 517 } 518 519 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 port = (port + 1) << 5; 522 523 return mv88e6xxx_g1_stats_snapshot(chip, port); 524 } 525 526 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 527 { 528 int err; 529 530 port = (port + 1) << 5; 531 532 /* Snapshot the hardware statistics counters for this port. */ 533 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 534 MV88E6XXX_G1_STATS_OP_BUSY | 535 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 536 if (err) 537 return err; 538 539 /* Wait for the snapshotting to complete. */ 540 return mv88e6xxx_g1_stats_wait(chip); 541 } 542 543 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 544 { 545 u32 value; 546 u16 reg; 547 int err; 548 549 *val = 0; 550 551 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 552 MV88E6XXX_G1_STATS_OP_BUSY | 553 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 554 if (err) 555 return; 556 557 err = mv88e6xxx_g1_stats_wait(chip); 558 if (err) 559 return; 560 561 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 562 if (err) 563 return; 564 565 value = reg << 16; 566 567 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 568 if (err) 569 return; 570 571 *val = value | reg; 572 } 573 574 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 575 { 576 int err; 577 u16 val; 578 579 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 580 if (err) 581 return err; 582 583 /* Keep the histogram mode bits */ 584 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 585 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 586 587 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 588 if (err) 589 return err; 590 591 /* Wait for the flush to complete. */ 592 return mv88e6xxx_g1_stats_wait(chip); 593 } 594