1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Global (1) Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 13 #include "chip.h" 14 #include "global1.h" 15 16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17 { 18 int addr = chip->info->global1_addr; 19 20 return mv88e6xxx_read(chip, addr, reg, val); 21 } 22 23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24 { 25 int addr = chip->info->global1_addr; 26 27 return mv88e6xxx_write(chip, addr, reg, val); 28 } 29 30 int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 31 { 32 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 33 } 34 35 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 36 u16 mask, u16 val) 37 { 38 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 39 mask, val); 40 } 41 42 /* Offset 0x00: Switch Global Status Register */ 43 44 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 45 { 46 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 47 MV88E6185_G1_STS_PPU_STATE_MASK, 48 MV88E6185_G1_STS_PPU_STATE_DISABLED); 49 } 50 51 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 52 { 53 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 54 MV88E6185_G1_STS_PPU_STATE_MASK, 55 MV88E6185_G1_STS_PPU_STATE_POLLING); 56 } 57 58 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 59 { 60 u16 state; 61 int i, err; 62 63 for (i = 0; i < 16; ++i) { 64 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 65 if (err) 66 return err; 67 68 /* Check the value of the PPUState (or InitState) bit 15 */ 69 if (state & MV88E6352_G1_STS_PPU_STATE) 70 return 0; 71 72 usleep_range(1000, 2000); 73 } 74 75 return -ETIMEDOUT; 76 } 77 78 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 79 { 80 const unsigned long timeout = jiffies + 1 * HZ; 81 u16 val; 82 int err; 83 84 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 85 * is set to a one when all units inside the device (ATU, VTU, etc.) 86 * have finished their initialization and are ready to accept frames. 87 */ 88 while (time_before(jiffies, timeout)) { 89 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 90 if (err) 91 return err; 92 93 if (val & MV88E6XXX_G1_STS_INIT_READY) 94 break; 95 96 usleep_range(1000, 2000); 97 } 98 99 if (time_after(jiffies, timeout)) 100 return -ETIMEDOUT; 101 102 return 0; 103 } 104 105 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 106 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 107 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 108 */ 109 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 110 { 111 u16 reg; 112 int err; 113 114 reg = (addr[0] << 8) | addr[1]; 115 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 116 if (err) 117 return err; 118 119 reg = (addr[2] << 8) | addr[3]; 120 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 121 if (err) 122 return err; 123 124 reg = (addr[4] << 8) | addr[5]; 125 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 126 if (err) 127 return err; 128 129 return 0; 130 } 131 132 /* Offset 0x04: Switch Global Control Register */ 133 134 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 135 { 136 u16 val; 137 int err; 138 139 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 140 * the PPU, including re-doing PHY detection and initialization 141 */ 142 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 143 if (err) 144 return err; 145 146 val |= MV88E6XXX_G1_CTL1_SW_RESET; 147 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 148 149 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 150 if (err) 151 return err; 152 153 err = mv88e6xxx_g1_wait_init_ready(chip); 154 if (err) 155 return err; 156 157 return mv88e6185_g1_wait_ppu_polling(chip); 158 } 159 160 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 161 { 162 u16 val; 163 int err; 164 165 /* Set the SWReset bit 15 */ 166 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 167 if (err) 168 return err; 169 170 val |= MV88E6XXX_G1_CTL1_SW_RESET; 171 172 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 173 if (err) 174 return err; 175 176 return mv88e6xxx_g1_wait_init_ready(chip); 177 } 178 179 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 180 { 181 int err; 182 183 err = mv88e6250_g1_reset(chip); 184 if (err) 185 return err; 186 187 return mv88e6352_g1_wait_ppu_polling(chip); 188 } 189 190 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 191 { 192 u16 val; 193 int err; 194 195 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 196 if (err) 197 return err; 198 199 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 200 201 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 202 if (err) 203 return err; 204 205 return mv88e6185_g1_wait_ppu_polling(chip); 206 } 207 208 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 209 { 210 u16 val; 211 int err; 212 213 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 214 if (err) 215 return err; 216 217 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 218 219 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 220 if (err) 221 return err; 222 223 return mv88e6185_g1_wait_ppu_disabled(chip); 224 } 225 226 /* Offset 0x10: IP-PRI Mapping Register 0 227 * Offset 0x11: IP-PRI Mapping Register 1 228 * Offset 0x12: IP-PRI Mapping Register 2 229 * Offset 0x13: IP-PRI Mapping Register 3 230 * Offset 0x14: IP-PRI Mapping Register 4 231 * Offset 0x15: IP-PRI Mapping Register 5 232 * Offset 0x16: IP-PRI Mapping Register 6 233 * Offset 0x17: IP-PRI Mapping Register 7 234 */ 235 236 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 237 { 238 int err; 239 240 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 241 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 242 if (err) 243 return err; 244 245 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 246 if (err) 247 return err; 248 249 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 250 if (err) 251 return err; 252 253 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 254 if (err) 255 return err; 256 257 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 258 if (err) 259 return err; 260 261 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 262 if (err) 263 return err; 264 265 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 266 if (err) 267 return err; 268 269 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 270 if (err) 271 return err; 272 273 return 0; 274 } 275 276 /* Offset 0x18: IEEE-PRI Register */ 277 278 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 279 { 280 /* Reset the IEEE Tag priorities to defaults */ 281 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 282 } 283 284 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 285 { 286 /* Reset the IEEE Tag priorities to defaults */ 287 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 288 } 289 290 /* Offset 0x1a: Monitor Control */ 291 /* Offset 0x1a: Monitor & MGMT Control on some devices */ 292 293 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 294 { 295 u16 reg; 296 int err; 297 298 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 299 if (err) 300 return err; 301 302 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 303 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 304 305 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 306 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 307 308 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 309 } 310 311 /* Older generations also call this the ARP destination. It has been 312 * generalized in more modern devices such that more than ARP can 313 * egress it 314 */ 315 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 316 { 317 u16 reg; 318 int err; 319 320 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 321 if (err) 322 return err; 323 324 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 325 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 326 327 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 328 } 329 330 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 331 u16 pointer, u8 data) 332 { 333 u16 reg; 334 335 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 336 337 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 338 } 339 340 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 341 { 342 u16 ptr; 343 int err; 344 345 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 346 err = mv88e6390_g1_monitor_write(chip, ptr, port); 347 if (err) 348 return err; 349 350 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 351 err = mv88e6390_g1_monitor_write(chip, ptr, port); 352 if (err) 353 return err; 354 355 return 0; 356 } 357 358 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 359 { 360 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 361 362 return mv88e6390_g1_monitor_write(chip, ptr, port); 363 } 364 365 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 366 { 367 u16 ptr; 368 int err; 369 370 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 371 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 372 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 373 if (err) 374 return err; 375 376 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 377 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 378 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 379 if (err) 380 return err; 381 382 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 383 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 384 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 385 if (err) 386 return err; 387 388 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 389 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 390 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 391 if (err) 392 return err; 393 394 return 0; 395 } 396 397 /* Offset 0x1c: Global Control 2 */ 398 399 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 400 u16 val) 401 { 402 u16 reg; 403 int err; 404 405 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 406 if (err) 407 return err; 408 409 reg &= ~mask; 410 reg |= val & mask; 411 412 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 413 } 414 415 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 416 { 417 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 418 419 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 420 } 421 422 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 423 { 424 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 425 MV88E6085_G1_CTL2_RM_ENABLE, 0); 426 } 427 428 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 429 { 430 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 431 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 432 } 433 434 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 435 { 436 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 437 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 438 } 439 440 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 441 { 442 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 443 MV88E6390_G1_CTL2_HIST_MODE_RX | 444 MV88E6390_G1_CTL2_HIST_MODE_TX); 445 } 446 447 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 448 { 449 return mv88e6xxx_g1_ctl2_mask(chip, 450 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 451 index); 452 } 453 454 /* Offset 0x1d: Statistics Operation 2 */ 455 456 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 457 { 458 return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 459 MV88E6XXX_G1_STATS_OP_BUSY); 460 } 461 462 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 463 { 464 u16 val; 465 int err; 466 467 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 468 if (err) 469 return err; 470 471 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 472 473 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 474 475 return err; 476 } 477 478 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 479 { 480 int err; 481 482 /* Snapshot the hardware statistics counters for this port. */ 483 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 484 MV88E6XXX_G1_STATS_OP_BUSY | 485 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 486 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 487 if (err) 488 return err; 489 490 /* Wait for the snapshotting to complete. */ 491 return mv88e6xxx_g1_stats_wait(chip); 492 } 493 494 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 495 { 496 port = (port + 1) << 5; 497 498 return mv88e6xxx_g1_stats_snapshot(chip, port); 499 } 500 501 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 502 { 503 int err; 504 505 port = (port + 1) << 5; 506 507 /* Snapshot the hardware statistics counters for this port. */ 508 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 509 MV88E6XXX_G1_STATS_OP_BUSY | 510 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 511 if (err) 512 return err; 513 514 /* Wait for the snapshotting to complete. */ 515 return mv88e6xxx_g1_stats_wait(chip); 516 } 517 518 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 519 { 520 u32 value; 521 u16 reg; 522 int err; 523 524 *val = 0; 525 526 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 527 MV88E6XXX_G1_STATS_OP_BUSY | 528 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 529 if (err) 530 return; 531 532 err = mv88e6xxx_g1_stats_wait(chip); 533 if (err) 534 return; 535 536 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 537 if (err) 538 return; 539 540 value = reg << 16; 541 542 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 543 if (err) 544 return; 545 546 *val = value | reg; 547 } 548 549 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 550 { 551 int err; 552 u16 val; 553 554 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 555 if (err) 556 return err; 557 558 /* Keep the histogram mode bits */ 559 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 560 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 561 562 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 563 if (err) 564 return err; 565 566 /* Wait for the flush to complete. */ 567 return mv88e6xxx_g1_stats_wait(chip); 568 } 569