1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Global (1) Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 13 #include "chip.h" 14 #include "global1.h" 15 16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17 { 18 int addr = chip->info->global1_addr; 19 20 return mv88e6xxx_read(chip, addr, reg, val); 21 } 22 23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24 { 25 int addr = chip->info->global1_addr; 26 27 return mv88e6xxx_write(chip, addr, reg, val); 28 } 29 30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 31 bit, int val) 32 { 33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 34 bit, val); 35 } 36 37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 38 u16 mask, u16 val) 39 { 40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 41 mask, val); 42 } 43 44 /* Offset 0x00: Switch Global Status Register */ 45 46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 47 { 48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 49 MV88E6185_G1_STS_PPU_STATE_MASK, 50 MV88E6185_G1_STS_PPU_STATE_DISABLED); 51 } 52 53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 54 { 55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 56 MV88E6185_G1_STS_PPU_STATE_MASK, 57 MV88E6185_G1_STS_PPU_STATE_POLLING); 58 } 59 60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 61 { 62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 63 64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 65 } 66 67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 68 { 69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 70 71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 72 * is set to a one when all units inside the device (ATU, VTU, etc.) 73 * have finished their initialization and are ready to accept frames. 74 */ 75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 76 } 77 78 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 79 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 80 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 81 */ 82 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 83 { 84 u16 reg; 85 int err; 86 87 reg = (addr[0] << 8) | addr[1]; 88 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 89 if (err) 90 return err; 91 92 reg = (addr[2] << 8) | addr[3]; 93 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 94 if (err) 95 return err; 96 97 reg = (addr[4] << 8) | addr[5]; 98 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 99 if (err) 100 return err; 101 102 return 0; 103 } 104 105 /* Offset 0x04: Switch Global Control Register */ 106 107 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 108 { 109 u16 val; 110 int err; 111 112 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 113 * the PPU, including re-doing PHY detection and initialization 114 */ 115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 116 if (err) 117 return err; 118 119 val |= MV88E6XXX_G1_CTL1_SW_RESET; 120 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 121 122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 123 if (err) 124 return err; 125 126 err = mv88e6xxx_g1_wait_init_ready(chip); 127 if (err) 128 return err; 129 130 return mv88e6185_g1_wait_ppu_polling(chip); 131 } 132 133 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 134 { 135 u16 val; 136 int err; 137 138 /* Set the SWReset bit 15 */ 139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 140 if (err) 141 return err; 142 143 val |= MV88E6XXX_G1_CTL1_SW_RESET; 144 145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 146 if (err) 147 return err; 148 149 return mv88e6xxx_g1_wait_init_ready(chip); 150 } 151 152 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 153 { 154 int err; 155 156 err = mv88e6250_g1_reset(chip); 157 if (err) 158 return err; 159 160 return mv88e6352_g1_wait_ppu_polling(chip); 161 } 162 163 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 164 { 165 u16 val; 166 int err; 167 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 169 if (err) 170 return err; 171 172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 173 174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 175 if (err) 176 return err; 177 178 return mv88e6185_g1_wait_ppu_polling(chip); 179 } 180 181 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 182 { 183 u16 val; 184 int err; 185 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 187 if (err) 188 return err; 189 190 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 191 192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 193 if (err) 194 return err; 195 196 return mv88e6185_g1_wait_ppu_disabled(chip); 197 } 198 199 int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) 200 { 201 u16 val; 202 int err; 203 204 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 205 if (err) 206 return err; 207 208 val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632; 209 210 if (mtu > 1518) 211 val |= MV88E6185_G1_CTL1_MAX_FRAME_1632; 212 213 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 214 } 215 216 /* Offset 0x10: IP-PRI Mapping Register 0 217 * Offset 0x11: IP-PRI Mapping Register 1 218 * Offset 0x12: IP-PRI Mapping Register 2 219 * Offset 0x13: IP-PRI Mapping Register 3 220 * Offset 0x14: IP-PRI Mapping Register 4 221 * Offset 0x15: IP-PRI Mapping Register 5 222 * Offset 0x16: IP-PRI Mapping Register 6 223 * Offset 0x17: IP-PRI Mapping Register 7 224 */ 225 226 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 227 { 228 int err; 229 230 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 231 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 232 if (err) 233 return err; 234 235 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 236 if (err) 237 return err; 238 239 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 240 if (err) 241 return err; 242 243 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 244 if (err) 245 return err; 246 247 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 248 if (err) 249 return err; 250 251 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 252 if (err) 253 return err; 254 255 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 256 if (err) 257 return err; 258 259 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 260 if (err) 261 return err; 262 263 return 0; 264 } 265 266 /* Offset 0x18: IEEE-PRI Register */ 267 268 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 269 { 270 /* Reset the IEEE Tag priorities to defaults */ 271 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 272 } 273 274 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 275 { 276 /* Reset the IEEE Tag priorities to defaults */ 277 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 278 } 279 280 /* Offset 0x1a: Monitor Control */ 281 /* Offset 0x1a: Monitor & MGMT Control on some devices */ 282 283 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 284 enum mv88e6xxx_egress_direction direction, 285 int port) 286 { 287 int *dest_port_chip; 288 u16 reg; 289 int err; 290 291 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 292 if (err) 293 return err; 294 295 switch (direction) { 296 case MV88E6XXX_EGRESS_DIR_INGRESS: 297 dest_port_chip = &chip->ingress_dest_port; 298 reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK; 299 reg |= port << 300 __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK); 301 break; 302 case MV88E6XXX_EGRESS_DIR_EGRESS: 303 dest_port_chip = &chip->egress_dest_port; 304 reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK; 305 reg |= port << 306 __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 307 break; 308 default: 309 return -EINVAL; 310 } 311 312 err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 313 if (!err) 314 *dest_port_chip = port; 315 316 return err; 317 } 318 319 /* Older generations also call this the ARP destination. It has been 320 * generalized in more modern devices such that more than ARP can 321 * egress it 322 */ 323 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 324 { 325 u16 reg; 326 int err; 327 328 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 329 if (err) 330 return err; 331 332 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 333 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 334 335 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 336 } 337 338 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 339 u16 pointer, u8 data) 340 { 341 u16 reg; 342 343 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 344 345 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 346 } 347 348 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 349 enum mv88e6xxx_egress_direction direction, 350 int port) 351 { 352 int *dest_port_chip; 353 u16 ptr; 354 int err; 355 356 switch (direction) { 357 case MV88E6XXX_EGRESS_DIR_INGRESS: 358 dest_port_chip = &chip->ingress_dest_port; 359 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 360 break; 361 case MV88E6XXX_EGRESS_DIR_EGRESS: 362 dest_port_chip = &chip->egress_dest_port; 363 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 364 break; 365 default: 366 return -EINVAL; 367 } 368 369 err = mv88e6390_g1_monitor_write(chip, ptr, port); 370 if (!err) 371 *dest_port_chip = port; 372 373 return err; 374 } 375 376 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 377 { 378 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 379 380 /* Use the default high priority for management frames sent to 381 * the CPU. 382 */ 383 port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; 384 385 return mv88e6390_g1_monitor_write(chip, ptr, port); 386 } 387 388 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 389 { 390 u16 ptr; 391 int err; 392 393 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 394 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 395 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 396 if (err) 397 return err; 398 399 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 400 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 401 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 402 if (err) 403 return err; 404 405 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 406 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 407 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 408 if (err) 409 return err; 410 411 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 412 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 413 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 414 if (err) 415 return err; 416 417 return 0; 418 } 419 420 /* Offset 0x1c: Global Control 2 */ 421 422 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 423 u16 val) 424 { 425 u16 reg; 426 int err; 427 428 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 429 if (err) 430 return err; 431 432 reg &= ~mask; 433 reg |= val & mask; 434 435 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 436 } 437 438 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 439 { 440 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 441 442 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 443 } 444 445 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 446 { 447 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 448 MV88E6085_G1_CTL2_RM_ENABLE, 0); 449 } 450 451 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 452 { 453 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 454 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 455 } 456 457 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 458 { 459 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 460 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 461 } 462 463 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 464 { 465 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 466 MV88E6390_G1_CTL2_HIST_MODE_RX | 467 MV88E6390_G1_CTL2_HIST_MODE_TX); 468 } 469 470 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 471 { 472 return mv88e6xxx_g1_ctl2_mask(chip, 473 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 474 index); 475 } 476 477 /* Offset 0x1d: Statistics Operation 2 */ 478 479 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 480 { 481 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 482 483 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 484 } 485 486 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 487 { 488 u16 val; 489 int err; 490 491 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 492 if (err) 493 return err; 494 495 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 496 497 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 498 499 return err; 500 } 501 502 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 503 { 504 int err; 505 506 /* Snapshot the hardware statistics counters for this port. */ 507 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 508 MV88E6XXX_G1_STATS_OP_BUSY | 509 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 510 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 511 if (err) 512 return err; 513 514 /* Wait for the snapshotting to complete. */ 515 return mv88e6xxx_g1_stats_wait(chip); 516 } 517 518 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 519 { 520 port = (port + 1) << 5; 521 522 return mv88e6xxx_g1_stats_snapshot(chip, port); 523 } 524 525 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 526 { 527 int err; 528 529 port = (port + 1) << 5; 530 531 /* Snapshot the hardware statistics counters for this port. */ 532 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 533 MV88E6XXX_G1_STATS_OP_BUSY | 534 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 535 if (err) 536 return err; 537 538 /* Wait for the snapshotting to complete. */ 539 return mv88e6xxx_g1_stats_wait(chip); 540 } 541 542 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 543 { 544 u32 value; 545 u16 reg; 546 int err; 547 548 *val = 0; 549 550 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 551 MV88E6XXX_G1_STATS_OP_BUSY | 552 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 553 if (err) 554 return; 555 556 err = mv88e6xxx_g1_stats_wait(chip); 557 if (err) 558 return; 559 560 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 561 if (err) 562 return; 563 564 value = reg << 16; 565 566 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 567 if (err) 568 return; 569 570 *val = value | reg; 571 } 572 573 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 574 { 575 int err; 576 u16 val; 577 578 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 579 if (err) 580 return err; 581 582 /* Keep the histogram mode bits */ 583 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 584 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 585 586 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 587 if (err) 588 return err; 589 590 /* Wait for the flush to complete. */ 591 return mv88e6xxx_g1_stats_wait(chip); 592 } 593