1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88E6xxx Switch Global (1) Registers support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 8 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9 */ 10 11 #include <linux/bitfield.h> 12 13 #include "chip.h" 14 #include "global1.h" 15 16 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17 { 18 int addr = chip->info->global1_addr; 19 20 return mv88e6xxx_read(chip, addr, reg, val); 21 } 22 23 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24 { 25 int addr = chip->info->global1_addr; 26 27 return mv88e6xxx_write(chip, addr, reg, val); 28 } 29 30 int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 31 bit, int val) 32 { 33 return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 34 bit, val); 35 } 36 37 int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 38 u16 mask, u16 val) 39 { 40 return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 41 mask, val); 42 } 43 44 /* Offset 0x00: Switch Global Status Register */ 45 46 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 47 { 48 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 49 MV88E6185_G1_STS_PPU_STATE_MASK, 50 MV88E6185_G1_STS_PPU_STATE_DISABLED); 51 } 52 53 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 54 { 55 return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 56 MV88E6185_G1_STS_PPU_STATE_MASK, 57 MV88E6185_G1_STS_PPU_STATE_POLLING); 58 } 59 60 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 61 { 62 int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 63 64 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 65 } 66 67 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 68 { 69 int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 70 71 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 72 * is set to a one when all units inside the device (ATU, VTU, etc.) 73 * have finished their initialization and are ready to accept frames. 74 */ 75 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 76 } 77 78 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 79 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 80 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 81 */ 82 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 83 { 84 u16 reg; 85 int err; 86 87 reg = (addr[0] << 8) | addr[1]; 88 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 89 if (err) 90 return err; 91 92 reg = (addr[2] << 8) | addr[3]; 93 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 94 if (err) 95 return err; 96 97 reg = (addr[4] << 8) | addr[5]; 98 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 99 if (err) 100 return err; 101 102 return 0; 103 } 104 105 /* Offset 0x04: Switch Global Control Register */ 106 107 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 108 { 109 u16 val; 110 int err; 111 112 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 113 * the PPU, including re-doing PHY detection and initialization 114 */ 115 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 116 if (err) 117 return err; 118 119 val |= MV88E6XXX_G1_CTL1_SW_RESET; 120 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 121 122 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 123 if (err) 124 return err; 125 126 err = mv88e6xxx_g1_wait_init_ready(chip); 127 if (err) 128 return err; 129 130 return mv88e6185_g1_wait_ppu_polling(chip); 131 } 132 133 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 134 { 135 u16 val; 136 int err; 137 138 /* Set the SWReset bit 15 */ 139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 140 if (err) 141 return err; 142 143 val |= MV88E6XXX_G1_CTL1_SW_RESET; 144 145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 146 if (err) 147 return err; 148 149 return mv88e6xxx_g1_wait_init_ready(chip); 150 } 151 152 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 153 { 154 int err; 155 156 err = mv88e6250_g1_reset(chip); 157 if (err) 158 return err; 159 160 return mv88e6352_g1_wait_ppu_polling(chip); 161 } 162 163 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 164 { 165 u16 val; 166 int err; 167 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 169 if (err) 170 return err; 171 172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 173 174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 175 if (err) 176 return err; 177 178 return mv88e6185_g1_wait_ppu_polling(chip); 179 } 180 181 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 182 { 183 u16 val; 184 int err; 185 186 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 187 if (err) 188 return err; 189 190 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 191 192 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 193 if (err) 194 return err; 195 196 return mv88e6185_g1_wait_ppu_disabled(chip); 197 } 198 199 /* Offset 0x10: IP-PRI Mapping Register 0 200 * Offset 0x11: IP-PRI Mapping Register 1 201 * Offset 0x12: IP-PRI Mapping Register 2 202 * Offset 0x13: IP-PRI Mapping Register 3 203 * Offset 0x14: IP-PRI Mapping Register 4 204 * Offset 0x15: IP-PRI Mapping Register 5 205 * Offset 0x16: IP-PRI Mapping Register 6 206 * Offset 0x17: IP-PRI Mapping Register 7 207 */ 208 209 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 210 { 211 int err; 212 213 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 215 if (err) 216 return err; 217 218 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 219 if (err) 220 return err; 221 222 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 223 if (err) 224 return err; 225 226 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 227 if (err) 228 return err; 229 230 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 231 if (err) 232 return err; 233 234 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 235 if (err) 236 return err; 237 238 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 239 if (err) 240 return err; 241 242 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 243 if (err) 244 return err; 245 246 return 0; 247 } 248 249 /* Offset 0x18: IEEE-PRI Register */ 250 251 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 252 { 253 /* Reset the IEEE Tag priorities to defaults */ 254 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 255 } 256 257 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 258 { 259 /* Reset the IEEE Tag priorities to defaults */ 260 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 261 } 262 263 /* Offset 0x1a: Monitor Control */ 264 /* Offset 0x1a: Monitor & MGMT Control on some devices */ 265 266 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 267 { 268 u16 reg; 269 int err; 270 271 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 272 if (err) 273 return err; 274 275 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 276 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 277 278 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 279 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 280 281 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 282 } 283 284 /* Older generations also call this the ARP destination. It has been 285 * generalized in more modern devices such that more than ARP can 286 * egress it 287 */ 288 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 289 { 290 u16 reg; 291 int err; 292 293 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 294 if (err) 295 return err; 296 297 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 298 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 299 300 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 301 } 302 303 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 304 u16 pointer, u8 data) 305 { 306 u16 reg; 307 308 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 309 310 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 311 } 312 313 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 314 { 315 u16 ptr; 316 int err; 317 318 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 319 err = mv88e6390_g1_monitor_write(chip, ptr, port); 320 if (err) 321 return err; 322 323 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 324 err = mv88e6390_g1_monitor_write(chip, ptr, port); 325 if (err) 326 return err; 327 328 return 0; 329 } 330 331 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 332 { 333 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 334 335 return mv88e6390_g1_monitor_write(chip, ptr, port); 336 } 337 338 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 339 { 340 u16 ptr; 341 int err; 342 343 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 344 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 345 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 346 if (err) 347 return err; 348 349 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 350 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 351 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 352 if (err) 353 return err; 354 355 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 356 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 357 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 358 if (err) 359 return err; 360 361 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 362 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 363 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 364 if (err) 365 return err; 366 367 return 0; 368 } 369 370 /* Offset 0x1c: Global Control 2 */ 371 372 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 373 u16 val) 374 { 375 u16 reg; 376 int err; 377 378 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 379 if (err) 380 return err; 381 382 reg &= ~mask; 383 reg |= val & mask; 384 385 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 386 } 387 388 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 389 { 390 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 391 392 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 393 } 394 395 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 396 { 397 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 398 MV88E6085_G1_CTL2_RM_ENABLE, 0); 399 } 400 401 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 402 { 403 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 404 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 405 } 406 407 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 408 { 409 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 410 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 411 } 412 413 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 414 { 415 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 416 MV88E6390_G1_CTL2_HIST_MODE_RX | 417 MV88E6390_G1_CTL2_HIST_MODE_TX); 418 } 419 420 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 421 { 422 return mv88e6xxx_g1_ctl2_mask(chip, 423 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 424 index); 425 } 426 427 /* Offset 0x1d: Statistics Operation 2 */ 428 429 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 430 { 431 int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 432 433 return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 434 } 435 436 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 437 { 438 u16 val; 439 int err; 440 441 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 442 if (err) 443 return err; 444 445 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 446 447 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 448 449 return err; 450 } 451 452 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 453 { 454 int err; 455 456 /* Snapshot the hardware statistics counters for this port. */ 457 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 458 MV88E6XXX_G1_STATS_OP_BUSY | 459 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 460 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 461 if (err) 462 return err; 463 464 /* Wait for the snapshotting to complete. */ 465 return mv88e6xxx_g1_stats_wait(chip); 466 } 467 468 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 469 { 470 port = (port + 1) << 5; 471 472 return mv88e6xxx_g1_stats_snapshot(chip, port); 473 } 474 475 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 476 { 477 int err; 478 479 port = (port + 1) << 5; 480 481 /* Snapshot the hardware statistics counters for this port. */ 482 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 483 MV88E6XXX_G1_STATS_OP_BUSY | 484 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 485 if (err) 486 return err; 487 488 /* Wait for the snapshotting to complete. */ 489 return mv88e6xxx_g1_stats_wait(chip); 490 } 491 492 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 493 { 494 u32 value; 495 u16 reg; 496 int err; 497 498 *val = 0; 499 500 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 501 MV88E6XXX_G1_STATS_OP_BUSY | 502 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 503 if (err) 504 return; 505 506 err = mv88e6xxx_g1_stats_wait(chip); 507 if (err) 508 return; 509 510 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 511 if (err) 512 return; 513 514 value = reg << 16; 515 516 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 517 if (err) 518 return; 519 520 *val = value | reg; 521 } 522 523 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 524 { 525 int err; 526 u16 val; 527 528 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 529 if (err) 530 return err; 531 532 /* Keep the histogram mode bits */ 533 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 534 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 535 536 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 537 if (err) 538 return err; 539 540 /* Wait for the flush to complete. */ 541 return mv88e6xxx_g1_stats_wait(chip); 542 } 543