1 /* 2 * Marvell 88E6xxx Switch Global (1) Registers support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 */ 14 15 #include <linux/bitfield.h> 16 17 #include "chip.h" 18 #include "global1.h" 19 20 int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 21 { 22 int addr = chip->info->global1_addr; 23 24 return mv88e6xxx_read(chip, addr, reg, val); 25 } 26 27 int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 28 { 29 int addr = chip->info->global1_addr; 30 31 return mv88e6xxx_write(chip, addr, reg, val); 32 } 33 34 int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 35 { 36 return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 37 } 38 39 /* Offset 0x00: Switch Global Status Register */ 40 41 static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 42 { 43 u16 state; 44 int i, err; 45 46 for (i = 0; i < 16; i++) { 47 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 48 if (err) 49 return err; 50 51 /* Check the value of the PPUState bits 15:14 */ 52 state &= MV88E6185_G1_STS_PPU_STATE_MASK; 53 if (state != MV88E6185_G1_STS_PPU_STATE_POLLING) 54 return 0; 55 56 usleep_range(1000, 2000); 57 } 58 59 return -ETIMEDOUT; 60 } 61 62 static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 63 { 64 u16 state; 65 int i, err; 66 67 for (i = 0; i < 16; ++i) { 68 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 69 if (err) 70 return err; 71 72 /* Check the value of the PPUState bits 15:14 */ 73 state &= MV88E6185_G1_STS_PPU_STATE_MASK; 74 if (state == MV88E6185_G1_STS_PPU_STATE_POLLING) 75 return 0; 76 77 usleep_range(1000, 2000); 78 } 79 80 return -ETIMEDOUT; 81 } 82 83 static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 84 { 85 u16 state; 86 int i, err; 87 88 for (i = 0; i < 16; ++i) { 89 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 90 if (err) 91 return err; 92 93 /* Check the value of the PPUState (or InitState) bit 15 */ 94 if (state & MV88E6352_G1_STS_PPU_STATE) 95 return 0; 96 97 usleep_range(1000, 2000); 98 } 99 100 return -ETIMEDOUT; 101 } 102 103 static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 104 { 105 const unsigned long timeout = jiffies + 1 * HZ; 106 u16 val; 107 int err; 108 109 /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 110 * is set to a one when all units inside the device (ATU, VTU, etc.) 111 * have finished their initialization and are ready to accept frames. 112 */ 113 while (time_before(jiffies, timeout)) { 114 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 115 if (err) 116 return err; 117 118 if (val & MV88E6XXX_G1_STS_INIT_READY) 119 break; 120 121 usleep_range(1000, 2000); 122 } 123 124 if (time_after(jiffies, timeout)) 125 return -ETIMEDOUT; 126 127 return 0; 128 } 129 130 /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 131 * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 132 * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 133 */ 134 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 135 { 136 u16 reg; 137 int err; 138 139 reg = (addr[0] << 8) | addr[1]; 140 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 141 if (err) 142 return err; 143 144 reg = (addr[2] << 8) | addr[3]; 145 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 146 if (err) 147 return err; 148 149 reg = (addr[4] << 8) | addr[5]; 150 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 151 if (err) 152 return err; 153 154 return 0; 155 } 156 157 /* Offset 0x04: Switch Global Control Register */ 158 159 int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 160 { 161 u16 val; 162 int err; 163 164 /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 165 * the PPU, including re-doing PHY detection and initialization 166 */ 167 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 168 if (err) 169 return err; 170 171 val |= MV88E6XXX_G1_CTL1_SW_RESET; 172 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 173 174 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 175 if (err) 176 return err; 177 178 err = mv88e6xxx_g1_wait_init_ready(chip); 179 if (err) 180 return err; 181 182 return mv88e6185_g1_wait_ppu_polling(chip); 183 } 184 185 int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 186 { 187 u16 val; 188 int err; 189 190 /* Set the SWReset bit 15 */ 191 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 192 if (err) 193 return err; 194 195 val |= MV88E6XXX_G1_CTL1_SW_RESET; 196 197 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 198 if (err) 199 return err; 200 201 return mv88e6xxx_g1_wait_init_ready(chip); 202 } 203 204 int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 205 { 206 u16 val; 207 int err; 208 209 /* Set the SWReset bit 15 */ 210 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 211 if (err) 212 return err; 213 214 val |= MV88E6XXX_G1_CTL1_SW_RESET; 215 216 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 217 if (err) 218 return err; 219 220 err = mv88e6xxx_g1_wait_init_ready(chip); 221 if (err) 222 return err; 223 224 return mv88e6352_g1_wait_ppu_polling(chip); 225 } 226 227 int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 228 { 229 u16 val; 230 int err; 231 232 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 233 if (err) 234 return err; 235 236 val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 237 238 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 239 if (err) 240 return err; 241 242 return mv88e6185_g1_wait_ppu_polling(chip); 243 } 244 245 int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 246 { 247 u16 val; 248 int err; 249 250 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 251 if (err) 252 return err; 253 254 val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 255 256 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 257 if (err) 258 return err; 259 260 return mv88e6185_g1_wait_ppu_disabled(chip); 261 } 262 263 /* Offset 0x10: IP-PRI Mapping Register 0 264 * Offset 0x11: IP-PRI Mapping Register 1 265 * Offset 0x12: IP-PRI Mapping Register 2 266 * Offset 0x13: IP-PRI Mapping Register 3 267 * Offset 0x14: IP-PRI Mapping Register 4 268 * Offset 0x15: IP-PRI Mapping Register 5 269 * Offset 0x16: IP-PRI Mapping Register 6 270 * Offset 0x17: IP-PRI Mapping Register 7 271 */ 272 273 int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 274 { 275 int err; 276 277 /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 278 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 279 if (err) 280 return err; 281 282 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 283 if (err) 284 return err; 285 286 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 287 if (err) 288 return err; 289 290 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 291 if (err) 292 return err; 293 294 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 295 if (err) 296 return err; 297 298 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 299 if (err) 300 return err; 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 303 if (err) 304 return err; 305 306 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 307 if (err) 308 return err; 309 310 return 0; 311 } 312 313 /* Offset 0x18: IEEE-PRI Register */ 314 315 int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 316 { 317 /* Reset the IEEE Tag priorities to defaults */ 318 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 319 } 320 321 int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 322 { 323 /* Reset the IEEE Tag priorities to defaults */ 324 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 325 } 326 327 /* Offset 0x1a: Monitor Control */ 328 /* Offset 0x1a: Monitor & MGMT Control on some devices */ 329 330 int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 331 { 332 u16 reg; 333 int err; 334 335 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 336 if (err) 337 return err; 338 339 reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 340 MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 341 342 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 343 port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 344 345 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 346 } 347 348 /* Older generations also call this the ARP destination. It has been 349 * generalized in more modern devices such that more than ARP can 350 * egress it 351 */ 352 int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 353 { 354 u16 reg; 355 int err; 356 357 err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 358 if (err) 359 return err; 360 361 reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 362 reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 363 364 return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 365 } 366 367 static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 368 u16 pointer, u8 data) 369 { 370 u16 reg; 371 372 reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 373 374 return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 375 } 376 377 int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 378 { 379 u16 ptr; 380 int err; 381 382 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 383 err = mv88e6390_g1_monitor_write(chip, ptr, port); 384 if (err) 385 return err; 386 387 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 388 err = mv88e6390_g1_monitor_write(chip, ptr, port); 389 if (err) 390 return err; 391 392 return 0; 393 } 394 395 int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 396 { 397 u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 398 399 return mv88e6390_g1_monitor_write(chip, ptr, port); 400 } 401 402 int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 403 { 404 u16 ptr; 405 int err; 406 407 /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 408 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 409 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 410 if (err) 411 return err; 412 413 /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 414 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 415 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 416 if (err) 417 return err; 418 419 /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 420 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 421 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 422 if (err) 423 return err; 424 425 /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 426 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 427 err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 428 if (err) 429 return err; 430 431 return 0; 432 } 433 434 /* Offset 0x1c: Global Control 2 */ 435 436 static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 437 u16 val) 438 { 439 u16 reg; 440 int err; 441 442 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 443 if (err) 444 return err; 445 446 reg &= ~mask; 447 reg |= val & mask; 448 449 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 450 } 451 452 int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 453 { 454 const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 455 456 return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 457 } 458 459 int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 460 { 461 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 462 MV88E6085_G1_CTL2_RM_ENABLE, 0); 463 } 464 465 int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 466 { 467 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 468 MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 469 } 470 471 int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 472 { 473 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 474 MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 475 } 476 477 int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 478 { 479 return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 480 MV88E6390_G1_CTL2_HIST_MODE_RX | 481 MV88E6390_G1_CTL2_HIST_MODE_TX); 482 } 483 484 int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 485 { 486 return mv88e6xxx_g1_ctl2_mask(chip, 487 MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 488 index); 489 } 490 491 /* Offset 0x1d: Statistics Operation 2 */ 492 493 static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 494 { 495 return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 496 MV88E6XXX_G1_STATS_OP_BUSY); 497 } 498 499 int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 500 { 501 u16 val; 502 int err; 503 504 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 505 if (err) 506 return err; 507 508 val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 509 510 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 511 512 return err; 513 } 514 515 int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 516 { 517 int err; 518 519 /* Snapshot the hardware statistics counters for this port. */ 520 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 521 MV88E6XXX_G1_STATS_OP_BUSY | 522 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 523 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 524 if (err) 525 return err; 526 527 /* Wait for the snapshotting to complete. */ 528 return mv88e6xxx_g1_stats_wait(chip); 529 } 530 531 int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 532 { 533 port = (port + 1) << 5; 534 535 return mv88e6xxx_g1_stats_snapshot(chip, port); 536 } 537 538 int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 539 { 540 int err; 541 542 port = (port + 1) << 5; 543 544 /* Snapshot the hardware statistics counters for this port. */ 545 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 546 MV88E6XXX_G1_STATS_OP_BUSY | 547 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 548 if (err) 549 return err; 550 551 /* Wait for the snapshotting to complete. */ 552 return mv88e6xxx_g1_stats_wait(chip); 553 } 554 555 void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 556 { 557 u32 value; 558 u16 reg; 559 int err; 560 561 *val = 0; 562 563 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 564 MV88E6XXX_G1_STATS_OP_BUSY | 565 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 566 if (err) 567 return; 568 569 err = mv88e6xxx_g1_stats_wait(chip); 570 if (err) 571 return; 572 573 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 574 if (err) 575 return; 576 577 value = reg << 16; 578 579 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 580 if (err) 581 return; 582 583 *val = value | reg; 584 } 585 586 int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 587 { 588 int err; 589 u16 val; 590 591 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 592 if (err) 593 return err; 594 595 /* Keep the histogram mode bits */ 596 val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 597 val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 598 599 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 600 if (err) 601 return err; 602 603 /* Wait for the flush to complete. */ 604 return mv88e6xxx_g1_stats_wait(chip); 605 } 606