12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11101515c8SVivien Didelot #include <linux/bitfield.h> 12101515c8SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14a935c052SVivien Didelot #include "global1.h" 15a935c052SVivien Didelot 16a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17a935c052SVivien Didelot { 18a935c052SVivien Didelot int addr = chip->info->global1_addr; 19a935c052SVivien Didelot 20a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 21a935c052SVivien Didelot } 22a935c052SVivien Didelot 23a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24a935c052SVivien Didelot { 25a935c052SVivien Didelot int addr = chip->info->global1_addr; 26a935c052SVivien Didelot 27a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 28a935c052SVivien Didelot } 29a935c052SVivien Didelot 3019fb7f69SVivien Didelot int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 3119fb7f69SVivien Didelot bit, int val) 3219fb7f69SVivien Didelot { 3319fb7f69SVivien Didelot return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 3419fb7f69SVivien Didelot bit, val); 3519fb7f69SVivien Didelot } 3619fb7f69SVivien Didelot 37683f2244SVivien Didelot int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 38683f2244SVivien Didelot u16 mask, u16 val) 39683f2244SVivien Didelot { 40683f2244SVivien Didelot return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 41683f2244SVivien Didelot mask, val); 42683f2244SVivien Didelot } 43683f2244SVivien Didelot 4417e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 4517e708baSVivien Didelot 46a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 47a199d8b6SVivien Didelot { 48683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 49683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 50683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_DISABLED); 51a199d8b6SVivien Didelot } 52a199d8b6SVivien Didelot 5317e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 5417e708baSVivien Didelot { 55683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 56683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 57683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_POLLING); 5817e708baSVivien Didelot } 5917e708baSVivien Didelot 6017e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 6117e708baSVivien Didelot { 6219fb7f69SVivien Didelot int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 6317e708baSVivien Didelot 6419fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 6517e708baSVivien Didelot } 6617e708baSVivien Didelot 6717e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 6817e708baSVivien Didelot { 6919fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 7017e708baSVivien Didelot 7117e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 7217e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 7317e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 7417e708baSVivien Didelot */ 7519fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 7617e708baSVivien Didelot } 7717e708baSVivien Didelot 784b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 794b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 804b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 814b0c4817SVivien Didelot */ 824b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 834b0c4817SVivien Didelot { 844b0c4817SVivien Didelot u16 reg; 854b0c4817SVivien Didelot int err; 864b0c4817SVivien Didelot 874b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 884b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 894b0c4817SVivien Didelot if (err) 904b0c4817SVivien Didelot return err; 914b0c4817SVivien Didelot 924b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 934b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 944b0c4817SVivien Didelot if (err) 954b0c4817SVivien Didelot return err; 964b0c4817SVivien Didelot 974b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 984b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 994b0c4817SVivien Didelot if (err) 1004b0c4817SVivien Didelot return err; 1014b0c4817SVivien Didelot 1024b0c4817SVivien Didelot return 0; 1034b0c4817SVivien Didelot } 1044b0c4817SVivien Didelot 10517e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 10617e708baSVivien Didelot 10717e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 10817e708baSVivien Didelot { 10917e708baSVivien Didelot u16 val; 11017e708baSVivien Didelot int err; 11117e708baSVivien Didelot 11217e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 11317e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 11417e708baSVivien Didelot */ 115d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 11617e708baSVivien Didelot if (err) 11717e708baSVivien Didelot return err; 11817e708baSVivien Didelot 119d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 120d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 12117e708baSVivien Didelot 122d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 12317e708baSVivien Didelot if (err) 12417e708baSVivien Didelot return err; 12517e708baSVivien Didelot 12617e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 12717e708baSVivien Didelot if (err) 12817e708baSVivien Didelot return err; 12917e708baSVivien Didelot 13017e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 13117e708baSVivien Didelot } 13217e708baSVivien Didelot 1331f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 1341f71836fSRasmus Villemoes { 1351f71836fSRasmus Villemoes u16 val; 1361f71836fSRasmus Villemoes int err; 1371f71836fSRasmus Villemoes 1381f71836fSRasmus Villemoes /* Set the SWReset bit 15 */ 1391f71836fSRasmus Villemoes err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 1401f71836fSRasmus Villemoes if (err) 1411f71836fSRasmus Villemoes return err; 1421f71836fSRasmus Villemoes 1431f71836fSRasmus Villemoes val |= MV88E6XXX_G1_CTL1_SW_RESET; 1441f71836fSRasmus Villemoes 1451f71836fSRasmus Villemoes err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 1461f71836fSRasmus Villemoes if (err) 1471f71836fSRasmus Villemoes return err; 1481f71836fSRasmus Villemoes 1491f71836fSRasmus Villemoes return mv88e6xxx_g1_wait_init_ready(chip); 1501f71836fSRasmus Villemoes } 1511f71836fSRasmus Villemoes 15217e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 15317e708baSVivien Didelot { 15417e708baSVivien Didelot int err; 15517e708baSVivien Didelot 1567358fd80SRasmus Villemoes err = mv88e6250_g1_reset(chip); 15717e708baSVivien Didelot if (err) 15817e708baSVivien Didelot return err; 15917e708baSVivien Didelot 16017e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 16117e708baSVivien Didelot } 16217e708baSVivien Didelot 163a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 164a199d8b6SVivien Didelot { 165a199d8b6SVivien Didelot u16 val; 166a199d8b6SVivien Didelot int err; 167a199d8b6SVivien Didelot 168d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 169a199d8b6SVivien Didelot if (err) 170a199d8b6SVivien Didelot return err; 171a199d8b6SVivien Didelot 172d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 173a199d8b6SVivien Didelot 174d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 175a199d8b6SVivien Didelot if (err) 176a199d8b6SVivien Didelot return err; 177a199d8b6SVivien Didelot 178a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 179a199d8b6SVivien Didelot } 180a199d8b6SVivien Didelot 181a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 182a199d8b6SVivien Didelot { 183a199d8b6SVivien Didelot u16 val; 184a199d8b6SVivien Didelot int err; 185a199d8b6SVivien Didelot 186d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 187a199d8b6SVivien Didelot if (err) 188a199d8b6SVivien Didelot return err; 189a199d8b6SVivien Didelot 190d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 191a199d8b6SVivien Didelot 192d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 193a199d8b6SVivien Didelot if (err) 194a199d8b6SVivien Didelot return err; 195a199d8b6SVivien Didelot 196a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 197a199d8b6SVivien Didelot } 198a199d8b6SVivien Didelot 19993e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 20093e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 20193e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 20293e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 20393e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 20493e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 20593e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 20693e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 20793e18d61SVivien Didelot */ 20893e18d61SVivien Didelot 20993e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 21093e18d61SVivien Didelot { 21193e18d61SVivien Didelot int err; 21293e18d61SVivien Didelot 21393e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 21493e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 21593e18d61SVivien Didelot if (err) 21693e18d61SVivien Didelot return err; 21793e18d61SVivien Didelot 21893e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 21993e18d61SVivien Didelot if (err) 22093e18d61SVivien Didelot return err; 22193e18d61SVivien Didelot 22293e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 22393e18d61SVivien Didelot if (err) 22493e18d61SVivien Didelot return err; 22593e18d61SVivien Didelot 22693e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 22793e18d61SVivien Didelot if (err) 22893e18d61SVivien Didelot return err; 22993e18d61SVivien Didelot 23093e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 23193e18d61SVivien Didelot if (err) 23293e18d61SVivien Didelot return err; 23393e18d61SVivien Didelot 23493e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 23593e18d61SVivien Didelot if (err) 23693e18d61SVivien Didelot return err; 23793e18d61SVivien Didelot 23893e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 23993e18d61SVivien Didelot if (err) 24093e18d61SVivien Didelot return err; 24193e18d61SVivien Didelot 24293e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 24393e18d61SVivien Didelot if (err) 24493e18d61SVivien Didelot return err; 24593e18d61SVivien Didelot 24693e18d61SVivien Didelot return 0; 24793e18d61SVivien Didelot } 24893e18d61SVivien Didelot 24993e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 25093e18d61SVivien Didelot 25193e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 25293e18d61SVivien Didelot { 25393e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 25493e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 25593e18d61SVivien Didelot } 25693e18d61SVivien Didelot 257df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 258df63b0d9SRasmus Villemoes { 259df63b0d9SRasmus Villemoes /* Reset the IEEE Tag priorities to defaults */ 260df63b0d9SRasmus Villemoes return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 261df63b0d9SRasmus Villemoes } 262df63b0d9SRasmus Villemoes 26333641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 26433641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 26533641994SAndrew Lunn 2665c74c54cSIwan R Timmer int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 2675c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 2685c74c54cSIwan R Timmer int port) 26933641994SAndrew Lunn { 270f0942e00SIwan R Timmer int *dest_port_chip; 27133641994SAndrew Lunn u16 reg; 27233641994SAndrew Lunn int err; 27333641994SAndrew Lunn 274101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 27533641994SAndrew Lunn if (err) 27633641994SAndrew Lunn return err; 27733641994SAndrew Lunn 2785c74c54cSIwan R Timmer switch (direction) { 2795c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_INGRESS: 280f0942e00SIwan R Timmer dest_port_chip = &chip->ingress_dest_port; 2815c74c54cSIwan R Timmer reg &= MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK; 2825c74c54cSIwan R Timmer reg |= port << 2835c74c54cSIwan R Timmer __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK); 2845c74c54cSIwan R Timmer break; 2855c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_EGRESS: 286f0942e00SIwan R Timmer dest_port_chip = &chip->egress_dest_port; 2875c74c54cSIwan R Timmer reg &= MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK; 2885c74c54cSIwan R Timmer reg |= port << 2895c74c54cSIwan R Timmer __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 2905c74c54cSIwan R Timmer break; 2915c74c54cSIwan R Timmer default: 2925c74c54cSIwan R Timmer return -EINVAL; 2935c74c54cSIwan R Timmer } 29433641994SAndrew Lunn 295f0942e00SIwan R Timmer err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 296f0942e00SIwan R Timmer if (!err) 297f0942e00SIwan R Timmer *dest_port_chip = port; 298f0942e00SIwan R Timmer 299f0942e00SIwan R Timmer return err; 30033641994SAndrew Lunn } 30133641994SAndrew Lunn 30233641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 30333641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 30433641994SAndrew Lunn * egress it 30533641994SAndrew Lunn */ 30633641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 30733641994SAndrew Lunn { 30833641994SAndrew Lunn u16 reg; 30933641994SAndrew Lunn int err; 31033641994SAndrew Lunn 311101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 31233641994SAndrew Lunn if (err) 31333641994SAndrew Lunn return err; 31433641994SAndrew Lunn 315101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 316101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 31733641994SAndrew Lunn 318101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 31933641994SAndrew Lunn } 32033641994SAndrew Lunn 32133641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 32233641994SAndrew Lunn u16 pointer, u8 data) 32333641994SAndrew Lunn { 32433641994SAndrew Lunn u16 reg; 32533641994SAndrew Lunn 326101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 32733641994SAndrew Lunn 328101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 32933641994SAndrew Lunn } 33033641994SAndrew Lunn 3315c74c54cSIwan R Timmer int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 3325c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 3335c74c54cSIwan R Timmer int port) 33433641994SAndrew Lunn { 335f0942e00SIwan R Timmer int *dest_port_chip; 336101515c8SVivien Didelot u16 ptr; 33733641994SAndrew Lunn int err; 33833641994SAndrew Lunn 3395c74c54cSIwan R Timmer switch (direction) { 3405c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_INGRESS: 341f0942e00SIwan R Timmer dest_port_chip = &chip->ingress_dest_port; 342101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 3435c74c54cSIwan R Timmer break; 3445c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_EGRESS: 345f0942e00SIwan R Timmer dest_port_chip = &chip->egress_dest_port; 346101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 3475c74c54cSIwan R Timmer break; 3485c74c54cSIwan R Timmer default: 3495c74c54cSIwan R Timmer return -EINVAL; 3505c74c54cSIwan R Timmer } 3515c74c54cSIwan R Timmer 352101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 353f0942e00SIwan R Timmer if (!err) 354f0942e00SIwan R Timmer *dest_port_chip = port; 355101515c8SVivien Didelot 356f0942e00SIwan R Timmer return err; 35733641994SAndrew Lunn } 35833641994SAndrew Lunn 35933641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 36033641994SAndrew Lunn { 361101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 362101515c8SVivien Didelot 363d8dc2c96SAndrew Lunn /* Use the default high priority for management frames sent to 364d8dc2c96SAndrew Lunn * the CPU. 365d8dc2c96SAndrew Lunn */ 366d8dc2c96SAndrew Lunn port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; 367d8dc2c96SAndrew Lunn 368101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 36933641994SAndrew Lunn } 37033641994SAndrew Lunn 3716e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3726e55f698SAndrew Lunn { 373101515c8SVivien Didelot u16 ptr; 3746e55f698SAndrew Lunn int err; 3756e55f698SAndrew Lunn 376989f405aSRasmus Villemoes /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 377989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 378101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3796e55f698SAndrew Lunn if (err) 3806e55f698SAndrew Lunn return err; 3816e55f698SAndrew Lunn 382989f405aSRasmus Villemoes /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 383989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 384101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3856e55f698SAndrew Lunn if (err) 3866e55f698SAndrew Lunn return err; 3876e55f698SAndrew Lunn 388989f405aSRasmus Villemoes /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 389989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 390101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3916e55f698SAndrew Lunn if (err) 3926e55f698SAndrew Lunn return err; 3936e55f698SAndrew Lunn 394989f405aSRasmus Villemoes /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 395989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 396101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 397101515c8SVivien Didelot if (err) 398101515c8SVivien Didelot return err; 399101515c8SVivien Didelot 400101515c8SVivien Didelot return 0; 4016e55f698SAndrew Lunn } 4026e55f698SAndrew Lunn 403de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 404de227387SAndrew Lunn 40502317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 40602317e68SVivien Didelot u16 val) 40702317e68SVivien Didelot { 40802317e68SVivien Didelot u16 reg; 40902317e68SVivien Didelot int err; 41002317e68SVivien Didelot 41102317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 41202317e68SVivien Didelot if (err) 41302317e68SVivien Didelot return err; 41402317e68SVivien Didelot 41502317e68SVivien Didelot reg &= ~mask; 41602317e68SVivien Didelot reg |= val & mask; 41702317e68SVivien Didelot 41802317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 41902317e68SVivien Didelot } 42002317e68SVivien Didelot 42102317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 42202317e68SVivien Didelot { 42302317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 42402317e68SVivien Didelot 42502317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 42602317e68SVivien Didelot } 42702317e68SVivien Didelot 4289e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4299e5baf9bSVivien Didelot { 4309e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4319e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4329e5baf9bSVivien Didelot } 4339e5baf9bSVivien Didelot 4349e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4359e5baf9bSVivien Didelot { 4369e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4379e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4389e5baf9bSVivien Didelot } 4399e5baf9bSVivien Didelot 4409e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4419e5baf9bSVivien Didelot { 4429e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4439e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4449e5baf9bSVivien Didelot } 4459e5baf9bSVivien Didelot 446de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 447de227387SAndrew Lunn { 448408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 449408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 450408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 451de227387SAndrew Lunn } 452de227387SAndrew Lunn 45323c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 45423c98919SVivien Didelot { 45523c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 45623c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 45723c98919SVivien Didelot index); 45823c98919SVivien Didelot } 45923c98919SVivien Didelot 460de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 461de227387SAndrew Lunn 462cfd10888SRasmus Villemoes static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 463a605a0feSAndrew Lunn { 46419fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 46519fb7f69SVivien Didelot 46619fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 467a605a0feSAndrew Lunn } 468a605a0feSAndrew Lunn 46940cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 47040cff8fcSAndrew Lunn { 47140cff8fcSAndrew Lunn u16 val; 47240cff8fcSAndrew Lunn int err; 47340cff8fcSAndrew Lunn 47440cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 47540cff8fcSAndrew Lunn if (err) 47640cff8fcSAndrew Lunn return err; 47740cff8fcSAndrew Lunn 47840cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 47940cff8fcSAndrew Lunn 48040cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 48140cff8fcSAndrew Lunn 48240cff8fcSAndrew Lunn return err; 48340cff8fcSAndrew Lunn } 48440cff8fcSAndrew Lunn 485a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 486a605a0feSAndrew Lunn { 487a605a0feSAndrew Lunn int err; 488a605a0feSAndrew Lunn 489a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 49057d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 49157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 49257d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 49357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 494a605a0feSAndrew Lunn if (err) 495a605a0feSAndrew Lunn return err; 496a605a0feSAndrew Lunn 497a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 498a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 499a605a0feSAndrew Lunn } 500a605a0feSAndrew Lunn 501a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 502a605a0feSAndrew Lunn { 503a605a0feSAndrew Lunn port = (port + 1) << 5; 504a605a0feSAndrew Lunn 505a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 506a605a0feSAndrew Lunn } 50779523473SAndrew Lunn 50879523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 50979523473SAndrew Lunn { 51079523473SAndrew Lunn int err; 51179523473SAndrew Lunn 51279523473SAndrew Lunn port = (port + 1) << 5; 51379523473SAndrew Lunn 51479523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 51557d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 51657d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 51757d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 51879523473SAndrew Lunn if (err) 51979523473SAndrew Lunn return err; 52079523473SAndrew Lunn 52179523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 52279523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 52379523473SAndrew Lunn } 5247f9ef3afSAndrew Lunn 5257f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 5267f9ef3afSAndrew Lunn { 5277f9ef3afSAndrew Lunn u32 value; 5287f9ef3afSAndrew Lunn u16 reg; 5297f9ef3afSAndrew Lunn int err; 5307f9ef3afSAndrew Lunn 5317f9ef3afSAndrew Lunn *val = 0; 5327f9ef3afSAndrew Lunn 53357d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 53457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 53557d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5367f9ef3afSAndrew Lunn if (err) 5377f9ef3afSAndrew Lunn return; 5387f9ef3afSAndrew Lunn 5397f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5407f9ef3afSAndrew Lunn if (err) 5417f9ef3afSAndrew Lunn return; 5427f9ef3afSAndrew Lunn 54357d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5447f9ef3afSAndrew Lunn if (err) 5457f9ef3afSAndrew Lunn return; 5467f9ef3afSAndrew Lunn 5477f9ef3afSAndrew Lunn value = reg << 16; 5487f9ef3afSAndrew Lunn 54957d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5507f9ef3afSAndrew Lunn if (err) 5517f9ef3afSAndrew Lunn return; 5527f9ef3afSAndrew Lunn 5537f9ef3afSAndrew Lunn *val = value | reg; 5547f9ef3afSAndrew Lunn } 55540cff8fcSAndrew Lunn 55640cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 55740cff8fcSAndrew Lunn { 55840cff8fcSAndrew Lunn int err; 55940cff8fcSAndrew Lunn u16 val; 56040cff8fcSAndrew Lunn 56140cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 56240cff8fcSAndrew Lunn if (err) 56340cff8fcSAndrew Lunn return err; 56440cff8fcSAndrew Lunn 565a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 566a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 56740cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 56840cff8fcSAndrew Lunn 56940cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 57040cff8fcSAndrew Lunn if (err) 57140cff8fcSAndrew Lunn return err; 57240cff8fcSAndrew Lunn 57340cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 57440cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 57540cff8fcSAndrew Lunn } 576