1a935c052SVivien Didelot /* 2a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 3a935c052SVivien Didelot * 4a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5a935c052SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8a935c052SVivien Didelot * 9a935c052SVivien Didelot * This program is free software; you can redistribute it and/or modify 10a935c052SVivien Didelot * it under the terms of the GNU General Public License as published by 11a935c052SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 12a935c052SVivien Didelot * (at your option) any later version. 13a935c052SVivien Didelot */ 14a935c052SVivien Didelot 15101515c8SVivien Didelot #include <linux/bitfield.h> 16101515c8SVivien Didelot 174d5f2ba7SVivien Didelot #include "chip.h" 18a935c052SVivien Didelot #include "global1.h" 19a935c052SVivien Didelot 20a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 21a935c052SVivien Didelot { 22a935c052SVivien Didelot int addr = chip->info->global1_addr; 23a935c052SVivien Didelot 24a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 25a935c052SVivien Didelot } 26a935c052SVivien Didelot 27a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 28a935c052SVivien Didelot { 29a935c052SVivien Didelot int addr = chip->info->global1_addr; 30a935c052SVivien Didelot 31a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 32a935c052SVivien Didelot } 33a935c052SVivien Didelot 34a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 35a935c052SVivien Didelot { 36a935c052SVivien Didelot return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 37a935c052SVivien Didelot } 38a605a0feSAndrew Lunn 3917e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 4017e708baSVivien Didelot 41a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 42a199d8b6SVivien Didelot { 43a199d8b6SVivien Didelot u16 state; 44a199d8b6SVivien Didelot int i, err; 45a199d8b6SVivien Didelot 46a199d8b6SVivien Didelot for (i = 0; i < 16; i++) { 4782466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 48a199d8b6SVivien Didelot if (err) 49a199d8b6SVivien Didelot return err; 50a199d8b6SVivien Didelot 51a199d8b6SVivien Didelot /* Check the value of the PPUState bits 15:14 */ 5282466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 5382466921SVivien Didelot if (state != MV88E6185_G1_STS_PPU_STATE_POLLING) 54a199d8b6SVivien Didelot return 0; 55a199d8b6SVivien Didelot 56a199d8b6SVivien Didelot usleep_range(1000, 2000); 57a199d8b6SVivien Didelot } 58a199d8b6SVivien Didelot 59a199d8b6SVivien Didelot return -ETIMEDOUT; 60a199d8b6SVivien Didelot } 61a199d8b6SVivien Didelot 6217e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 6317e708baSVivien Didelot { 6417e708baSVivien Didelot u16 state; 6517e708baSVivien Didelot int i, err; 6617e708baSVivien Didelot 6717e708baSVivien Didelot for (i = 0; i < 16; ++i) { 6882466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 6917e708baSVivien Didelot if (err) 7017e708baSVivien Didelot return err; 7117e708baSVivien Didelot 7217e708baSVivien Didelot /* Check the value of the PPUState bits 15:14 */ 7382466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 7482466921SVivien Didelot if (state == MV88E6185_G1_STS_PPU_STATE_POLLING) 7517e708baSVivien Didelot return 0; 7617e708baSVivien Didelot 7717e708baSVivien Didelot usleep_range(1000, 2000); 7817e708baSVivien Didelot } 7917e708baSVivien Didelot 8017e708baSVivien Didelot return -ETIMEDOUT; 8117e708baSVivien Didelot } 8217e708baSVivien Didelot 8317e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 8417e708baSVivien Didelot { 8517e708baSVivien Didelot u16 state; 8617e708baSVivien Didelot int i, err; 8717e708baSVivien Didelot 8817e708baSVivien Didelot for (i = 0; i < 16; ++i) { 8982466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 9017e708baSVivien Didelot if (err) 9117e708baSVivien Didelot return err; 9217e708baSVivien Didelot 9317e708baSVivien Didelot /* Check the value of the PPUState (or InitState) bit 15 */ 9482466921SVivien Didelot if (state & MV88E6352_G1_STS_PPU_STATE) 9517e708baSVivien Didelot return 0; 9617e708baSVivien Didelot 9717e708baSVivien Didelot usleep_range(1000, 2000); 9817e708baSVivien Didelot } 9917e708baSVivien Didelot 10017e708baSVivien Didelot return -ETIMEDOUT; 10117e708baSVivien Didelot } 10217e708baSVivien Didelot 10317e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 10417e708baSVivien Didelot { 10517e708baSVivien Didelot const unsigned long timeout = jiffies + 1 * HZ; 10617e708baSVivien Didelot u16 val; 10717e708baSVivien Didelot int err; 10817e708baSVivien Didelot 10917e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 11017e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 11117e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 11217e708baSVivien Didelot */ 11317e708baSVivien Didelot while (time_before(jiffies, timeout)) { 11482466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 11517e708baSVivien Didelot if (err) 11617e708baSVivien Didelot return err; 11717e708baSVivien Didelot 11882466921SVivien Didelot if (val & MV88E6XXX_G1_STS_INIT_READY) 11917e708baSVivien Didelot break; 12017e708baSVivien Didelot 12117e708baSVivien Didelot usleep_range(1000, 2000); 12217e708baSVivien Didelot } 12317e708baSVivien Didelot 12417e708baSVivien Didelot if (time_after(jiffies, timeout)) 12517e708baSVivien Didelot return -ETIMEDOUT; 12617e708baSVivien Didelot 12717e708baSVivien Didelot return 0; 12817e708baSVivien Didelot } 12917e708baSVivien Didelot 1304b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 1314b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 1324b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 1334b0c4817SVivien Didelot */ 1344b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 1354b0c4817SVivien Didelot { 1364b0c4817SVivien Didelot u16 reg; 1374b0c4817SVivien Didelot int err; 1384b0c4817SVivien Didelot 1394b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 1404b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 1414b0c4817SVivien Didelot if (err) 1424b0c4817SVivien Didelot return err; 1434b0c4817SVivien Didelot 1444b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 1454b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 1464b0c4817SVivien Didelot if (err) 1474b0c4817SVivien Didelot return err; 1484b0c4817SVivien Didelot 1494b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 1504b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 1514b0c4817SVivien Didelot if (err) 1524b0c4817SVivien Didelot return err; 1534b0c4817SVivien Didelot 1544b0c4817SVivien Didelot return 0; 1554b0c4817SVivien Didelot } 1564b0c4817SVivien Didelot 15717e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 15817e708baSVivien Didelot 15917e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 16017e708baSVivien Didelot { 16117e708baSVivien Didelot u16 val; 16217e708baSVivien Didelot int err; 16317e708baSVivien Didelot 16417e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 16517e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 16617e708baSVivien Didelot */ 167d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 16817e708baSVivien Didelot if (err) 16917e708baSVivien Didelot return err; 17017e708baSVivien Didelot 171d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 172d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 17317e708baSVivien Didelot 174d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 17517e708baSVivien Didelot if (err) 17617e708baSVivien Didelot return err; 17717e708baSVivien Didelot 17817e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 17917e708baSVivien Didelot if (err) 18017e708baSVivien Didelot return err; 18117e708baSVivien Didelot 18217e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 18317e708baSVivien Didelot } 18417e708baSVivien Didelot 18517e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 18617e708baSVivien Didelot { 18717e708baSVivien Didelot u16 val; 18817e708baSVivien Didelot int err; 18917e708baSVivien Didelot 19017e708baSVivien Didelot /* Set the SWReset bit 15 */ 191d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 19217e708baSVivien Didelot if (err) 19317e708baSVivien Didelot return err; 19417e708baSVivien Didelot 195d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 19617e708baSVivien Didelot 197d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 19817e708baSVivien Didelot if (err) 19917e708baSVivien Didelot return err; 20017e708baSVivien Didelot 20117e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 20217e708baSVivien Didelot if (err) 20317e708baSVivien Didelot return err; 20417e708baSVivien Didelot 20517e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 20617e708baSVivien Didelot } 20717e708baSVivien Didelot 208a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 209a199d8b6SVivien Didelot { 210a199d8b6SVivien Didelot u16 val; 211a199d8b6SVivien Didelot int err; 212a199d8b6SVivien Didelot 213d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 214a199d8b6SVivien Didelot if (err) 215a199d8b6SVivien Didelot return err; 216a199d8b6SVivien Didelot 217d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 218a199d8b6SVivien Didelot 219d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 220a199d8b6SVivien Didelot if (err) 221a199d8b6SVivien Didelot return err; 222a199d8b6SVivien Didelot 223a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 224a199d8b6SVivien Didelot } 225a199d8b6SVivien Didelot 226a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 227a199d8b6SVivien Didelot { 228a199d8b6SVivien Didelot u16 val; 229a199d8b6SVivien Didelot int err; 230a199d8b6SVivien Didelot 231d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 232a199d8b6SVivien Didelot if (err) 233a199d8b6SVivien Didelot return err; 234a199d8b6SVivien Didelot 235d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 236a199d8b6SVivien Didelot 237d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 238a199d8b6SVivien Didelot if (err) 239a199d8b6SVivien Didelot return err; 240a199d8b6SVivien Didelot 241a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 242a199d8b6SVivien Didelot } 243a199d8b6SVivien Didelot 24493e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 24593e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 24693e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 24793e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 24893e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 24993e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 25093e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 25193e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 25293e18d61SVivien Didelot */ 25393e18d61SVivien Didelot 25493e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 25593e18d61SVivien Didelot { 25693e18d61SVivien Didelot int err; 25793e18d61SVivien Didelot 25893e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 25993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 26093e18d61SVivien Didelot if (err) 26193e18d61SVivien Didelot return err; 26293e18d61SVivien Didelot 26393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 26493e18d61SVivien Didelot if (err) 26593e18d61SVivien Didelot return err; 26693e18d61SVivien Didelot 26793e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 26893e18d61SVivien Didelot if (err) 26993e18d61SVivien Didelot return err; 27093e18d61SVivien Didelot 27193e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 27293e18d61SVivien Didelot if (err) 27393e18d61SVivien Didelot return err; 27493e18d61SVivien Didelot 27593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 27693e18d61SVivien Didelot if (err) 27793e18d61SVivien Didelot return err; 27893e18d61SVivien Didelot 27993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 28093e18d61SVivien Didelot if (err) 28193e18d61SVivien Didelot return err; 28293e18d61SVivien Didelot 28393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 28493e18d61SVivien Didelot if (err) 28593e18d61SVivien Didelot return err; 28693e18d61SVivien Didelot 28793e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 28893e18d61SVivien Didelot if (err) 28993e18d61SVivien Didelot return err; 29093e18d61SVivien Didelot 29193e18d61SVivien Didelot return 0; 29293e18d61SVivien Didelot } 29393e18d61SVivien Didelot 29493e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 29593e18d61SVivien Didelot 29693e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 29793e18d61SVivien Didelot { 29893e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 29993e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 30093e18d61SVivien Didelot } 30193e18d61SVivien Didelot 30233641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 30333641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 30433641994SAndrew Lunn 30533641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 30633641994SAndrew Lunn { 30733641994SAndrew Lunn u16 reg; 30833641994SAndrew Lunn int err; 30933641994SAndrew Lunn 310101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 31133641994SAndrew Lunn if (err) 31233641994SAndrew Lunn return err; 31333641994SAndrew Lunn 314101515c8SVivien Didelot reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 315101515c8SVivien Didelot MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 31633641994SAndrew Lunn 317101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 318101515c8SVivien Didelot port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 31933641994SAndrew Lunn 320101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 32133641994SAndrew Lunn } 32233641994SAndrew Lunn 32333641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 32433641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 32533641994SAndrew Lunn * egress it 32633641994SAndrew Lunn */ 32733641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 32833641994SAndrew Lunn { 32933641994SAndrew Lunn u16 reg; 33033641994SAndrew Lunn int err; 33133641994SAndrew Lunn 332101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 33333641994SAndrew Lunn if (err) 33433641994SAndrew Lunn return err; 33533641994SAndrew Lunn 336101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 337101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 33833641994SAndrew Lunn 339101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 34033641994SAndrew Lunn } 34133641994SAndrew Lunn 34233641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 34333641994SAndrew Lunn u16 pointer, u8 data) 34433641994SAndrew Lunn { 34533641994SAndrew Lunn u16 reg; 34633641994SAndrew Lunn 347101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 34833641994SAndrew Lunn 349101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 35033641994SAndrew Lunn } 35133641994SAndrew Lunn 35233641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 35333641994SAndrew Lunn { 354101515c8SVivien Didelot u16 ptr; 35533641994SAndrew Lunn int err; 35633641994SAndrew Lunn 357101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 358101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 35933641994SAndrew Lunn if (err) 36033641994SAndrew Lunn return err; 36133641994SAndrew Lunn 362101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 363101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 364101515c8SVivien Didelot if (err) 365101515c8SVivien Didelot return err; 366101515c8SVivien Didelot 367101515c8SVivien Didelot return 0; 36833641994SAndrew Lunn } 36933641994SAndrew Lunn 37033641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 37133641994SAndrew Lunn { 372101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 373101515c8SVivien Didelot 374101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 37533641994SAndrew Lunn } 37633641994SAndrew Lunn 3776e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3786e55f698SAndrew Lunn { 379101515c8SVivien Didelot u16 ptr; 3806e55f698SAndrew Lunn int err; 3816e55f698SAndrew Lunn 3826e55f698SAndrew Lunn /* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */ 383101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO; 384101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3856e55f698SAndrew Lunn if (err) 3866e55f698SAndrew Lunn return err; 3876e55f698SAndrew Lunn 3886e55f698SAndrew Lunn /* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */ 389101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI; 390101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3916e55f698SAndrew Lunn if (err) 3926e55f698SAndrew Lunn return err; 3936e55f698SAndrew Lunn 3946e55f698SAndrew Lunn /* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */ 395101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO; 396101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3976e55f698SAndrew Lunn if (err) 3986e55f698SAndrew Lunn return err; 3996e55f698SAndrew Lunn 4006e55f698SAndrew Lunn /* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */ 401101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI; 402101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 403101515c8SVivien Didelot if (err) 404101515c8SVivien Didelot return err; 405101515c8SVivien Didelot 406101515c8SVivien Didelot return 0; 4076e55f698SAndrew Lunn } 4086e55f698SAndrew Lunn 409de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 410de227387SAndrew Lunn 41102317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 41202317e68SVivien Didelot u16 val) 41302317e68SVivien Didelot { 41402317e68SVivien Didelot u16 reg; 41502317e68SVivien Didelot int err; 41602317e68SVivien Didelot 41702317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 41802317e68SVivien Didelot if (err) 41902317e68SVivien Didelot return err; 42002317e68SVivien Didelot 42102317e68SVivien Didelot reg &= ~mask; 42202317e68SVivien Didelot reg |= val & mask; 42302317e68SVivien Didelot 42402317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 42502317e68SVivien Didelot } 42602317e68SVivien Didelot 42702317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 42802317e68SVivien Didelot { 42902317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 43002317e68SVivien Didelot 43102317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 43202317e68SVivien Didelot } 43302317e68SVivien Didelot 4349e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4359e5baf9bSVivien Didelot { 4369e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4379e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4389e5baf9bSVivien Didelot } 4399e5baf9bSVivien Didelot 4409e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4419e5baf9bSVivien Didelot { 4429e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4439e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4449e5baf9bSVivien Didelot } 4459e5baf9bSVivien Didelot 4469e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4479e5baf9bSVivien Didelot { 4489e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4499e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4509e5baf9bSVivien Didelot } 4519e5baf9bSVivien Didelot 452de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 453de227387SAndrew Lunn { 454408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 455408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 456408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 457de227387SAndrew Lunn } 458de227387SAndrew Lunn 45923c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 46023c98919SVivien Didelot { 46123c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 46223c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 46323c98919SVivien Didelot index); 46423c98919SVivien Didelot } 46523c98919SVivien Didelot 466de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 467de227387SAndrew Lunn 4687f9ef3afSAndrew Lunn int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 469a605a0feSAndrew Lunn { 47057d1ef38SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 47157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY); 472a605a0feSAndrew Lunn } 473a605a0feSAndrew Lunn 47440cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 47540cff8fcSAndrew Lunn { 47640cff8fcSAndrew Lunn u16 val; 47740cff8fcSAndrew Lunn int err; 47840cff8fcSAndrew Lunn 47940cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 48040cff8fcSAndrew Lunn if (err) 48140cff8fcSAndrew Lunn return err; 48240cff8fcSAndrew Lunn 48340cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 48440cff8fcSAndrew Lunn 48540cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 48640cff8fcSAndrew Lunn 48740cff8fcSAndrew Lunn return err; 48840cff8fcSAndrew Lunn } 48940cff8fcSAndrew Lunn 490a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 491a605a0feSAndrew Lunn { 492a605a0feSAndrew Lunn int err; 493a605a0feSAndrew Lunn 494a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 49557d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 49657d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 49757d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 49857d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 499a605a0feSAndrew Lunn if (err) 500a605a0feSAndrew Lunn return err; 501a605a0feSAndrew Lunn 502a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 503a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 504a605a0feSAndrew Lunn } 505a605a0feSAndrew Lunn 506a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 507a605a0feSAndrew Lunn { 508a605a0feSAndrew Lunn port = (port + 1) << 5; 509a605a0feSAndrew Lunn 510a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 511a605a0feSAndrew Lunn } 51279523473SAndrew Lunn 51379523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 51479523473SAndrew Lunn { 51579523473SAndrew Lunn int err; 51679523473SAndrew Lunn 51779523473SAndrew Lunn port = (port + 1) << 5; 51879523473SAndrew Lunn 51979523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 52057d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 52157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 52257d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 52379523473SAndrew Lunn if (err) 52479523473SAndrew Lunn return err; 52579523473SAndrew Lunn 52679523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 52779523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 52879523473SAndrew Lunn } 5297f9ef3afSAndrew Lunn 5307f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 5317f9ef3afSAndrew Lunn { 5327f9ef3afSAndrew Lunn u32 value; 5337f9ef3afSAndrew Lunn u16 reg; 5347f9ef3afSAndrew Lunn int err; 5357f9ef3afSAndrew Lunn 5367f9ef3afSAndrew Lunn *val = 0; 5377f9ef3afSAndrew Lunn 53857d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 53957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 54057d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5417f9ef3afSAndrew Lunn if (err) 5427f9ef3afSAndrew Lunn return; 5437f9ef3afSAndrew Lunn 5447f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5457f9ef3afSAndrew Lunn if (err) 5467f9ef3afSAndrew Lunn return; 5477f9ef3afSAndrew Lunn 54857d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5497f9ef3afSAndrew Lunn if (err) 5507f9ef3afSAndrew Lunn return; 5517f9ef3afSAndrew Lunn 5527f9ef3afSAndrew Lunn value = reg << 16; 5537f9ef3afSAndrew Lunn 55457d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5557f9ef3afSAndrew Lunn if (err) 5567f9ef3afSAndrew Lunn return; 5577f9ef3afSAndrew Lunn 5587f9ef3afSAndrew Lunn *val = value | reg; 5597f9ef3afSAndrew Lunn } 56040cff8fcSAndrew Lunn 56140cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 56240cff8fcSAndrew Lunn { 56340cff8fcSAndrew Lunn int err; 56440cff8fcSAndrew Lunn u16 val; 56540cff8fcSAndrew Lunn 56640cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 56740cff8fcSAndrew Lunn if (err) 56840cff8fcSAndrew Lunn return err; 56940cff8fcSAndrew Lunn 570a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 571a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 57240cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 57340cff8fcSAndrew Lunn 57440cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 57540cff8fcSAndrew Lunn if (err) 57640cff8fcSAndrew Lunn return err; 57740cff8fcSAndrew Lunn 57840cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 57940cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 58040cff8fcSAndrew Lunn } 581