12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11101515c8SVivien Didelot #include <linux/bitfield.h> 12101515c8SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14a935c052SVivien Didelot #include "global1.h" 15a935c052SVivien Didelot 16a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17a935c052SVivien Didelot { 18a935c052SVivien Didelot int addr = chip->info->global1_addr; 19a935c052SVivien Didelot 20a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 21a935c052SVivien Didelot } 22a935c052SVivien Didelot 23a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24a935c052SVivien Didelot { 25a935c052SVivien Didelot int addr = chip->info->global1_addr; 26a935c052SVivien Didelot 27a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 28a935c052SVivien Didelot } 29a935c052SVivien Didelot 3019fb7f69SVivien Didelot int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 3119fb7f69SVivien Didelot bit, int val) 3219fb7f69SVivien Didelot { 3319fb7f69SVivien Didelot return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 3419fb7f69SVivien Didelot bit, val); 3519fb7f69SVivien Didelot } 3619fb7f69SVivien Didelot 37683f2244SVivien Didelot int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 38683f2244SVivien Didelot u16 mask, u16 val) 39683f2244SVivien Didelot { 40683f2244SVivien Didelot return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 41683f2244SVivien Didelot mask, val); 42683f2244SVivien Didelot } 43683f2244SVivien Didelot 4417e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 4517e708baSVivien Didelot 46a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 47a199d8b6SVivien Didelot { 48683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 49683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 50683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_DISABLED); 51a199d8b6SVivien Didelot } 52a199d8b6SVivien Didelot 5317e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 5417e708baSVivien Didelot { 55683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 56683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 57683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_POLLING); 5817e708baSVivien Didelot } 5917e708baSVivien Didelot 6017e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 6117e708baSVivien Didelot { 6219fb7f69SVivien Didelot int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 6317e708baSVivien Didelot 6419fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 6517e708baSVivien Didelot } 6617e708baSVivien Didelot 6717e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 6817e708baSVivien Didelot { 6919fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 7017e708baSVivien Didelot 7117e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 7217e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 7317e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 7417e708baSVivien Didelot */ 7519fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 7617e708baSVivien Didelot } 7717e708baSVivien Didelot 78a3dcb3e7SAndrew Lunn void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip) 79a3dcb3e7SAndrew Lunn { 80a3dcb3e7SAndrew Lunn const unsigned long timeout = jiffies + 1 * HZ; 81a3dcb3e7SAndrew Lunn u16 val; 82a3dcb3e7SAndrew Lunn int err; 83a3dcb3e7SAndrew Lunn 84a3dcb3e7SAndrew Lunn /* Wait up to 1 second for the switch to finish reading the 85a3dcb3e7SAndrew Lunn * EEPROM. 86a3dcb3e7SAndrew Lunn */ 87a3dcb3e7SAndrew Lunn while (time_before(jiffies, timeout)) { 88a3dcb3e7SAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 89a3dcb3e7SAndrew Lunn if (err) { 90a3dcb3e7SAndrew Lunn dev_err(chip->dev, "Error reading status"); 91a3dcb3e7SAndrew Lunn return; 92a3dcb3e7SAndrew Lunn } 93a3dcb3e7SAndrew Lunn 94a3dcb3e7SAndrew Lunn /* If the switch is still resetting, it may not 95a3dcb3e7SAndrew Lunn * respond on the bus, and so MDIO read returns 96a3dcb3e7SAndrew Lunn * 0xffff. Differentiate between that, and waiting for 97a3dcb3e7SAndrew Lunn * the EEPROM to be done by bit 0 being set. 98a3dcb3e7SAndrew Lunn */ 99a3dcb3e7SAndrew Lunn if (val != 0xffff && 100a3dcb3e7SAndrew Lunn val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE)) 101a3dcb3e7SAndrew Lunn return; 102a3dcb3e7SAndrew Lunn 103a3dcb3e7SAndrew Lunn usleep_range(1000, 2000); 104a3dcb3e7SAndrew Lunn } 105a3dcb3e7SAndrew Lunn 106a3dcb3e7SAndrew Lunn dev_err(chip->dev, "Timeout waiting for EEPROM done"); 107a3dcb3e7SAndrew Lunn } 108a3dcb3e7SAndrew Lunn 1094b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 1104b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 1114b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 1124b0c4817SVivien Didelot */ 1134b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 1144b0c4817SVivien Didelot { 1154b0c4817SVivien Didelot u16 reg; 1164b0c4817SVivien Didelot int err; 1174b0c4817SVivien Didelot 1184b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 1194b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 1204b0c4817SVivien Didelot if (err) 1214b0c4817SVivien Didelot return err; 1224b0c4817SVivien Didelot 1234b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 1244b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 1254b0c4817SVivien Didelot if (err) 1264b0c4817SVivien Didelot return err; 1274b0c4817SVivien Didelot 1284b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 1294b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 1304b0c4817SVivien Didelot if (err) 1314b0c4817SVivien Didelot return err; 1324b0c4817SVivien Didelot 1334b0c4817SVivien Didelot return 0; 1344b0c4817SVivien Didelot } 1354b0c4817SVivien Didelot 13617e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 13717e708baSVivien Didelot 13817e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 13917e708baSVivien Didelot { 14017e708baSVivien Didelot u16 val; 14117e708baSVivien Didelot int err; 14217e708baSVivien Didelot 14317e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 14417e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 14517e708baSVivien Didelot */ 146d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 14717e708baSVivien Didelot if (err) 14817e708baSVivien Didelot return err; 14917e708baSVivien Didelot 150d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 151d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 15217e708baSVivien Didelot 153d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 15417e708baSVivien Didelot if (err) 15517e708baSVivien Didelot return err; 15617e708baSVivien Didelot 15717e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 15817e708baSVivien Didelot if (err) 15917e708baSVivien Didelot return err; 16017e708baSVivien Didelot 16117e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 16217e708baSVivien Didelot } 16317e708baSVivien Didelot 1641f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 1651f71836fSRasmus Villemoes { 1661f71836fSRasmus Villemoes u16 val; 1671f71836fSRasmus Villemoes int err; 1681f71836fSRasmus Villemoes 1691f71836fSRasmus Villemoes /* Set the SWReset bit 15 */ 1701f71836fSRasmus Villemoes err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 1711f71836fSRasmus Villemoes if (err) 1721f71836fSRasmus Villemoes return err; 1731f71836fSRasmus Villemoes 1741f71836fSRasmus Villemoes val |= MV88E6XXX_G1_CTL1_SW_RESET; 1751f71836fSRasmus Villemoes 1761f71836fSRasmus Villemoes err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 1771f71836fSRasmus Villemoes if (err) 1781f71836fSRasmus Villemoes return err; 1791f71836fSRasmus Villemoes 1801f71836fSRasmus Villemoes return mv88e6xxx_g1_wait_init_ready(chip); 1811f71836fSRasmus Villemoes } 1821f71836fSRasmus Villemoes 18317e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 18417e708baSVivien Didelot { 18517e708baSVivien Didelot int err; 18617e708baSVivien Didelot 1877358fd80SRasmus Villemoes err = mv88e6250_g1_reset(chip); 18817e708baSVivien Didelot if (err) 18917e708baSVivien Didelot return err; 19017e708baSVivien Didelot 19117e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 19217e708baSVivien Didelot } 19317e708baSVivien Didelot 194a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 195a199d8b6SVivien Didelot { 196a199d8b6SVivien Didelot u16 val; 197a199d8b6SVivien Didelot int err; 198a199d8b6SVivien Didelot 199d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 200a199d8b6SVivien Didelot if (err) 201a199d8b6SVivien Didelot return err; 202a199d8b6SVivien Didelot 203d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 204a199d8b6SVivien Didelot 205d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 206a199d8b6SVivien Didelot if (err) 207a199d8b6SVivien Didelot return err; 208a199d8b6SVivien Didelot 209a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 210a199d8b6SVivien Didelot } 211a199d8b6SVivien Didelot 212a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 213a199d8b6SVivien Didelot { 214a199d8b6SVivien Didelot u16 val; 215a199d8b6SVivien Didelot int err; 216a199d8b6SVivien Didelot 217d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 218a199d8b6SVivien Didelot if (err) 219a199d8b6SVivien Didelot return err; 220a199d8b6SVivien Didelot 221d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 222a199d8b6SVivien Didelot 223d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 224a199d8b6SVivien Didelot if (err) 225a199d8b6SVivien Didelot return err; 226a199d8b6SVivien Didelot 227a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 228a199d8b6SVivien Didelot } 229a199d8b6SVivien Didelot 2301baf0facSChris Packham int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) 2311baf0facSChris Packham { 2321baf0facSChris Packham u16 val; 2331baf0facSChris Packham int err; 2341baf0facSChris Packham 235b92ce2f5SAndrew Lunn mtu += ETH_HLEN + ETH_FCS_LEN; 236b92ce2f5SAndrew Lunn 2371baf0facSChris Packham err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 2381baf0facSChris Packham if (err) 2391baf0facSChris Packham return err; 2401baf0facSChris Packham 2411baf0facSChris Packham val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632; 2421baf0facSChris Packham 2431baf0facSChris Packham if (mtu > 1518) 2441baf0facSChris Packham val |= MV88E6185_G1_CTL1_MAX_FRAME_1632; 2451baf0facSChris Packham 2461baf0facSChris Packham return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 2471baf0facSChris Packham } 2481baf0facSChris Packham 24993e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 25093e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 25193e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 25293e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 25393e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 25493e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 25593e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 25693e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 25793e18d61SVivien Didelot */ 25893e18d61SVivien Didelot 25993e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 26093e18d61SVivien Didelot { 26193e18d61SVivien Didelot int err; 26293e18d61SVivien Didelot 26393e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 26493e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 26593e18d61SVivien Didelot if (err) 26693e18d61SVivien Didelot return err; 26793e18d61SVivien Didelot 26893e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 26993e18d61SVivien Didelot if (err) 27093e18d61SVivien Didelot return err; 27193e18d61SVivien Didelot 27293e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 27393e18d61SVivien Didelot if (err) 27493e18d61SVivien Didelot return err; 27593e18d61SVivien Didelot 27693e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 27793e18d61SVivien Didelot if (err) 27893e18d61SVivien Didelot return err; 27993e18d61SVivien Didelot 28093e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 28193e18d61SVivien Didelot if (err) 28293e18d61SVivien Didelot return err; 28393e18d61SVivien Didelot 28493e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 28593e18d61SVivien Didelot if (err) 28693e18d61SVivien Didelot return err; 28793e18d61SVivien Didelot 28893e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 28993e18d61SVivien Didelot if (err) 29093e18d61SVivien Didelot return err; 29193e18d61SVivien Didelot 29293e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 29393e18d61SVivien Didelot if (err) 29493e18d61SVivien Didelot return err; 29593e18d61SVivien Didelot 29693e18d61SVivien Didelot return 0; 29793e18d61SVivien Didelot } 29893e18d61SVivien Didelot 29993e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 30093e18d61SVivien Didelot 30193e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 30293e18d61SVivien Didelot { 30393e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 30493e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 30593e18d61SVivien Didelot } 30693e18d61SVivien Didelot 307df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 308df63b0d9SRasmus Villemoes { 309df63b0d9SRasmus Villemoes /* Reset the IEEE Tag priorities to defaults */ 310df63b0d9SRasmus Villemoes return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 311df63b0d9SRasmus Villemoes } 312df63b0d9SRasmus Villemoes 31333641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 31433641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 31533641994SAndrew Lunn 3165c74c54cSIwan R Timmer int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 3175c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 3185c74c54cSIwan R Timmer int port) 31933641994SAndrew Lunn { 32033641994SAndrew Lunn u16 reg; 32133641994SAndrew Lunn int err; 32233641994SAndrew Lunn 323101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 32433641994SAndrew Lunn if (err) 32533641994SAndrew Lunn return err; 32633641994SAndrew Lunn 3275c74c54cSIwan R Timmer switch (direction) { 3285c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_INGRESS: 3293ee339ebSAndrew Lunn reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK; 3305c74c54cSIwan R Timmer reg |= port << 3315c74c54cSIwan R Timmer __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK); 3325c74c54cSIwan R Timmer break; 3335c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_EGRESS: 3343ee339ebSAndrew Lunn reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK; 3355c74c54cSIwan R Timmer reg |= port << 3365c74c54cSIwan R Timmer __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 3375c74c54cSIwan R Timmer break; 3385c74c54cSIwan R Timmer default: 3395c74c54cSIwan R Timmer return -EINVAL; 3405c74c54cSIwan R Timmer } 34133641994SAndrew Lunn 3422fda45f0SMarek Behún return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 34333641994SAndrew Lunn } 34433641994SAndrew Lunn 34533641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 34633641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 34733641994SAndrew Lunn * egress it 34833641994SAndrew Lunn */ 34933641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 35033641994SAndrew Lunn { 35133641994SAndrew Lunn u16 reg; 35233641994SAndrew Lunn int err; 35333641994SAndrew Lunn 354101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 35533641994SAndrew Lunn if (err) 35633641994SAndrew Lunn return err; 35733641994SAndrew Lunn 358101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 359101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 36033641994SAndrew Lunn 361101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 36233641994SAndrew Lunn } 36333641994SAndrew Lunn 36433641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 36533641994SAndrew Lunn u16 pointer, u8 data) 36633641994SAndrew Lunn { 36733641994SAndrew Lunn u16 reg; 36833641994SAndrew Lunn 369101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 37033641994SAndrew Lunn 371101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 37233641994SAndrew Lunn } 37333641994SAndrew Lunn 3745c74c54cSIwan R Timmer int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 3755c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 3765c74c54cSIwan R Timmer int port) 37733641994SAndrew Lunn { 378101515c8SVivien Didelot u16 ptr; 37933641994SAndrew Lunn 3805c74c54cSIwan R Timmer switch (direction) { 3815c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_INGRESS: 382101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 3835c74c54cSIwan R Timmer break; 3845c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_EGRESS: 385101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 3865c74c54cSIwan R Timmer break; 3875c74c54cSIwan R Timmer default: 3885c74c54cSIwan R Timmer return -EINVAL; 3895c74c54cSIwan R Timmer } 3905c74c54cSIwan R Timmer 3912fda45f0SMarek Behún return mv88e6390_g1_monitor_write(chip, ptr, port); 39233641994SAndrew Lunn } 39333641994SAndrew Lunn 39433641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 39533641994SAndrew Lunn { 396101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 397101515c8SVivien Didelot 398d8dc2c96SAndrew Lunn /* Use the default high priority for management frames sent to 399d8dc2c96SAndrew Lunn * the CPU. 400d8dc2c96SAndrew Lunn */ 401d8dc2c96SAndrew Lunn port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; 402d8dc2c96SAndrew Lunn 403101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 40433641994SAndrew Lunn } 40533641994SAndrew Lunn 406*9627c981SKurt Kanzenbach int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port) 407*9627c981SKurt Kanzenbach { 408*9627c981SKurt Kanzenbach u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST; 409*9627c981SKurt Kanzenbach 410*9627c981SKurt Kanzenbach /* Use the default high priority for PTP frames sent to 411*9627c981SKurt Kanzenbach * the CPU. 412*9627c981SKurt Kanzenbach */ 413*9627c981SKurt Kanzenbach port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; 414*9627c981SKurt Kanzenbach 415*9627c981SKurt Kanzenbach return mv88e6390_g1_monitor_write(chip, ptr, port); 416*9627c981SKurt Kanzenbach } 417*9627c981SKurt Kanzenbach 4186e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 4196e55f698SAndrew Lunn { 420101515c8SVivien Didelot u16 ptr; 4216e55f698SAndrew Lunn int err; 4226e55f698SAndrew Lunn 423989f405aSRasmus Villemoes /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 424989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 425101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 4266e55f698SAndrew Lunn if (err) 4276e55f698SAndrew Lunn return err; 4286e55f698SAndrew Lunn 429989f405aSRasmus Villemoes /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 430989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 431101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 4326e55f698SAndrew Lunn if (err) 4336e55f698SAndrew Lunn return err; 4346e55f698SAndrew Lunn 435989f405aSRasmus Villemoes /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 436989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 437101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 4386e55f698SAndrew Lunn if (err) 4396e55f698SAndrew Lunn return err; 4406e55f698SAndrew Lunn 441989f405aSRasmus Villemoes /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 442989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 443101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 444101515c8SVivien Didelot if (err) 445101515c8SVivien Didelot return err; 446101515c8SVivien Didelot 447101515c8SVivien Didelot return 0; 4486e55f698SAndrew Lunn } 4496e55f698SAndrew Lunn 450de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 451de227387SAndrew Lunn 45202317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 45302317e68SVivien Didelot u16 val) 45402317e68SVivien Didelot { 45502317e68SVivien Didelot u16 reg; 45602317e68SVivien Didelot int err; 45702317e68SVivien Didelot 45802317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 45902317e68SVivien Didelot if (err) 46002317e68SVivien Didelot return err; 46102317e68SVivien Didelot 46202317e68SVivien Didelot reg &= ~mask; 46302317e68SVivien Didelot reg |= val & mask; 46402317e68SVivien Didelot 46502317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 46602317e68SVivien Didelot } 46702317e68SVivien Didelot 46802317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 46902317e68SVivien Didelot { 47002317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 47102317e68SVivien Didelot 47202317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 47302317e68SVivien Didelot } 47402317e68SVivien Didelot 4759e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4769e5baf9bSVivien Didelot { 4779e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4789e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4799e5baf9bSVivien Didelot } 4809e5baf9bSVivien Didelot 4819e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4829e5baf9bSVivien Didelot { 4839e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4849e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4859e5baf9bSVivien Didelot } 4869e5baf9bSVivien Didelot 4879e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4889e5baf9bSVivien Didelot { 4899e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4909e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4919e5baf9bSVivien Didelot } 4929e5baf9bSVivien Didelot 493de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 494de227387SAndrew Lunn { 495408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 496408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 497408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 498de227387SAndrew Lunn } 499de227387SAndrew Lunn 50023c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 50123c98919SVivien Didelot { 50223c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 50323c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 50423c98919SVivien Didelot index); 50523c98919SVivien Didelot } 50623c98919SVivien Didelot 507de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 508de227387SAndrew Lunn 509cfd10888SRasmus Villemoes static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 510a605a0feSAndrew Lunn { 51119fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 51219fb7f69SVivien Didelot 51319fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 514a605a0feSAndrew Lunn } 515a605a0feSAndrew Lunn 51640cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 51740cff8fcSAndrew Lunn { 51840cff8fcSAndrew Lunn u16 val; 51940cff8fcSAndrew Lunn int err; 52040cff8fcSAndrew Lunn 52140cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 52240cff8fcSAndrew Lunn if (err) 52340cff8fcSAndrew Lunn return err; 52440cff8fcSAndrew Lunn 52540cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 52640cff8fcSAndrew Lunn 52740cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 52840cff8fcSAndrew Lunn 52940cff8fcSAndrew Lunn return err; 53040cff8fcSAndrew Lunn } 53140cff8fcSAndrew Lunn 532a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 533a605a0feSAndrew Lunn { 534a605a0feSAndrew Lunn int err; 535a605a0feSAndrew Lunn 536a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 53757d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 53857d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 53957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 54057d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 541a605a0feSAndrew Lunn if (err) 542a605a0feSAndrew Lunn return err; 543a605a0feSAndrew Lunn 544a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 545a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 546a605a0feSAndrew Lunn } 547a605a0feSAndrew Lunn 548a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 549a605a0feSAndrew Lunn { 550a605a0feSAndrew Lunn port = (port + 1) << 5; 551a605a0feSAndrew Lunn 552a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 553a605a0feSAndrew Lunn } 55479523473SAndrew Lunn 55579523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 55679523473SAndrew Lunn { 55779523473SAndrew Lunn int err; 55879523473SAndrew Lunn 55979523473SAndrew Lunn port = (port + 1) << 5; 56079523473SAndrew Lunn 56179523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 56257d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 56357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 56457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 56579523473SAndrew Lunn if (err) 56679523473SAndrew Lunn return err; 56779523473SAndrew Lunn 56879523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 56979523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 57079523473SAndrew Lunn } 5717f9ef3afSAndrew Lunn 5727f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 5737f9ef3afSAndrew Lunn { 5747f9ef3afSAndrew Lunn u32 value; 5757f9ef3afSAndrew Lunn u16 reg; 5767f9ef3afSAndrew Lunn int err; 5777f9ef3afSAndrew Lunn 5787f9ef3afSAndrew Lunn *val = 0; 5797f9ef3afSAndrew Lunn 58057d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 58157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 58257d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5837f9ef3afSAndrew Lunn if (err) 5847f9ef3afSAndrew Lunn return; 5857f9ef3afSAndrew Lunn 5867f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5877f9ef3afSAndrew Lunn if (err) 5887f9ef3afSAndrew Lunn return; 5897f9ef3afSAndrew Lunn 59057d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5917f9ef3afSAndrew Lunn if (err) 5927f9ef3afSAndrew Lunn return; 5937f9ef3afSAndrew Lunn 5947f9ef3afSAndrew Lunn value = reg << 16; 5957f9ef3afSAndrew Lunn 59657d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5977f9ef3afSAndrew Lunn if (err) 5987f9ef3afSAndrew Lunn return; 5997f9ef3afSAndrew Lunn 6007f9ef3afSAndrew Lunn *val = value | reg; 6017f9ef3afSAndrew Lunn } 60240cff8fcSAndrew Lunn 60340cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 60440cff8fcSAndrew Lunn { 60540cff8fcSAndrew Lunn int err; 60640cff8fcSAndrew Lunn u16 val; 60740cff8fcSAndrew Lunn 60840cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 60940cff8fcSAndrew Lunn if (err) 61040cff8fcSAndrew Lunn return err; 61140cff8fcSAndrew Lunn 612a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 613a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 61440cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 61540cff8fcSAndrew Lunn 61640cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 61740cff8fcSAndrew Lunn if (err) 61840cff8fcSAndrew Lunn return err; 61940cff8fcSAndrew Lunn 62040cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 62140cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 62240cff8fcSAndrew Lunn } 623