1a935c052SVivien Didelot /* 2a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 3a935c052SVivien Didelot * 4a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5a935c052SVivien Didelot * 6a935c052SVivien Didelot * Copyright (c) 2016 Vivien Didelot <vivien.didelot@savoirfairelinux.com> 7a935c052SVivien Didelot * 8a935c052SVivien Didelot * This program is free software; you can redistribute it and/or modify 9a935c052SVivien Didelot * it under the terms of the GNU General Public License as published by 10a935c052SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 11a935c052SVivien Didelot * (at your option) any later version. 12a935c052SVivien Didelot */ 13a935c052SVivien Didelot 14a935c052SVivien Didelot #include "mv88e6xxx.h" 15a935c052SVivien Didelot #include "global1.h" 16a935c052SVivien Didelot 17a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 18a935c052SVivien Didelot { 19a935c052SVivien Didelot int addr = chip->info->global1_addr; 20a935c052SVivien Didelot 21a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 22a935c052SVivien Didelot } 23a935c052SVivien Didelot 24a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 25a935c052SVivien Didelot { 26a935c052SVivien Didelot int addr = chip->info->global1_addr; 27a935c052SVivien Didelot 28a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 29a935c052SVivien Didelot } 30a935c052SVivien Didelot 31a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 32a935c052SVivien Didelot { 33a935c052SVivien Didelot return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 34a935c052SVivien Didelot } 35a605a0feSAndrew Lunn 36a605a0feSAndrew Lunn static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 37a605a0feSAndrew Lunn { 38a605a0feSAndrew Lunn return mv88e6xxx_g1_wait(chip, GLOBAL_STATS_OP, GLOBAL_STATS_OP_BUSY); 39a605a0feSAndrew Lunn } 40a605a0feSAndrew Lunn 41a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 42a605a0feSAndrew Lunn { 43a605a0feSAndrew Lunn int err; 44a605a0feSAndrew Lunn 45a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 46a605a0feSAndrew Lunn err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 47a605a0feSAndrew Lunn GLOBAL_STATS_OP_CAPTURE_PORT | 48a605a0feSAndrew Lunn GLOBAL_STATS_OP_HIST_RX_TX | port); 49a605a0feSAndrew Lunn if (err) 50a605a0feSAndrew Lunn return err; 51a605a0feSAndrew Lunn 52a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 53a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 54a605a0feSAndrew Lunn } 55a605a0feSAndrew Lunn 56a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 57a605a0feSAndrew Lunn { 58a605a0feSAndrew Lunn port = (port + 1) << 5; 59a605a0feSAndrew Lunn 60a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 61a605a0feSAndrew Lunn } 6279523473SAndrew Lunn 6379523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 6479523473SAndrew Lunn { 6579523473SAndrew Lunn int err; 6679523473SAndrew Lunn 6779523473SAndrew Lunn port = (port + 1) << 5; 6879523473SAndrew Lunn 6979523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 7079523473SAndrew Lunn err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 7179523473SAndrew Lunn GLOBAL_STATS_OP_CAPTURE_PORT | port); 7279523473SAndrew Lunn if (err) 7379523473SAndrew Lunn return err; 7479523473SAndrew Lunn 7579523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 7679523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 7779523473SAndrew Lunn } 78