1a935c052SVivien Didelot /* 2a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 3a935c052SVivien Didelot * 4a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5a935c052SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8a935c052SVivien Didelot * 9a935c052SVivien Didelot * This program is free software; you can redistribute it and/or modify 10a935c052SVivien Didelot * it under the terms of the GNU General Public License as published by 11a935c052SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 12a935c052SVivien Didelot * (at your option) any later version. 13a935c052SVivien Didelot */ 14a935c052SVivien Didelot 15101515c8SVivien Didelot #include <linux/bitfield.h> 16101515c8SVivien Didelot 174d5f2ba7SVivien Didelot #include "chip.h" 18a935c052SVivien Didelot #include "global1.h" 19a935c052SVivien Didelot 20a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 21a935c052SVivien Didelot { 22a935c052SVivien Didelot int addr = chip->info->global1_addr; 23a935c052SVivien Didelot 24a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 25a935c052SVivien Didelot } 26a935c052SVivien Didelot 27a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 28a935c052SVivien Didelot { 29a935c052SVivien Didelot int addr = chip->info->global1_addr; 30a935c052SVivien Didelot 31a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 32a935c052SVivien Didelot } 33a935c052SVivien Didelot 34a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 35a935c052SVivien Didelot { 36a935c052SVivien Didelot return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 37a935c052SVivien Didelot } 38a605a0feSAndrew Lunn 3917e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 4017e708baSVivien Didelot 41a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 42a199d8b6SVivien Didelot { 43a199d8b6SVivien Didelot u16 state; 44a199d8b6SVivien Didelot int i, err; 45a199d8b6SVivien Didelot 46a199d8b6SVivien Didelot for (i = 0; i < 16; i++) { 4782466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 48a199d8b6SVivien Didelot if (err) 49a199d8b6SVivien Didelot return err; 50a199d8b6SVivien Didelot 51a199d8b6SVivien Didelot /* Check the value of the PPUState bits 15:14 */ 5282466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 5382466921SVivien Didelot if (state != MV88E6185_G1_STS_PPU_STATE_POLLING) 54a199d8b6SVivien Didelot return 0; 55a199d8b6SVivien Didelot 56a199d8b6SVivien Didelot usleep_range(1000, 2000); 57a199d8b6SVivien Didelot } 58a199d8b6SVivien Didelot 59a199d8b6SVivien Didelot return -ETIMEDOUT; 60a199d8b6SVivien Didelot } 61a199d8b6SVivien Didelot 6217e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 6317e708baSVivien Didelot { 6417e708baSVivien Didelot u16 state; 6517e708baSVivien Didelot int i, err; 6617e708baSVivien Didelot 6717e708baSVivien Didelot for (i = 0; i < 16; ++i) { 6882466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 6917e708baSVivien Didelot if (err) 7017e708baSVivien Didelot return err; 7117e708baSVivien Didelot 7217e708baSVivien Didelot /* Check the value of the PPUState bits 15:14 */ 7382466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 7482466921SVivien Didelot if (state == MV88E6185_G1_STS_PPU_STATE_POLLING) 7517e708baSVivien Didelot return 0; 7617e708baSVivien Didelot 7717e708baSVivien Didelot usleep_range(1000, 2000); 7817e708baSVivien Didelot } 7917e708baSVivien Didelot 8017e708baSVivien Didelot return -ETIMEDOUT; 8117e708baSVivien Didelot } 8217e708baSVivien Didelot 8317e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 8417e708baSVivien Didelot { 8517e708baSVivien Didelot u16 state; 8617e708baSVivien Didelot int i, err; 8717e708baSVivien Didelot 8817e708baSVivien Didelot for (i = 0; i < 16; ++i) { 8982466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 9017e708baSVivien Didelot if (err) 9117e708baSVivien Didelot return err; 9217e708baSVivien Didelot 9317e708baSVivien Didelot /* Check the value of the PPUState (or InitState) bit 15 */ 9482466921SVivien Didelot if (state & MV88E6352_G1_STS_PPU_STATE) 9517e708baSVivien Didelot return 0; 9617e708baSVivien Didelot 9717e708baSVivien Didelot usleep_range(1000, 2000); 9817e708baSVivien Didelot } 9917e708baSVivien Didelot 10017e708baSVivien Didelot return -ETIMEDOUT; 10117e708baSVivien Didelot } 10217e708baSVivien Didelot 10317e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 10417e708baSVivien Didelot { 10517e708baSVivien Didelot const unsigned long timeout = jiffies + 1 * HZ; 10617e708baSVivien Didelot u16 val; 10717e708baSVivien Didelot int err; 10817e708baSVivien Didelot 10917e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 11017e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 11117e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 11217e708baSVivien Didelot */ 11317e708baSVivien Didelot while (time_before(jiffies, timeout)) { 11482466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 11517e708baSVivien Didelot if (err) 11617e708baSVivien Didelot return err; 11717e708baSVivien Didelot 11882466921SVivien Didelot if (val & MV88E6XXX_G1_STS_INIT_READY) 11917e708baSVivien Didelot break; 12017e708baSVivien Didelot 12117e708baSVivien Didelot usleep_range(1000, 2000); 12217e708baSVivien Didelot } 12317e708baSVivien Didelot 12417e708baSVivien Didelot if (time_after(jiffies, timeout)) 12517e708baSVivien Didelot return -ETIMEDOUT; 12617e708baSVivien Didelot 12717e708baSVivien Didelot return 0; 12817e708baSVivien Didelot } 12917e708baSVivien Didelot 1304b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 1314b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 1324b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 1334b0c4817SVivien Didelot */ 1344b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 1354b0c4817SVivien Didelot { 1364b0c4817SVivien Didelot u16 reg; 1374b0c4817SVivien Didelot int err; 1384b0c4817SVivien Didelot 1394b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 1404b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 1414b0c4817SVivien Didelot if (err) 1424b0c4817SVivien Didelot return err; 1434b0c4817SVivien Didelot 1444b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 1454b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 1464b0c4817SVivien Didelot if (err) 1474b0c4817SVivien Didelot return err; 1484b0c4817SVivien Didelot 1494b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 1504b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 1514b0c4817SVivien Didelot if (err) 1524b0c4817SVivien Didelot return err; 1534b0c4817SVivien Didelot 1544b0c4817SVivien Didelot return 0; 1554b0c4817SVivien Didelot } 1564b0c4817SVivien Didelot 15717e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 15817e708baSVivien Didelot 15917e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 16017e708baSVivien Didelot { 16117e708baSVivien Didelot u16 val; 16217e708baSVivien Didelot int err; 16317e708baSVivien Didelot 16417e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 16517e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 16617e708baSVivien Didelot */ 167d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 16817e708baSVivien Didelot if (err) 16917e708baSVivien Didelot return err; 17017e708baSVivien Didelot 171d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 172d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 17317e708baSVivien Didelot 174d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 17517e708baSVivien Didelot if (err) 17617e708baSVivien Didelot return err; 17717e708baSVivien Didelot 17817e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 17917e708baSVivien Didelot if (err) 18017e708baSVivien Didelot return err; 18117e708baSVivien Didelot 18217e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 18317e708baSVivien Didelot } 18417e708baSVivien Didelot 1851f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 1861f71836fSRasmus Villemoes { 1871f71836fSRasmus Villemoes u16 val; 1881f71836fSRasmus Villemoes int err; 1891f71836fSRasmus Villemoes 1901f71836fSRasmus Villemoes /* Set the SWReset bit 15 */ 1911f71836fSRasmus Villemoes err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 1921f71836fSRasmus Villemoes if (err) 1931f71836fSRasmus Villemoes return err; 1941f71836fSRasmus Villemoes 1951f71836fSRasmus Villemoes val |= MV88E6XXX_G1_CTL1_SW_RESET; 1961f71836fSRasmus Villemoes 1971f71836fSRasmus Villemoes err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 1981f71836fSRasmus Villemoes if (err) 1991f71836fSRasmus Villemoes return err; 2001f71836fSRasmus Villemoes 2011f71836fSRasmus Villemoes return mv88e6xxx_g1_wait_init_ready(chip); 2021f71836fSRasmus Villemoes } 2031f71836fSRasmus Villemoes 20417e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 20517e708baSVivien Didelot { 20617e708baSVivien Didelot int err; 20717e708baSVivien Didelot 2087358fd80SRasmus Villemoes err = mv88e6250_g1_reset(chip); 20917e708baSVivien Didelot if (err) 21017e708baSVivien Didelot return err; 21117e708baSVivien Didelot 21217e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 21317e708baSVivien Didelot } 21417e708baSVivien Didelot 215a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 216a199d8b6SVivien Didelot { 217a199d8b6SVivien Didelot u16 val; 218a199d8b6SVivien Didelot int err; 219a199d8b6SVivien Didelot 220d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 221a199d8b6SVivien Didelot if (err) 222a199d8b6SVivien Didelot return err; 223a199d8b6SVivien Didelot 224d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 225a199d8b6SVivien Didelot 226d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 227a199d8b6SVivien Didelot if (err) 228a199d8b6SVivien Didelot return err; 229a199d8b6SVivien Didelot 230a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 231a199d8b6SVivien Didelot } 232a199d8b6SVivien Didelot 233a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 234a199d8b6SVivien Didelot { 235a199d8b6SVivien Didelot u16 val; 236a199d8b6SVivien Didelot int err; 237a199d8b6SVivien Didelot 238d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 239a199d8b6SVivien Didelot if (err) 240a199d8b6SVivien Didelot return err; 241a199d8b6SVivien Didelot 242d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 243a199d8b6SVivien Didelot 244d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 245a199d8b6SVivien Didelot if (err) 246a199d8b6SVivien Didelot return err; 247a199d8b6SVivien Didelot 248a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 249a199d8b6SVivien Didelot } 250a199d8b6SVivien Didelot 25193e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 25293e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 25393e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 25493e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 25593e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 25693e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 25793e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 25893e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 25993e18d61SVivien Didelot */ 26093e18d61SVivien Didelot 26193e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 26293e18d61SVivien Didelot { 26393e18d61SVivien Didelot int err; 26493e18d61SVivien Didelot 26593e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 26693e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 26793e18d61SVivien Didelot if (err) 26893e18d61SVivien Didelot return err; 26993e18d61SVivien Didelot 27093e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 27193e18d61SVivien Didelot if (err) 27293e18d61SVivien Didelot return err; 27393e18d61SVivien Didelot 27493e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 27593e18d61SVivien Didelot if (err) 27693e18d61SVivien Didelot return err; 27793e18d61SVivien Didelot 27893e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 27993e18d61SVivien Didelot if (err) 28093e18d61SVivien Didelot return err; 28193e18d61SVivien Didelot 28293e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 28393e18d61SVivien Didelot if (err) 28493e18d61SVivien Didelot return err; 28593e18d61SVivien Didelot 28693e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 28793e18d61SVivien Didelot if (err) 28893e18d61SVivien Didelot return err; 28993e18d61SVivien Didelot 29093e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 29193e18d61SVivien Didelot if (err) 29293e18d61SVivien Didelot return err; 29393e18d61SVivien Didelot 29493e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 29593e18d61SVivien Didelot if (err) 29693e18d61SVivien Didelot return err; 29793e18d61SVivien Didelot 29893e18d61SVivien Didelot return 0; 29993e18d61SVivien Didelot } 30093e18d61SVivien Didelot 30193e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 30293e18d61SVivien Didelot 30393e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 30493e18d61SVivien Didelot { 30593e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 30693e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 30793e18d61SVivien Didelot } 30893e18d61SVivien Didelot 309df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 310df63b0d9SRasmus Villemoes { 311df63b0d9SRasmus Villemoes /* Reset the IEEE Tag priorities to defaults */ 312df63b0d9SRasmus Villemoes return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 313df63b0d9SRasmus Villemoes } 314df63b0d9SRasmus Villemoes 31533641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 31633641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 31733641994SAndrew Lunn 31833641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 31933641994SAndrew Lunn { 32033641994SAndrew Lunn u16 reg; 32133641994SAndrew Lunn int err; 32233641994SAndrew Lunn 323101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 32433641994SAndrew Lunn if (err) 32533641994SAndrew Lunn return err; 32633641994SAndrew Lunn 327101515c8SVivien Didelot reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 328101515c8SVivien Didelot MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 32933641994SAndrew Lunn 330101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 331101515c8SVivien Didelot port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 33233641994SAndrew Lunn 333101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 33433641994SAndrew Lunn } 33533641994SAndrew Lunn 33633641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 33733641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 33833641994SAndrew Lunn * egress it 33933641994SAndrew Lunn */ 34033641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 34133641994SAndrew Lunn { 34233641994SAndrew Lunn u16 reg; 34333641994SAndrew Lunn int err; 34433641994SAndrew Lunn 345101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 34633641994SAndrew Lunn if (err) 34733641994SAndrew Lunn return err; 34833641994SAndrew Lunn 349101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 350101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 35133641994SAndrew Lunn 352101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 35333641994SAndrew Lunn } 35433641994SAndrew Lunn 35533641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 35633641994SAndrew Lunn u16 pointer, u8 data) 35733641994SAndrew Lunn { 35833641994SAndrew Lunn u16 reg; 35933641994SAndrew Lunn 360101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 36133641994SAndrew Lunn 362101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 36333641994SAndrew Lunn } 36433641994SAndrew Lunn 36533641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 36633641994SAndrew Lunn { 367101515c8SVivien Didelot u16 ptr; 36833641994SAndrew Lunn int err; 36933641994SAndrew Lunn 370101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 371101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 37233641994SAndrew Lunn if (err) 37333641994SAndrew Lunn return err; 37433641994SAndrew Lunn 375101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 376101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 377101515c8SVivien Didelot if (err) 378101515c8SVivien Didelot return err; 379101515c8SVivien Didelot 380101515c8SVivien Didelot return 0; 38133641994SAndrew Lunn } 38233641994SAndrew Lunn 38333641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 38433641994SAndrew Lunn { 385101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 386101515c8SVivien Didelot 387101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 38833641994SAndrew Lunn } 38933641994SAndrew Lunn 3906e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3916e55f698SAndrew Lunn { 392101515c8SVivien Didelot u16 ptr; 3936e55f698SAndrew Lunn int err; 3946e55f698SAndrew Lunn 395989f405aSRasmus Villemoes /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 396989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 397101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3986e55f698SAndrew Lunn if (err) 3996e55f698SAndrew Lunn return err; 4006e55f698SAndrew Lunn 401989f405aSRasmus Villemoes /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 402989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 403101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 4046e55f698SAndrew Lunn if (err) 4056e55f698SAndrew Lunn return err; 4066e55f698SAndrew Lunn 407989f405aSRasmus Villemoes /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 408989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 409101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 4106e55f698SAndrew Lunn if (err) 4116e55f698SAndrew Lunn return err; 4126e55f698SAndrew Lunn 413989f405aSRasmus Villemoes /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 414989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 415101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 416101515c8SVivien Didelot if (err) 417101515c8SVivien Didelot return err; 418101515c8SVivien Didelot 419101515c8SVivien Didelot return 0; 4206e55f698SAndrew Lunn } 4216e55f698SAndrew Lunn 422de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 423de227387SAndrew Lunn 42402317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 42502317e68SVivien Didelot u16 val) 42602317e68SVivien Didelot { 42702317e68SVivien Didelot u16 reg; 42802317e68SVivien Didelot int err; 42902317e68SVivien Didelot 43002317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 43102317e68SVivien Didelot if (err) 43202317e68SVivien Didelot return err; 43302317e68SVivien Didelot 43402317e68SVivien Didelot reg &= ~mask; 43502317e68SVivien Didelot reg |= val & mask; 43602317e68SVivien Didelot 43702317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 43802317e68SVivien Didelot } 43902317e68SVivien Didelot 44002317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 44102317e68SVivien Didelot { 44202317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 44302317e68SVivien Didelot 44402317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 44502317e68SVivien Didelot } 44602317e68SVivien Didelot 4479e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4489e5baf9bSVivien Didelot { 4499e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4509e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4519e5baf9bSVivien Didelot } 4529e5baf9bSVivien Didelot 4539e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4549e5baf9bSVivien Didelot { 4559e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4569e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4579e5baf9bSVivien Didelot } 4589e5baf9bSVivien Didelot 4599e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4609e5baf9bSVivien Didelot { 4619e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4629e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4639e5baf9bSVivien Didelot } 4649e5baf9bSVivien Didelot 465de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 466de227387SAndrew Lunn { 467408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 468408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 469408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 470de227387SAndrew Lunn } 471de227387SAndrew Lunn 47223c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 47323c98919SVivien Didelot { 47423c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 47523c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 47623c98919SVivien Didelot index); 47723c98919SVivien Didelot } 47823c98919SVivien Didelot 479de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 480de227387SAndrew Lunn 481cfd10888SRasmus Villemoes static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 482a605a0feSAndrew Lunn { 48357d1ef38SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 48457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY); 485a605a0feSAndrew Lunn } 486a605a0feSAndrew Lunn 48740cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 48840cff8fcSAndrew Lunn { 48940cff8fcSAndrew Lunn u16 val; 49040cff8fcSAndrew Lunn int err; 49140cff8fcSAndrew Lunn 49240cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 49340cff8fcSAndrew Lunn if (err) 49440cff8fcSAndrew Lunn return err; 49540cff8fcSAndrew Lunn 49640cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 49740cff8fcSAndrew Lunn 49840cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 49940cff8fcSAndrew Lunn 50040cff8fcSAndrew Lunn return err; 50140cff8fcSAndrew Lunn } 50240cff8fcSAndrew Lunn 503a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 504a605a0feSAndrew Lunn { 505a605a0feSAndrew Lunn int err; 506a605a0feSAndrew Lunn 507a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 50857d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 50957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 51057d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 51157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 512a605a0feSAndrew Lunn if (err) 513a605a0feSAndrew Lunn return err; 514a605a0feSAndrew Lunn 515a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 516a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 517a605a0feSAndrew Lunn } 518a605a0feSAndrew Lunn 519a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520a605a0feSAndrew Lunn { 521a605a0feSAndrew Lunn port = (port + 1) << 5; 522a605a0feSAndrew Lunn 523a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 524a605a0feSAndrew Lunn } 52579523473SAndrew Lunn 52679523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 52779523473SAndrew Lunn { 52879523473SAndrew Lunn int err; 52979523473SAndrew Lunn 53079523473SAndrew Lunn port = (port + 1) << 5; 53179523473SAndrew Lunn 53279523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 53357d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 53457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 53557d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 53679523473SAndrew Lunn if (err) 53779523473SAndrew Lunn return err; 53879523473SAndrew Lunn 53979523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 54079523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 54179523473SAndrew Lunn } 5427f9ef3afSAndrew Lunn 5437f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 5447f9ef3afSAndrew Lunn { 5457f9ef3afSAndrew Lunn u32 value; 5467f9ef3afSAndrew Lunn u16 reg; 5477f9ef3afSAndrew Lunn int err; 5487f9ef3afSAndrew Lunn 5497f9ef3afSAndrew Lunn *val = 0; 5507f9ef3afSAndrew Lunn 55157d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 55257d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 55357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5547f9ef3afSAndrew Lunn if (err) 5557f9ef3afSAndrew Lunn return; 5567f9ef3afSAndrew Lunn 5577f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5587f9ef3afSAndrew Lunn if (err) 5597f9ef3afSAndrew Lunn return; 5607f9ef3afSAndrew Lunn 56157d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5627f9ef3afSAndrew Lunn if (err) 5637f9ef3afSAndrew Lunn return; 5647f9ef3afSAndrew Lunn 5657f9ef3afSAndrew Lunn value = reg << 16; 5667f9ef3afSAndrew Lunn 56757d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5687f9ef3afSAndrew Lunn if (err) 5697f9ef3afSAndrew Lunn return; 5707f9ef3afSAndrew Lunn 5717f9ef3afSAndrew Lunn *val = value | reg; 5727f9ef3afSAndrew Lunn } 57340cff8fcSAndrew Lunn 57440cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 57540cff8fcSAndrew Lunn { 57640cff8fcSAndrew Lunn int err; 57740cff8fcSAndrew Lunn u16 val; 57840cff8fcSAndrew Lunn 57940cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 58040cff8fcSAndrew Lunn if (err) 58140cff8fcSAndrew Lunn return err; 58240cff8fcSAndrew Lunn 583a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 584a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 58540cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 58640cff8fcSAndrew Lunn 58740cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 58840cff8fcSAndrew Lunn if (err) 58940cff8fcSAndrew Lunn return err; 59040cff8fcSAndrew Lunn 59140cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 59240cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 59340cff8fcSAndrew Lunn } 594