12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11101515c8SVivien Didelot #include <linux/bitfield.h> 12101515c8SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14a935c052SVivien Didelot #include "global1.h" 15a935c052SVivien Didelot 16a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17a935c052SVivien Didelot { 18a935c052SVivien Didelot int addr = chip->info->global1_addr; 19a935c052SVivien Didelot 20a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 21a935c052SVivien Didelot } 22a935c052SVivien Didelot 23a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24a935c052SVivien Didelot { 25a935c052SVivien Didelot int addr = chip->info->global1_addr; 26a935c052SVivien Didelot 27a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 28a935c052SVivien Didelot } 29a935c052SVivien Didelot 30a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 31a935c052SVivien Didelot { 32a935c052SVivien Didelot return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 33a935c052SVivien Didelot } 34a605a0feSAndrew Lunn 35683f2244SVivien Didelot int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 36683f2244SVivien Didelot u16 mask, u16 val) 37683f2244SVivien Didelot { 38683f2244SVivien Didelot return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 39683f2244SVivien Didelot mask, val); 40683f2244SVivien Didelot } 41683f2244SVivien Didelot 4217e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 4317e708baSVivien Didelot 44a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 45a199d8b6SVivien Didelot { 46683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 47683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 48683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_DISABLED); 49a199d8b6SVivien Didelot } 50a199d8b6SVivien Didelot 5117e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 5217e708baSVivien Didelot { 53683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 54683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 55683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_POLLING); 5617e708baSVivien Didelot } 5717e708baSVivien Didelot 5817e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 5917e708baSVivien Didelot { 6017e708baSVivien Didelot u16 state; 6117e708baSVivien Didelot int i, err; 6217e708baSVivien Didelot 6317e708baSVivien Didelot for (i = 0; i < 16; ++i) { 6482466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 6517e708baSVivien Didelot if (err) 6617e708baSVivien Didelot return err; 6717e708baSVivien Didelot 6817e708baSVivien Didelot /* Check the value of the PPUState (or InitState) bit 15 */ 6982466921SVivien Didelot if (state & MV88E6352_G1_STS_PPU_STATE) 7017e708baSVivien Didelot return 0; 7117e708baSVivien Didelot 7217e708baSVivien Didelot usleep_range(1000, 2000); 7317e708baSVivien Didelot } 7417e708baSVivien Didelot 7517e708baSVivien Didelot return -ETIMEDOUT; 7617e708baSVivien Didelot } 7717e708baSVivien Didelot 7817e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 7917e708baSVivien Didelot { 8017e708baSVivien Didelot const unsigned long timeout = jiffies + 1 * HZ; 8117e708baSVivien Didelot u16 val; 8217e708baSVivien Didelot int err; 8317e708baSVivien Didelot 8417e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 8517e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 8617e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 8717e708baSVivien Didelot */ 8817e708baSVivien Didelot while (time_before(jiffies, timeout)) { 8982466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 9017e708baSVivien Didelot if (err) 9117e708baSVivien Didelot return err; 9217e708baSVivien Didelot 9382466921SVivien Didelot if (val & MV88E6XXX_G1_STS_INIT_READY) 9417e708baSVivien Didelot break; 9517e708baSVivien Didelot 9617e708baSVivien Didelot usleep_range(1000, 2000); 9717e708baSVivien Didelot } 9817e708baSVivien Didelot 9917e708baSVivien Didelot if (time_after(jiffies, timeout)) 10017e708baSVivien Didelot return -ETIMEDOUT; 10117e708baSVivien Didelot 10217e708baSVivien Didelot return 0; 10317e708baSVivien Didelot } 10417e708baSVivien Didelot 1054b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 1064b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 1074b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 1084b0c4817SVivien Didelot */ 1094b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 1104b0c4817SVivien Didelot { 1114b0c4817SVivien Didelot u16 reg; 1124b0c4817SVivien Didelot int err; 1134b0c4817SVivien Didelot 1144b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 1154b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 1164b0c4817SVivien Didelot if (err) 1174b0c4817SVivien Didelot return err; 1184b0c4817SVivien Didelot 1194b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 1204b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 1214b0c4817SVivien Didelot if (err) 1224b0c4817SVivien Didelot return err; 1234b0c4817SVivien Didelot 1244b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 1254b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 1264b0c4817SVivien Didelot if (err) 1274b0c4817SVivien Didelot return err; 1284b0c4817SVivien Didelot 1294b0c4817SVivien Didelot return 0; 1304b0c4817SVivien Didelot } 1314b0c4817SVivien Didelot 13217e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 13317e708baSVivien Didelot 13417e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 13517e708baSVivien Didelot { 13617e708baSVivien Didelot u16 val; 13717e708baSVivien Didelot int err; 13817e708baSVivien Didelot 13917e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 14017e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 14117e708baSVivien Didelot */ 142d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 14317e708baSVivien Didelot if (err) 14417e708baSVivien Didelot return err; 14517e708baSVivien Didelot 146d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 147d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 14817e708baSVivien Didelot 149d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 15017e708baSVivien Didelot if (err) 15117e708baSVivien Didelot return err; 15217e708baSVivien Didelot 15317e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 15417e708baSVivien Didelot if (err) 15517e708baSVivien Didelot return err; 15617e708baSVivien Didelot 15717e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 15817e708baSVivien Didelot } 15917e708baSVivien Didelot 1601f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 1611f71836fSRasmus Villemoes { 1621f71836fSRasmus Villemoes u16 val; 1631f71836fSRasmus Villemoes int err; 1641f71836fSRasmus Villemoes 1651f71836fSRasmus Villemoes /* Set the SWReset bit 15 */ 1661f71836fSRasmus Villemoes err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 1671f71836fSRasmus Villemoes if (err) 1681f71836fSRasmus Villemoes return err; 1691f71836fSRasmus Villemoes 1701f71836fSRasmus Villemoes val |= MV88E6XXX_G1_CTL1_SW_RESET; 1711f71836fSRasmus Villemoes 1721f71836fSRasmus Villemoes err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 1731f71836fSRasmus Villemoes if (err) 1741f71836fSRasmus Villemoes return err; 1751f71836fSRasmus Villemoes 1761f71836fSRasmus Villemoes return mv88e6xxx_g1_wait_init_ready(chip); 1771f71836fSRasmus Villemoes } 1781f71836fSRasmus Villemoes 17917e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 18017e708baSVivien Didelot { 18117e708baSVivien Didelot int err; 18217e708baSVivien Didelot 1837358fd80SRasmus Villemoes err = mv88e6250_g1_reset(chip); 18417e708baSVivien Didelot if (err) 18517e708baSVivien Didelot return err; 18617e708baSVivien Didelot 18717e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 18817e708baSVivien Didelot } 18917e708baSVivien Didelot 190a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 191a199d8b6SVivien Didelot { 192a199d8b6SVivien Didelot u16 val; 193a199d8b6SVivien Didelot int err; 194a199d8b6SVivien Didelot 195d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 196a199d8b6SVivien Didelot if (err) 197a199d8b6SVivien Didelot return err; 198a199d8b6SVivien Didelot 199d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 200a199d8b6SVivien Didelot 201d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 202a199d8b6SVivien Didelot if (err) 203a199d8b6SVivien Didelot return err; 204a199d8b6SVivien Didelot 205a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 206a199d8b6SVivien Didelot } 207a199d8b6SVivien Didelot 208a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 209a199d8b6SVivien Didelot { 210a199d8b6SVivien Didelot u16 val; 211a199d8b6SVivien Didelot int err; 212a199d8b6SVivien Didelot 213d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 214a199d8b6SVivien Didelot if (err) 215a199d8b6SVivien Didelot return err; 216a199d8b6SVivien Didelot 217d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 218a199d8b6SVivien Didelot 219d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 220a199d8b6SVivien Didelot if (err) 221a199d8b6SVivien Didelot return err; 222a199d8b6SVivien Didelot 223a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 224a199d8b6SVivien Didelot } 225a199d8b6SVivien Didelot 22693e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 22793e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 22893e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 22993e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 23093e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 23193e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 23293e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 23393e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 23493e18d61SVivien Didelot */ 23593e18d61SVivien Didelot 23693e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 23793e18d61SVivien Didelot { 23893e18d61SVivien Didelot int err; 23993e18d61SVivien Didelot 24093e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 24193e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 24293e18d61SVivien Didelot if (err) 24393e18d61SVivien Didelot return err; 24493e18d61SVivien Didelot 24593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 24693e18d61SVivien Didelot if (err) 24793e18d61SVivien Didelot return err; 24893e18d61SVivien Didelot 24993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 25093e18d61SVivien Didelot if (err) 25193e18d61SVivien Didelot return err; 25293e18d61SVivien Didelot 25393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 25493e18d61SVivien Didelot if (err) 25593e18d61SVivien Didelot return err; 25693e18d61SVivien Didelot 25793e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 25893e18d61SVivien Didelot if (err) 25993e18d61SVivien Didelot return err; 26093e18d61SVivien Didelot 26193e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 26293e18d61SVivien Didelot if (err) 26393e18d61SVivien Didelot return err; 26493e18d61SVivien Didelot 26593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 26693e18d61SVivien Didelot if (err) 26793e18d61SVivien Didelot return err; 26893e18d61SVivien Didelot 26993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 27093e18d61SVivien Didelot if (err) 27193e18d61SVivien Didelot return err; 27293e18d61SVivien Didelot 27393e18d61SVivien Didelot return 0; 27493e18d61SVivien Didelot } 27593e18d61SVivien Didelot 27693e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 27793e18d61SVivien Didelot 27893e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 27993e18d61SVivien Didelot { 28093e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 28193e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 28293e18d61SVivien Didelot } 28393e18d61SVivien Didelot 284df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 285df63b0d9SRasmus Villemoes { 286df63b0d9SRasmus Villemoes /* Reset the IEEE Tag priorities to defaults */ 287df63b0d9SRasmus Villemoes return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 288df63b0d9SRasmus Villemoes } 289df63b0d9SRasmus Villemoes 29033641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 29133641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 29233641994SAndrew Lunn 29333641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 29433641994SAndrew Lunn { 29533641994SAndrew Lunn u16 reg; 29633641994SAndrew Lunn int err; 29733641994SAndrew Lunn 298101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 29933641994SAndrew Lunn if (err) 30033641994SAndrew Lunn return err; 30133641994SAndrew Lunn 302101515c8SVivien Didelot reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 303101515c8SVivien Didelot MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 30433641994SAndrew Lunn 305101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 306101515c8SVivien Didelot port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 30733641994SAndrew Lunn 308101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 30933641994SAndrew Lunn } 31033641994SAndrew Lunn 31133641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 31233641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 31333641994SAndrew Lunn * egress it 31433641994SAndrew Lunn */ 31533641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 31633641994SAndrew Lunn { 31733641994SAndrew Lunn u16 reg; 31833641994SAndrew Lunn int err; 31933641994SAndrew Lunn 320101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 32133641994SAndrew Lunn if (err) 32233641994SAndrew Lunn return err; 32333641994SAndrew Lunn 324101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 325101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 32633641994SAndrew Lunn 327101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 32833641994SAndrew Lunn } 32933641994SAndrew Lunn 33033641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 33133641994SAndrew Lunn u16 pointer, u8 data) 33233641994SAndrew Lunn { 33333641994SAndrew Lunn u16 reg; 33433641994SAndrew Lunn 335101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 33633641994SAndrew Lunn 337101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 33833641994SAndrew Lunn } 33933641994SAndrew Lunn 34033641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 34133641994SAndrew Lunn { 342101515c8SVivien Didelot u16 ptr; 34333641994SAndrew Lunn int err; 34433641994SAndrew Lunn 345101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 346101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 34733641994SAndrew Lunn if (err) 34833641994SAndrew Lunn return err; 34933641994SAndrew Lunn 350101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 351101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 352101515c8SVivien Didelot if (err) 353101515c8SVivien Didelot return err; 354101515c8SVivien Didelot 355101515c8SVivien Didelot return 0; 35633641994SAndrew Lunn } 35733641994SAndrew Lunn 35833641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 35933641994SAndrew Lunn { 360101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 361101515c8SVivien Didelot 362101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 36333641994SAndrew Lunn } 36433641994SAndrew Lunn 3656e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3666e55f698SAndrew Lunn { 367101515c8SVivien Didelot u16 ptr; 3686e55f698SAndrew Lunn int err; 3696e55f698SAndrew Lunn 370989f405aSRasmus Villemoes /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 371989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 372101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3736e55f698SAndrew Lunn if (err) 3746e55f698SAndrew Lunn return err; 3756e55f698SAndrew Lunn 376989f405aSRasmus Villemoes /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 377989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 378101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3796e55f698SAndrew Lunn if (err) 3806e55f698SAndrew Lunn return err; 3816e55f698SAndrew Lunn 382989f405aSRasmus Villemoes /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 383989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 384101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3856e55f698SAndrew Lunn if (err) 3866e55f698SAndrew Lunn return err; 3876e55f698SAndrew Lunn 388989f405aSRasmus Villemoes /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 389989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 390101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 391101515c8SVivien Didelot if (err) 392101515c8SVivien Didelot return err; 393101515c8SVivien Didelot 394101515c8SVivien Didelot return 0; 3956e55f698SAndrew Lunn } 3966e55f698SAndrew Lunn 397de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 398de227387SAndrew Lunn 39902317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 40002317e68SVivien Didelot u16 val) 40102317e68SVivien Didelot { 40202317e68SVivien Didelot u16 reg; 40302317e68SVivien Didelot int err; 40402317e68SVivien Didelot 40502317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 40602317e68SVivien Didelot if (err) 40702317e68SVivien Didelot return err; 40802317e68SVivien Didelot 40902317e68SVivien Didelot reg &= ~mask; 41002317e68SVivien Didelot reg |= val & mask; 41102317e68SVivien Didelot 41202317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 41302317e68SVivien Didelot } 41402317e68SVivien Didelot 41502317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 41602317e68SVivien Didelot { 41702317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 41802317e68SVivien Didelot 41902317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 42002317e68SVivien Didelot } 42102317e68SVivien Didelot 4229e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4239e5baf9bSVivien Didelot { 4249e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4259e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4269e5baf9bSVivien Didelot } 4279e5baf9bSVivien Didelot 4289e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4299e5baf9bSVivien Didelot { 4309e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4319e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4329e5baf9bSVivien Didelot } 4339e5baf9bSVivien Didelot 4349e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4359e5baf9bSVivien Didelot { 4369e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4379e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4389e5baf9bSVivien Didelot } 4399e5baf9bSVivien Didelot 440de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 441de227387SAndrew Lunn { 442408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 443408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 444408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 445de227387SAndrew Lunn } 446de227387SAndrew Lunn 44723c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 44823c98919SVivien Didelot { 44923c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 45023c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 45123c98919SVivien Didelot index); 45223c98919SVivien Didelot } 45323c98919SVivien Didelot 454de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 455de227387SAndrew Lunn 456cfd10888SRasmus Villemoes static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 457a605a0feSAndrew Lunn { 45857d1ef38SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 45957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY); 460a605a0feSAndrew Lunn } 461a605a0feSAndrew Lunn 46240cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 46340cff8fcSAndrew Lunn { 46440cff8fcSAndrew Lunn u16 val; 46540cff8fcSAndrew Lunn int err; 46640cff8fcSAndrew Lunn 46740cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 46840cff8fcSAndrew Lunn if (err) 46940cff8fcSAndrew Lunn return err; 47040cff8fcSAndrew Lunn 47140cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 47240cff8fcSAndrew Lunn 47340cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 47440cff8fcSAndrew Lunn 47540cff8fcSAndrew Lunn return err; 47640cff8fcSAndrew Lunn } 47740cff8fcSAndrew Lunn 478a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 479a605a0feSAndrew Lunn { 480a605a0feSAndrew Lunn int err; 481a605a0feSAndrew Lunn 482a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 48357d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 48457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 48557d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 48657d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 487a605a0feSAndrew Lunn if (err) 488a605a0feSAndrew Lunn return err; 489a605a0feSAndrew Lunn 490a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 491a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 492a605a0feSAndrew Lunn } 493a605a0feSAndrew Lunn 494a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 495a605a0feSAndrew Lunn { 496a605a0feSAndrew Lunn port = (port + 1) << 5; 497a605a0feSAndrew Lunn 498a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 499a605a0feSAndrew Lunn } 50079523473SAndrew Lunn 50179523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 50279523473SAndrew Lunn { 50379523473SAndrew Lunn int err; 50479523473SAndrew Lunn 50579523473SAndrew Lunn port = (port + 1) << 5; 50679523473SAndrew Lunn 50779523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 50857d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 50957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 51057d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 51179523473SAndrew Lunn if (err) 51279523473SAndrew Lunn return err; 51379523473SAndrew Lunn 51479523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 51579523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 51679523473SAndrew Lunn } 5177f9ef3afSAndrew Lunn 5187f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 5197f9ef3afSAndrew Lunn { 5207f9ef3afSAndrew Lunn u32 value; 5217f9ef3afSAndrew Lunn u16 reg; 5227f9ef3afSAndrew Lunn int err; 5237f9ef3afSAndrew Lunn 5247f9ef3afSAndrew Lunn *val = 0; 5257f9ef3afSAndrew Lunn 52657d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 52757d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 52857d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5297f9ef3afSAndrew Lunn if (err) 5307f9ef3afSAndrew Lunn return; 5317f9ef3afSAndrew Lunn 5327f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5337f9ef3afSAndrew Lunn if (err) 5347f9ef3afSAndrew Lunn return; 5357f9ef3afSAndrew Lunn 53657d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5377f9ef3afSAndrew Lunn if (err) 5387f9ef3afSAndrew Lunn return; 5397f9ef3afSAndrew Lunn 5407f9ef3afSAndrew Lunn value = reg << 16; 5417f9ef3afSAndrew Lunn 54257d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5437f9ef3afSAndrew Lunn if (err) 5447f9ef3afSAndrew Lunn return; 5457f9ef3afSAndrew Lunn 5467f9ef3afSAndrew Lunn *val = value | reg; 5477f9ef3afSAndrew Lunn } 54840cff8fcSAndrew Lunn 54940cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 55040cff8fcSAndrew Lunn { 55140cff8fcSAndrew Lunn int err; 55240cff8fcSAndrew Lunn u16 val; 55340cff8fcSAndrew Lunn 55440cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 55540cff8fcSAndrew Lunn if (err) 55640cff8fcSAndrew Lunn return err; 55740cff8fcSAndrew Lunn 558a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 559a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 56040cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 56140cff8fcSAndrew Lunn 56240cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 56340cff8fcSAndrew Lunn if (err) 56440cff8fcSAndrew Lunn return err; 56540cff8fcSAndrew Lunn 56640cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 56740cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 56840cff8fcSAndrew Lunn } 569