1a935c052SVivien Didelot /* 2a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 3a935c052SVivien Didelot * 4a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 5a935c052SVivien Didelot * 64333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 74333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 8a935c052SVivien Didelot * 9a935c052SVivien Didelot * This program is free software; you can redistribute it and/or modify 10a935c052SVivien Didelot * it under the terms of the GNU General Public License as published by 11a935c052SVivien Didelot * the Free Software Foundation; either version 2 of the License, or 12a935c052SVivien Didelot * (at your option) any later version. 13a935c052SVivien Didelot */ 14a935c052SVivien Didelot 15101515c8SVivien Didelot #include <linux/bitfield.h> 16101515c8SVivien Didelot 174d5f2ba7SVivien Didelot #include "chip.h" 18a935c052SVivien Didelot #include "global1.h" 19a935c052SVivien Didelot 20a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 21a935c052SVivien Didelot { 22a935c052SVivien Didelot int addr = chip->info->global1_addr; 23a935c052SVivien Didelot 24a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 25a935c052SVivien Didelot } 26a935c052SVivien Didelot 27a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 28a935c052SVivien Didelot { 29a935c052SVivien Didelot int addr = chip->info->global1_addr; 30a935c052SVivien Didelot 31a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 32a935c052SVivien Didelot } 33a935c052SVivien Didelot 34a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 35a935c052SVivien Didelot { 36a935c052SVivien Didelot return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 37a935c052SVivien Didelot } 38a605a0feSAndrew Lunn 3917e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 4017e708baSVivien Didelot 41a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 42a199d8b6SVivien Didelot { 43a199d8b6SVivien Didelot u16 state; 44a199d8b6SVivien Didelot int i, err; 45a199d8b6SVivien Didelot 46a199d8b6SVivien Didelot for (i = 0; i < 16; i++) { 4782466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 48a199d8b6SVivien Didelot if (err) 49a199d8b6SVivien Didelot return err; 50a199d8b6SVivien Didelot 51a199d8b6SVivien Didelot /* Check the value of the PPUState bits 15:14 */ 5282466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 5382466921SVivien Didelot if (state != MV88E6185_G1_STS_PPU_STATE_POLLING) 54a199d8b6SVivien Didelot return 0; 55a199d8b6SVivien Didelot 56a199d8b6SVivien Didelot usleep_range(1000, 2000); 57a199d8b6SVivien Didelot } 58a199d8b6SVivien Didelot 59a199d8b6SVivien Didelot return -ETIMEDOUT; 60a199d8b6SVivien Didelot } 61a199d8b6SVivien Didelot 6217e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 6317e708baSVivien Didelot { 6417e708baSVivien Didelot u16 state; 6517e708baSVivien Didelot int i, err; 6617e708baSVivien Didelot 6717e708baSVivien Didelot for (i = 0; i < 16; ++i) { 6882466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 6917e708baSVivien Didelot if (err) 7017e708baSVivien Didelot return err; 7117e708baSVivien Didelot 7217e708baSVivien Didelot /* Check the value of the PPUState bits 15:14 */ 7382466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 7482466921SVivien Didelot if (state == MV88E6185_G1_STS_PPU_STATE_POLLING) 7517e708baSVivien Didelot return 0; 7617e708baSVivien Didelot 7717e708baSVivien Didelot usleep_range(1000, 2000); 7817e708baSVivien Didelot } 7917e708baSVivien Didelot 8017e708baSVivien Didelot return -ETIMEDOUT; 8117e708baSVivien Didelot } 8217e708baSVivien Didelot 8317e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 8417e708baSVivien Didelot { 8517e708baSVivien Didelot u16 state; 8617e708baSVivien Didelot int i, err; 8717e708baSVivien Didelot 8817e708baSVivien Didelot for (i = 0; i < 16; ++i) { 8982466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 9017e708baSVivien Didelot if (err) 9117e708baSVivien Didelot return err; 9217e708baSVivien Didelot 9317e708baSVivien Didelot /* Check the value of the PPUState (or InitState) bit 15 */ 9482466921SVivien Didelot if (state & MV88E6352_G1_STS_PPU_STATE) 9517e708baSVivien Didelot return 0; 9617e708baSVivien Didelot 9717e708baSVivien Didelot usleep_range(1000, 2000); 9817e708baSVivien Didelot } 9917e708baSVivien Didelot 10017e708baSVivien Didelot return -ETIMEDOUT; 10117e708baSVivien Didelot } 10217e708baSVivien Didelot 10317e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 10417e708baSVivien Didelot { 10517e708baSVivien Didelot const unsigned long timeout = jiffies + 1 * HZ; 10617e708baSVivien Didelot u16 val; 10717e708baSVivien Didelot int err; 10817e708baSVivien Didelot 10917e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 11017e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 11117e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 11217e708baSVivien Didelot */ 11317e708baSVivien Didelot while (time_before(jiffies, timeout)) { 11482466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 11517e708baSVivien Didelot if (err) 11617e708baSVivien Didelot return err; 11717e708baSVivien Didelot 11882466921SVivien Didelot if (val & MV88E6XXX_G1_STS_INIT_READY) 11917e708baSVivien Didelot break; 12017e708baSVivien Didelot 12117e708baSVivien Didelot usleep_range(1000, 2000); 12217e708baSVivien Didelot } 12317e708baSVivien Didelot 12417e708baSVivien Didelot if (time_after(jiffies, timeout)) 12517e708baSVivien Didelot return -ETIMEDOUT; 12617e708baSVivien Didelot 12717e708baSVivien Didelot return 0; 12817e708baSVivien Didelot } 12917e708baSVivien Didelot 1304b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 1314b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 1324b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 1334b0c4817SVivien Didelot */ 1344b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 1354b0c4817SVivien Didelot { 1364b0c4817SVivien Didelot u16 reg; 1374b0c4817SVivien Didelot int err; 1384b0c4817SVivien Didelot 1394b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 1404b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 1414b0c4817SVivien Didelot if (err) 1424b0c4817SVivien Didelot return err; 1434b0c4817SVivien Didelot 1444b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 1454b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 1464b0c4817SVivien Didelot if (err) 1474b0c4817SVivien Didelot return err; 1484b0c4817SVivien Didelot 1494b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 1504b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 1514b0c4817SVivien Didelot if (err) 1524b0c4817SVivien Didelot return err; 1534b0c4817SVivien Didelot 1544b0c4817SVivien Didelot return 0; 1554b0c4817SVivien Didelot } 1564b0c4817SVivien Didelot 15717e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 15817e708baSVivien Didelot 15917e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 16017e708baSVivien Didelot { 16117e708baSVivien Didelot u16 val; 16217e708baSVivien Didelot int err; 16317e708baSVivien Didelot 16417e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 16517e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 16617e708baSVivien Didelot */ 167d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 16817e708baSVivien Didelot if (err) 16917e708baSVivien Didelot return err; 17017e708baSVivien Didelot 171d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 172d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 17317e708baSVivien Didelot 174d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 17517e708baSVivien Didelot if (err) 17617e708baSVivien Didelot return err; 17717e708baSVivien Didelot 17817e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 17917e708baSVivien Didelot if (err) 18017e708baSVivien Didelot return err; 18117e708baSVivien Didelot 18217e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 18317e708baSVivien Didelot } 18417e708baSVivien Didelot 18517e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 18617e708baSVivien Didelot { 18717e708baSVivien Didelot u16 val; 18817e708baSVivien Didelot int err; 18917e708baSVivien Didelot 19017e708baSVivien Didelot /* Set the SWReset bit 15 */ 191d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 19217e708baSVivien Didelot if (err) 19317e708baSVivien Didelot return err; 19417e708baSVivien Didelot 195d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 19617e708baSVivien Didelot 197d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 19817e708baSVivien Didelot if (err) 19917e708baSVivien Didelot return err; 20017e708baSVivien Didelot 20117e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 20217e708baSVivien Didelot if (err) 20317e708baSVivien Didelot return err; 20417e708baSVivien Didelot 20517e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 20617e708baSVivien Didelot } 20717e708baSVivien Didelot 208a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 209a199d8b6SVivien Didelot { 210a199d8b6SVivien Didelot u16 val; 211a199d8b6SVivien Didelot int err; 212a199d8b6SVivien Didelot 213d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 214a199d8b6SVivien Didelot if (err) 215a199d8b6SVivien Didelot return err; 216a199d8b6SVivien Didelot 217d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 218a199d8b6SVivien Didelot 219d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 220a199d8b6SVivien Didelot if (err) 221a199d8b6SVivien Didelot return err; 222a199d8b6SVivien Didelot 223a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 224a199d8b6SVivien Didelot } 225a199d8b6SVivien Didelot 226a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 227a199d8b6SVivien Didelot { 228a199d8b6SVivien Didelot u16 val; 229a199d8b6SVivien Didelot int err; 230a199d8b6SVivien Didelot 231d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 232a199d8b6SVivien Didelot if (err) 233a199d8b6SVivien Didelot return err; 234a199d8b6SVivien Didelot 235d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 236a199d8b6SVivien Didelot 237d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 238a199d8b6SVivien Didelot if (err) 239a199d8b6SVivien Didelot return err; 240a199d8b6SVivien Didelot 241a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 242a199d8b6SVivien Didelot } 243a199d8b6SVivien Didelot 24433641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 24533641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 24633641994SAndrew Lunn 24733641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 24833641994SAndrew Lunn { 24933641994SAndrew Lunn u16 reg; 25033641994SAndrew Lunn int err; 25133641994SAndrew Lunn 252101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 25333641994SAndrew Lunn if (err) 25433641994SAndrew Lunn return err; 25533641994SAndrew Lunn 256101515c8SVivien Didelot reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 257101515c8SVivien Didelot MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 25833641994SAndrew Lunn 259101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 260101515c8SVivien Didelot port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 26133641994SAndrew Lunn 262101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 26333641994SAndrew Lunn } 26433641994SAndrew Lunn 26533641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 26633641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 26733641994SAndrew Lunn * egress it 26833641994SAndrew Lunn */ 26933641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 27033641994SAndrew Lunn { 27133641994SAndrew Lunn u16 reg; 27233641994SAndrew Lunn int err; 27333641994SAndrew Lunn 274101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 27533641994SAndrew Lunn if (err) 27633641994SAndrew Lunn return err; 27733641994SAndrew Lunn 278101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 279101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 28033641994SAndrew Lunn 281101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 28233641994SAndrew Lunn } 28333641994SAndrew Lunn 28433641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 28533641994SAndrew Lunn u16 pointer, u8 data) 28633641994SAndrew Lunn { 28733641994SAndrew Lunn u16 reg; 28833641994SAndrew Lunn 289101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 29033641994SAndrew Lunn 291101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 29233641994SAndrew Lunn } 29333641994SAndrew Lunn 29433641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 29533641994SAndrew Lunn { 296101515c8SVivien Didelot u16 ptr; 29733641994SAndrew Lunn int err; 29833641994SAndrew Lunn 299101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 300101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 30133641994SAndrew Lunn if (err) 30233641994SAndrew Lunn return err; 30333641994SAndrew Lunn 304101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 305101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 306101515c8SVivien Didelot if (err) 307101515c8SVivien Didelot return err; 308101515c8SVivien Didelot 309101515c8SVivien Didelot return 0; 31033641994SAndrew Lunn } 31133641994SAndrew Lunn 31233641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 31333641994SAndrew Lunn { 314101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 315101515c8SVivien Didelot 316101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 31733641994SAndrew Lunn } 31833641994SAndrew Lunn 3196e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3206e55f698SAndrew Lunn { 321101515c8SVivien Didelot u16 ptr; 3226e55f698SAndrew Lunn int err; 3236e55f698SAndrew Lunn 3246e55f698SAndrew Lunn /* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */ 325101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO; 326101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3276e55f698SAndrew Lunn if (err) 3286e55f698SAndrew Lunn return err; 3296e55f698SAndrew Lunn 3306e55f698SAndrew Lunn /* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */ 331101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI; 332101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3336e55f698SAndrew Lunn if (err) 3346e55f698SAndrew Lunn return err; 3356e55f698SAndrew Lunn 3366e55f698SAndrew Lunn /* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */ 337101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO; 338101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3396e55f698SAndrew Lunn if (err) 3406e55f698SAndrew Lunn return err; 3416e55f698SAndrew Lunn 3426e55f698SAndrew Lunn /* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */ 343101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI; 344101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 345101515c8SVivien Didelot if (err) 346101515c8SVivien Didelot return err; 347101515c8SVivien Didelot 348101515c8SVivien Didelot return 0; 3496e55f698SAndrew Lunn } 3506e55f698SAndrew Lunn 351de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 352de227387SAndrew Lunn 35302317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 35402317e68SVivien Didelot u16 val) 35502317e68SVivien Didelot { 35602317e68SVivien Didelot u16 reg; 35702317e68SVivien Didelot int err; 35802317e68SVivien Didelot 35902317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 36002317e68SVivien Didelot if (err) 36102317e68SVivien Didelot return err; 36202317e68SVivien Didelot 36302317e68SVivien Didelot reg &= ~mask; 36402317e68SVivien Didelot reg |= val & mask; 36502317e68SVivien Didelot 36602317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 36702317e68SVivien Didelot } 36802317e68SVivien Didelot 36902317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 37002317e68SVivien Didelot { 37102317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 37202317e68SVivien Didelot 37302317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 37402317e68SVivien Didelot } 37502317e68SVivien Didelot 3769e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 3779e5baf9bSVivien Didelot { 3789e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 3799e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 3809e5baf9bSVivien Didelot } 3819e5baf9bSVivien Didelot 3829e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 3839e5baf9bSVivien Didelot { 3849e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 3859e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 3869e5baf9bSVivien Didelot } 3879e5baf9bSVivien Didelot 3889e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 3899e5baf9bSVivien Didelot { 3909e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 3919e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 3929e5baf9bSVivien Didelot } 3939e5baf9bSVivien Didelot 394de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 395de227387SAndrew Lunn { 396408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 397408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 398408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 399de227387SAndrew Lunn } 400de227387SAndrew Lunn 40123c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 40223c98919SVivien Didelot { 40323c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 40423c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 40523c98919SVivien Didelot index); 40623c98919SVivien Didelot } 40723c98919SVivien Didelot 408de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 409de227387SAndrew Lunn 4107f9ef3afSAndrew Lunn int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 411a605a0feSAndrew Lunn { 41257d1ef38SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 41357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY); 414a605a0feSAndrew Lunn } 415a605a0feSAndrew Lunn 41640cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 41740cff8fcSAndrew Lunn { 41840cff8fcSAndrew Lunn u16 val; 41940cff8fcSAndrew Lunn int err; 42040cff8fcSAndrew Lunn 42140cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 42240cff8fcSAndrew Lunn if (err) 42340cff8fcSAndrew Lunn return err; 42440cff8fcSAndrew Lunn 42540cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 42640cff8fcSAndrew Lunn 42740cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 42840cff8fcSAndrew Lunn 42940cff8fcSAndrew Lunn return err; 43040cff8fcSAndrew Lunn } 43140cff8fcSAndrew Lunn 432a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 433a605a0feSAndrew Lunn { 434a605a0feSAndrew Lunn int err; 435a605a0feSAndrew Lunn 436a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 43757d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 43857d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 43957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 44057d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 441a605a0feSAndrew Lunn if (err) 442a605a0feSAndrew Lunn return err; 443a605a0feSAndrew Lunn 444a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 445a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 446a605a0feSAndrew Lunn } 447a605a0feSAndrew Lunn 448a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 449a605a0feSAndrew Lunn { 450a605a0feSAndrew Lunn port = (port + 1) << 5; 451a605a0feSAndrew Lunn 452a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 453a605a0feSAndrew Lunn } 45479523473SAndrew Lunn 45579523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 45679523473SAndrew Lunn { 45779523473SAndrew Lunn int err; 45879523473SAndrew Lunn 45979523473SAndrew Lunn port = (port + 1) << 5; 46079523473SAndrew Lunn 46179523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 46257d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 46357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 46457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 46579523473SAndrew Lunn if (err) 46679523473SAndrew Lunn return err; 46779523473SAndrew Lunn 46879523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 46979523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 47079523473SAndrew Lunn } 4717f9ef3afSAndrew Lunn 4727f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 4737f9ef3afSAndrew Lunn { 4747f9ef3afSAndrew Lunn u32 value; 4757f9ef3afSAndrew Lunn u16 reg; 4767f9ef3afSAndrew Lunn int err; 4777f9ef3afSAndrew Lunn 4787f9ef3afSAndrew Lunn *val = 0; 4797f9ef3afSAndrew Lunn 48057d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 48157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 48257d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 4837f9ef3afSAndrew Lunn if (err) 4847f9ef3afSAndrew Lunn return; 4857f9ef3afSAndrew Lunn 4867f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 4877f9ef3afSAndrew Lunn if (err) 4887f9ef3afSAndrew Lunn return; 4897f9ef3afSAndrew Lunn 49057d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 4917f9ef3afSAndrew Lunn if (err) 4927f9ef3afSAndrew Lunn return; 4937f9ef3afSAndrew Lunn 4947f9ef3afSAndrew Lunn value = reg << 16; 4957f9ef3afSAndrew Lunn 49657d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 4977f9ef3afSAndrew Lunn if (err) 4987f9ef3afSAndrew Lunn return; 4997f9ef3afSAndrew Lunn 5007f9ef3afSAndrew Lunn *val = value | reg; 5017f9ef3afSAndrew Lunn } 50240cff8fcSAndrew Lunn 50340cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 50440cff8fcSAndrew Lunn { 50540cff8fcSAndrew Lunn int err; 50640cff8fcSAndrew Lunn u16 val; 50740cff8fcSAndrew Lunn 50840cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 50940cff8fcSAndrew Lunn if (err) 51040cff8fcSAndrew Lunn return err; 51140cff8fcSAndrew Lunn 51240cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 51340cff8fcSAndrew Lunn 51440cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 51540cff8fcSAndrew Lunn if (err) 51640cff8fcSAndrew Lunn return err; 51740cff8fcSAndrew Lunn 51840cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 51940cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 52040cff8fcSAndrew Lunn } 521