12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11101515c8SVivien Didelot #include <linux/bitfield.h> 12101515c8SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14a935c052SVivien Didelot #include "global1.h" 15a935c052SVivien Didelot 16a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17a935c052SVivien Didelot { 18a935c052SVivien Didelot int addr = chip->info->global1_addr; 19a935c052SVivien Didelot 20a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 21a935c052SVivien Didelot } 22a935c052SVivien Didelot 23a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24a935c052SVivien Didelot { 25a935c052SVivien Didelot int addr = chip->info->global1_addr; 26a935c052SVivien Didelot 27a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 28a935c052SVivien Didelot } 29a935c052SVivien Didelot 30a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 31a935c052SVivien Didelot { 32a935c052SVivien Didelot return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 33a935c052SVivien Didelot } 34a605a0feSAndrew Lunn 3517e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 3617e708baSVivien Didelot 37a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 38a199d8b6SVivien Didelot { 39a199d8b6SVivien Didelot u16 state; 40a199d8b6SVivien Didelot int i, err; 41a199d8b6SVivien Didelot 42a199d8b6SVivien Didelot for (i = 0; i < 16; i++) { 4382466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 44a199d8b6SVivien Didelot if (err) 45a199d8b6SVivien Didelot return err; 46a199d8b6SVivien Didelot 47a199d8b6SVivien Didelot /* Check the value of the PPUState bits 15:14 */ 4882466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 4982466921SVivien Didelot if (state != MV88E6185_G1_STS_PPU_STATE_POLLING) 50a199d8b6SVivien Didelot return 0; 51a199d8b6SVivien Didelot 52a199d8b6SVivien Didelot usleep_range(1000, 2000); 53a199d8b6SVivien Didelot } 54a199d8b6SVivien Didelot 55a199d8b6SVivien Didelot return -ETIMEDOUT; 56a199d8b6SVivien Didelot } 57a199d8b6SVivien Didelot 5817e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 5917e708baSVivien Didelot { 6017e708baSVivien Didelot u16 state; 6117e708baSVivien Didelot int i, err; 6217e708baSVivien Didelot 6317e708baSVivien Didelot for (i = 0; i < 16; ++i) { 6482466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 6517e708baSVivien Didelot if (err) 6617e708baSVivien Didelot return err; 6717e708baSVivien Didelot 6817e708baSVivien Didelot /* Check the value of the PPUState bits 15:14 */ 6982466921SVivien Didelot state &= MV88E6185_G1_STS_PPU_STATE_MASK; 7082466921SVivien Didelot if (state == MV88E6185_G1_STS_PPU_STATE_POLLING) 7117e708baSVivien Didelot return 0; 7217e708baSVivien Didelot 7317e708baSVivien Didelot usleep_range(1000, 2000); 7417e708baSVivien Didelot } 7517e708baSVivien Didelot 7617e708baSVivien Didelot return -ETIMEDOUT; 7717e708baSVivien Didelot } 7817e708baSVivien Didelot 7917e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 8017e708baSVivien Didelot { 8117e708baSVivien Didelot u16 state; 8217e708baSVivien Didelot int i, err; 8317e708baSVivien Didelot 8417e708baSVivien Didelot for (i = 0; i < 16; ++i) { 8582466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &state); 8617e708baSVivien Didelot if (err) 8717e708baSVivien Didelot return err; 8817e708baSVivien Didelot 8917e708baSVivien Didelot /* Check the value of the PPUState (or InitState) bit 15 */ 9082466921SVivien Didelot if (state & MV88E6352_G1_STS_PPU_STATE) 9117e708baSVivien Didelot return 0; 9217e708baSVivien Didelot 9317e708baSVivien Didelot usleep_range(1000, 2000); 9417e708baSVivien Didelot } 9517e708baSVivien Didelot 9617e708baSVivien Didelot return -ETIMEDOUT; 9717e708baSVivien Didelot } 9817e708baSVivien Didelot 9917e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 10017e708baSVivien Didelot { 10117e708baSVivien Didelot const unsigned long timeout = jiffies + 1 * HZ; 10217e708baSVivien Didelot u16 val; 10317e708baSVivien Didelot int err; 10417e708baSVivien Didelot 10517e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 10617e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 10717e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 10817e708baSVivien Didelot */ 10917e708baSVivien Didelot while (time_before(jiffies, timeout)) { 11082466921SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val); 11117e708baSVivien Didelot if (err) 11217e708baSVivien Didelot return err; 11317e708baSVivien Didelot 11482466921SVivien Didelot if (val & MV88E6XXX_G1_STS_INIT_READY) 11517e708baSVivien Didelot break; 11617e708baSVivien Didelot 11717e708baSVivien Didelot usleep_range(1000, 2000); 11817e708baSVivien Didelot } 11917e708baSVivien Didelot 12017e708baSVivien Didelot if (time_after(jiffies, timeout)) 12117e708baSVivien Didelot return -ETIMEDOUT; 12217e708baSVivien Didelot 12317e708baSVivien Didelot return 0; 12417e708baSVivien Didelot } 12517e708baSVivien Didelot 1264b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 1274b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 1284b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 1294b0c4817SVivien Didelot */ 1304b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 1314b0c4817SVivien Didelot { 1324b0c4817SVivien Didelot u16 reg; 1334b0c4817SVivien Didelot int err; 1344b0c4817SVivien Didelot 1354b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 1364b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 1374b0c4817SVivien Didelot if (err) 1384b0c4817SVivien Didelot return err; 1394b0c4817SVivien Didelot 1404b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 1414b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 1424b0c4817SVivien Didelot if (err) 1434b0c4817SVivien Didelot return err; 1444b0c4817SVivien Didelot 1454b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 1464b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 1474b0c4817SVivien Didelot if (err) 1484b0c4817SVivien Didelot return err; 1494b0c4817SVivien Didelot 1504b0c4817SVivien Didelot return 0; 1514b0c4817SVivien Didelot } 1524b0c4817SVivien Didelot 15317e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 15417e708baSVivien Didelot 15517e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 15617e708baSVivien Didelot { 15717e708baSVivien Didelot u16 val; 15817e708baSVivien Didelot int err; 15917e708baSVivien Didelot 16017e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 16117e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 16217e708baSVivien Didelot */ 163d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 16417e708baSVivien Didelot if (err) 16517e708baSVivien Didelot return err; 16617e708baSVivien Didelot 167d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 168d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 16917e708baSVivien Didelot 170d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 17117e708baSVivien Didelot if (err) 17217e708baSVivien Didelot return err; 17317e708baSVivien Didelot 17417e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 17517e708baSVivien Didelot if (err) 17617e708baSVivien Didelot return err; 17717e708baSVivien Didelot 17817e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 17917e708baSVivien Didelot } 18017e708baSVivien Didelot 18117e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 18217e708baSVivien Didelot { 18317e708baSVivien Didelot u16 val; 18417e708baSVivien Didelot int err; 18517e708baSVivien Didelot 18617e708baSVivien Didelot /* Set the SWReset bit 15 */ 187d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 18817e708baSVivien Didelot if (err) 18917e708baSVivien Didelot return err; 19017e708baSVivien Didelot 191d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 19217e708baSVivien Didelot 193d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 19417e708baSVivien Didelot if (err) 19517e708baSVivien Didelot return err; 19617e708baSVivien Didelot 19717e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 19817e708baSVivien Didelot if (err) 19917e708baSVivien Didelot return err; 20017e708baSVivien Didelot 20117e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 20217e708baSVivien Didelot } 20317e708baSVivien Didelot 204a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 205a199d8b6SVivien Didelot { 206a199d8b6SVivien Didelot u16 val; 207a199d8b6SVivien Didelot int err; 208a199d8b6SVivien Didelot 209d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 210a199d8b6SVivien Didelot if (err) 211a199d8b6SVivien Didelot return err; 212a199d8b6SVivien Didelot 213d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 214a199d8b6SVivien Didelot 215d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 216a199d8b6SVivien Didelot if (err) 217a199d8b6SVivien Didelot return err; 218a199d8b6SVivien Didelot 219a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 220a199d8b6SVivien Didelot } 221a199d8b6SVivien Didelot 222a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 223a199d8b6SVivien Didelot { 224a199d8b6SVivien Didelot u16 val; 225a199d8b6SVivien Didelot int err; 226a199d8b6SVivien Didelot 227d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 228a199d8b6SVivien Didelot if (err) 229a199d8b6SVivien Didelot return err; 230a199d8b6SVivien Didelot 231d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 232a199d8b6SVivien Didelot 233d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 234a199d8b6SVivien Didelot if (err) 235a199d8b6SVivien Didelot return err; 236a199d8b6SVivien Didelot 237a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 238a199d8b6SVivien Didelot } 239a199d8b6SVivien Didelot 24093e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 24193e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 24293e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 24393e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 24493e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 24593e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 24693e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 24793e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 24893e18d61SVivien Didelot */ 24993e18d61SVivien Didelot 25093e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 25193e18d61SVivien Didelot { 25293e18d61SVivien Didelot int err; 25393e18d61SVivien Didelot 25493e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 25593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 25693e18d61SVivien Didelot if (err) 25793e18d61SVivien Didelot return err; 25893e18d61SVivien Didelot 25993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 26093e18d61SVivien Didelot if (err) 26193e18d61SVivien Didelot return err; 26293e18d61SVivien Didelot 26393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 26493e18d61SVivien Didelot if (err) 26593e18d61SVivien Didelot return err; 26693e18d61SVivien Didelot 26793e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 26893e18d61SVivien Didelot if (err) 26993e18d61SVivien Didelot return err; 27093e18d61SVivien Didelot 27193e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 27293e18d61SVivien Didelot if (err) 27393e18d61SVivien Didelot return err; 27493e18d61SVivien Didelot 27593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 27693e18d61SVivien Didelot if (err) 27793e18d61SVivien Didelot return err; 27893e18d61SVivien Didelot 27993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 28093e18d61SVivien Didelot if (err) 28193e18d61SVivien Didelot return err; 28293e18d61SVivien Didelot 28393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 28493e18d61SVivien Didelot if (err) 28593e18d61SVivien Didelot return err; 28693e18d61SVivien Didelot 28793e18d61SVivien Didelot return 0; 28893e18d61SVivien Didelot } 28993e18d61SVivien Didelot 29093e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 29193e18d61SVivien Didelot 29293e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 29393e18d61SVivien Didelot { 29493e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 29593e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 29693e18d61SVivien Didelot } 29793e18d61SVivien Didelot 29833641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 29933641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 30033641994SAndrew Lunn 30133641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 30233641994SAndrew Lunn { 30333641994SAndrew Lunn u16 reg; 30433641994SAndrew Lunn int err; 30533641994SAndrew Lunn 306101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 30733641994SAndrew Lunn if (err) 30833641994SAndrew Lunn return err; 30933641994SAndrew Lunn 310101515c8SVivien Didelot reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 311101515c8SVivien Didelot MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 31233641994SAndrew Lunn 313101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 314101515c8SVivien Didelot port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 31533641994SAndrew Lunn 316101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 31733641994SAndrew Lunn } 31833641994SAndrew Lunn 31933641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 32033641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 32133641994SAndrew Lunn * egress it 32233641994SAndrew Lunn */ 32333641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 32433641994SAndrew Lunn { 32533641994SAndrew Lunn u16 reg; 32633641994SAndrew Lunn int err; 32733641994SAndrew Lunn 328101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 32933641994SAndrew Lunn if (err) 33033641994SAndrew Lunn return err; 33133641994SAndrew Lunn 332101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 333101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 33433641994SAndrew Lunn 335101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 33633641994SAndrew Lunn } 33733641994SAndrew Lunn 33833641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 33933641994SAndrew Lunn u16 pointer, u8 data) 34033641994SAndrew Lunn { 34133641994SAndrew Lunn u16 reg; 34233641994SAndrew Lunn 343101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 34433641994SAndrew Lunn 345101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 34633641994SAndrew Lunn } 34733641994SAndrew Lunn 34833641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 34933641994SAndrew Lunn { 350101515c8SVivien Didelot u16 ptr; 35133641994SAndrew Lunn int err; 35233641994SAndrew Lunn 353101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 354101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 35533641994SAndrew Lunn if (err) 35633641994SAndrew Lunn return err; 35733641994SAndrew Lunn 358101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 359101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 360101515c8SVivien Didelot if (err) 361101515c8SVivien Didelot return err; 362101515c8SVivien Didelot 363101515c8SVivien Didelot return 0; 36433641994SAndrew Lunn } 36533641994SAndrew Lunn 36633641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 36733641994SAndrew Lunn { 368101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 369101515c8SVivien Didelot 370101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 37133641994SAndrew Lunn } 37233641994SAndrew Lunn 3736e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3746e55f698SAndrew Lunn { 375101515c8SVivien Didelot u16 ptr; 3766e55f698SAndrew Lunn int err; 3776e55f698SAndrew Lunn 3786e55f698SAndrew Lunn /* 01:c2:80:00:00:00:00-01:c2:80:00:00:00:07 are Management */ 379101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XLO; 380101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3816e55f698SAndrew Lunn if (err) 3826e55f698SAndrew Lunn return err; 3836e55f698SAndrew Lunn 3846e55f698SAndrew Lunn /* 01:c2:80:00:00:00:08-01:c2:80:00:00:00:0f are Management */ 385101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000000XHI; 386101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3876e55f698SAndrew Lunn if (err) 3886e55f698SAndrew Lunn return err; 3896e55f698SAndrew Lunn 3906e55f698SAndrew Lunn /* 01:c2:80:00:00:00:20-01:c2:80:00:00:00:27 are Management */ 391101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XLO; 392101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3936e55f698SAndrew Lunn if (err) 3946e55f698SAndrew Lunn return err; 3956e55f698SAndrew Lunn 3966e55f698SAndrew Lunn /* 01:c2:80:00:00:00:28-01:c2:80:00:00:00:2f are Management */ 397101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C280000002XHI; 398101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 399101515c8SVivien Didelot if (err) 400101515c8SVivien Didelot return err; 401101515c8SVivien Didelot 402101515c8SVivien Didelot return 0; 4036e55f698SAndrew Lunn } 4046e55f698SAndrew Lunn 405de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 406de227387SAndrew Lunn 40702317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 40802317e68SVivien Didelot u16 val) 40902317e68SVivien Didelot { 41002317e68SVivien Didelot u16 reg; 41102317e68SVivien Didelot int err; 41202317e68SVivien Didelot 41302317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 41402317e68SVivien Didelot if (err) 41502317e68SVivien Didelot return err; 41602317e68SVivien Didelot 41702317e68SVivien Didelot reg &= ~mask; 41802317e68SVivien Didelot reg |= val & mask; 41902317e68SVivien Didelot 42002317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 42102317e68SVivien Didelot } 42202317e68SVivien Didelot 42302317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 42402317e68SVivien Didelot { 42502317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 42602317e68SVivien Didelot 42702317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 42802317e68SVivien Didelot } 42902317e68SVivien Didelot 4309e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4319e5baf9bSVivien Didelot { 4329e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4339e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4349e5baf9bSVivien Didelot } 4359e5baf9bSVivien Didelot 4369e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4379e5baf9bSVivien Didelot { 4389e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4399e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4409e5baf9bSVivien Didelot } 4419e5baf9bSVivien Didelot 4429e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4439e5baf9bSVivien Didelot { 4449e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4459e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4469e5baf9bSVivien Didelot } 4479e5baf9bSVivien Didelot 448de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 449de227387SAndrew Lunn { 450408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 451408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 452408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 453de227387SAndrew Lunn } 454de227387SAndrew Lunn 45523c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 45623c98919SVivien Didelot { 45723c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 45823c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 45923c98919SVivien Didelot index); 46023c98919SVivien Didelot } 46123c98919SVivien Didelot 462de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 463de227387SAndrew Lunn 4647f9ef3afSAndrew Lunn int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 465a605a0feSAndrew Lunn { 46657d1ef38SVivien Didelot return mv88e6xxx_g1_wait(chip, MV88E6XXX_G1_STATS_OP, 46757d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY); 468a605a0feSAndrew Lunn } 469a605a0feSAndrew Lunn 47040cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 47140cff8fcSAndrew Lunn { 47240cff8fcSAndrew Lunn u16 val; 47340cff8fcSAndrew Lunn int err; 47440cff8fcSAndrew Lunn 47540cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 47640cff8fcSAndrew Lunn if (err) 47740cff8fcSAndrew Lunn return err; 47840cff8fcSAndrew Lunn 47940cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 48040cff8fcSAndrew Lunn 48140cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 48240cff8fcSAndrew Lunn 48340cff8fcSAndrew Lunn return err; 48440cff8fcSAndrew Lunn } 48540cff8fcSAndrew Lunn 486a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 487a605a0feSAndrew Lunn { 488a605a0feSAndrew Lunn int err; 489a605a0feSAndrew Lunn 490a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 49157d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 49257d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 49357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 49457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 495a605a0feSAndrew Lunn if (err) 496a605a0feSAndrew Lunn return err; 497a605a0feSAndrew Lunn 498a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 499a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 500a605a0feSAndrew Lunn } 501a605a0feSAndrew Lunn 502a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 503a605a0feSAndrew Lunn { 504a605a0feSAndrew Lunn port = (port + 1) << 5; 505a605a0feSAndrew Lunn 506a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 507a605a0feSAndrew Lunn } 50879523473SAndrew Lunn 50979523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 51079523473SAndrew Lunn { 51179523473SAndrew Lunn int err; 51279523473SAndrew Lunn 51379523473SAndrew Lunn port = (port + 1) << 5; 51479523473SAndrew Lunn 51579523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 51657d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 51757d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 51857d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 51979523473SAndrew Lunn if (err) 52079523473SAndrew Lunn return err; 52179523473SAndrew Lunn 52279523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 52379523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 52479523473SAndrew Lunn } 5257f9ef3afSAndrew Lunn 5267f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 5277f9ef3afSAndrew Lunn { 5287f9ef3afSAndrew Lunn u32 value; 5297f9ef3afSAndrew Lunn u16 reg; 5307f9ef3afSAndrew Lunn int err; 5317f9ef3afSAndrew Lunn 5327f9ef3afSAndrew Lunn *val = 0; 5337f9ef3afSAndrew Lunn 53457d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 53557d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 53657d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5377f9ef3afSAndrew Lunn if (err) 5387f9ef3afSAndrew Lunn return; 5397f9ef3afSAndrew Lunn 5407f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5417f9ef3afSAndrew Lunn if (err) 5427f9ef3afSAndrew Lunn return; 5437f9ef3afSAndrew Lunn 54457d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5457f9ef3afSAndrew Lunn if (err) 5467f9ef3afSAndrew Lunn return; 5477f9ef3afSAndrew Lunn 5487f9ef3afSAndrew Lunn value = reg << 16; 5497f9ef3afSAndrew Lunn 55057d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5517f9ef3afSAndrew Lunn if (err) 5527f9ef3afSAndrew Lunn return; 5537f9ef3afSAndrew Lunn 5547f9ef3afSAndrew Lunn *val = value | reg; 5557f9ef3afSAndrew Lunn } 55640cff8fcSAndrew Lunn 55740cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 55840cff8fcSAndrew Lunn { 55940cff8fcSAndrew Lunn int err; 56040cff8fcSAndrew Lunn u16 val; 56140cff8fcSAndrew Lunn 56240cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 56340cff8fcSAndrew Lunn if (err) 56440cff8fcSAndrew Lunn return err; 56540cff8fcSAndrew Lunn 566a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 567a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 56840cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 56940cff8fcSAndrew Lunn 57040cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 57140cff8fcSAndrew Lunn if (err) 57240cff8fcSAndrew Lunn return err; 57340cff8fcSAndrew Lunn 57440cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 57540cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 57640cff8fcSAndrew Lunn } 577