12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11101515c8SVivien Didelot #include <linux/bitfield.h> 12101515c8SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14a935c052SVivien Didelot #include "global1.h" 15a935c052SVivien Didelot 16a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17a935c052SVivien Didelot { 18a935c052SVivien Didelot int addr = chip->info->global1_addr; 19a935c052SVivien Didelot 20a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 21a935c052SVivien Didelot } 22a935c052SVivien Didelot 23a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24a935c052SVivien Didelot { 25a935c052SVivien Didelot int addr = chip->info->global1_addr; 26a935c052SVivien Didelot 27a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 28a935c052SVivien Didelot } 29a935c052SVivien Didelot 3019fb7f69SVivien Didelot int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 3119fb7f69SVivien Didelot bit, int val) 3219fb7f69SVivien Didelot { 3319fb7f69SVivien Didelot return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 3419fb7f69SVivien Didelot bit, val); 3519fb7f69SVivien Didelot } 3619fb7f69SVivien Didelot 37683f2244SVivien Didelot int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 38683f2244SVivien Didelot u16 mask, u16 val) 39683f2244SVivien Didelot { 40683f2244SVivien Didelot return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 41683f2244SVivien Didelot mask, val); 42683f2244SVivien Didelot } 43683f2244SVivien Didelot 4417e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 4517e708baSVivien Didelot 46a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 47a199d8b6SVivien Didelot { 48683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 49683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 50683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_DISABLED); 51a199d8b6SVivien Didelot } 52a199d8b6SVivien Didelot 5317e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 5417e708baSVivien Didelot { 55683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 56683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 57683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_POLLING); 5817e708baSVivien Didelot } 5917e708baSVivien Didelot 6017e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 6117e708baSVivien Didelot { 6219fb7f69SVivien Didelot int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 6317e708baSVivien Didelot 6419fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 6517e708baSVivien Didelot } 6617e708baSVivien Didelot 6717e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 6817e708baSVivien Didelot { 6919fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 7017e708baSVivien Didelot 7117e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 7217e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 7317e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 7417e708baSVivien Didelot */ 7519fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 7617e708baSVivien Didelot } 7717e708baSVivien Didelot 784b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 794b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 804b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 814b0c4817SVivien Didelot */ 824b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 834b0c4817SVivien Didelot { 844b0c4817SVivien Didelot u16 reg; 854b0c4817SVivien Didelot int err; 864b0c4817SVivien Didelot 874b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 884b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 894b0c4817SVivien Didelot if (err) 904b0c4817SVivien Didelot return err; 914b0c4817SVivien Didelot 924b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 934b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 944b0c4817SVivien Didelot if (err) 954b0c4817SVivien Didelot return err; 964b0c4817SVivien Didelot 974b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 984b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 994b0c4817SVivien Didelot if (err) 1004b0c4817SVivien Didelot return err; 1014b0c4817SVivien Didelot 1024b0c4817SVivien Didelot return 0; 1034b0c4817SVivien Didelot } 1044b0c4817SVivien Didelot 10517e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 10617e708baSVivien Didelot 10717e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 10817e708baSVivien Didelot { 10917e708baSVivien Didelot u16 val; 11017e708baSVivien Didelot int err; 11117e708baSVivien Didelot 11217e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 11317e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 11417e708baSVivien Didelot */ 115d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 11617e708baSVivien Didelot if (err) 11717e708baSVivien Didelot return err; 11817e708baSVivien Didelot 119d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 120d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 12117e708baSVivien Didelot 122d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 12317e708baSVivien Didelot if (err) 12417e708baSVivien Didelot return err; 12517e708baSVivien Didelot 12617e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 12717e708baSVivien Didelot if (err) 12817e708baSVivien Didelot return err; 12917e708baSVivien Didelot 13017e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 13117e708baSVivien Didelot } 13217e708baSVivien Didelot 1331f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 1341f71836fSRasmus Villemoes { 1351f71836fSRasmus Villemoes u16 val; 1361f71836fSRasmus Villemoes int err; 1371f71836fSRasmus Villemoes 1381f71836fSRasmus Villemoes /* Set the SWReset bit 15 */ 1391f71836fSRasmus Villemoes err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 1401f71836fSRasmus Villemoes if (err) 1411f71836fSRasmus Villemoes return err; 1421f71836fSRasmus Villemoes 1431f71836fSRasmus Villemoes val |= MV88E6XXX_G1_CTL1_SW_RESET; 1441f71836fSRasmus Villemoes 1451f71836fSRasmus Villemoes err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 1461f71836fSRasmus Villemoes if (err) 1471f71836fSRasmus Villemoes return err; 1481f71836fSRasmus Villemoes 1491f71836fSRasmus Villemoes return mv88e6xxx_g1_wait_init_ready(chip); 1501f71836fSRasmus Villemoes } 1511f71836fSRasmus Villemoes 15217e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 15317e708baSVivien Didelot { 15417e708baSVivien Didelot int err; 15517e708baSVivien Didelot 1567358fd80SRasmus Villemoes err = mv88e6250_g1_reset(chip); 15717e708baSVivien Didelot if (err) 15817e708baSVivien Didelot return err; 15917e708baSVivien Didelot 16017e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 16117e708baSVivien Didelot } 16217e708baSVivien Didelot 163a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 164a199d8b6SVivien Didelot { 165a199d8b6SVivien Didelot u16 val; 166a199d8b6SVivien Didelot int err; 167a199d8b6SVivien Didelot 168d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 169a199d8b6SVivien Didelot if (err) 170a199d8b6SVivien Didelot return err; 171a199d8b6SVivien Didelot 172d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 173a199d8b6SVivien Didelot 174d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 175a199d8b6SVivien Didelot if (err) 176a199d8b6SVivien Didelot return err; 177a199d8b6SVivien Didelot 178a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 179a199d8b6SVivien Didelot } 180a199d8b6SVivien Didelot 181a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 182a199d8b6SVivien Didelot { 183a199d8b6SVivien Didelot u16 val; 184a199d8b6SVivien Didelot int err; 185a199d8b6SVivien Didelot 186d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 187a199d8b6SVivien Didelot if (err) 188a199d8b6SVivien Didelot return err; 189a199d8b6SVivien Didelot 190d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 191a199d8b6SVivien Didelot 192d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 193a199d8b6SVivien Didelot if (err) 194a199d8b6SVivien Didelot return err; 195a199d8b6SVivien Didelot 196a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 197a199d8b6SVivien Didelot } 198a199d8b6SVivien Didelot 1991baf0facSChris Packham int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu) 2001baf0facSChris Packham { 2011baf0facSChris Packham u16 val; 2021baf0facSChris Packham int err; 2031baf0facSChris Packham 2041baf0facSChris Packham err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 2051baf0facSChris Packham if (err) 2061baf0facSChris Packham return err; 2071baf0facSChris Packham 2081baf0facSChris Packham val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632; 2091baf0facSChris Packham 2101baf0facSChris Packham if (mtu > 1518) 2111baf0facSChris Packham val |= MV88E6185_G1_CTL1_MAX_FRAME_1632; 2121baf0facSChris Packham 2131baf0facSChris Packham return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 2141baf0facSChris Packham } 2151baf0facSChris Packham 21693e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 21793e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 21893e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 21993e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 22093e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 22193e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 22293e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 22393e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 22493e18d61SVivien Didelot */ 22593e18d61SVivien Didelot 22693e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 22793e18d61SVivien Didelot { 22893e18d61SVivien Didelot int err; 22993e18d61SVivien Didelot 23093e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 23193e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 23293e18d61SVivien Didelot if (err) 23393e18d61SVivien Didelot return err; 23493e18d61SVivien Didelot 23593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 23693e18d61SVivien Didelot if (err) 23793e18d61SVivien Didelot return err; 23893e18d61SVivien Didelot 23993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 24093e18d61SVivien Didelot if (err) 24193e18d61SVivien Didelot return err; 24293e18d61SVivien Didelot 24393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 24493e18d61SVivien Didelot if (err) 24593e18d61SVivien Didelot return err; 24693e18d61SVivien Didelot 24793e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 24893e18d61SVivien Didelot if (err) 24993e18d61SVivien Didelot return err; 25093e18d61SVivien Didelot 25193e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 25293e18d61SVivien Didelot if (err) 25393e18d61SVivien Didelot return err; 25493e18d61SVivien Didelot 25593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 25693e18d61SVivien Didelot if (err) 25793e18d61SVivien Didelot return err; 25893e18d61SVivien Didelot 25993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 26093e18d61SVivien Didelot if (err) 26193e18d61SVivien Didelot return err; 26293e18d61SVivien Didelot 26393e18d61SVivien Didelot return 0; 26493e18d61SVivien Didelot } 26593e18d61SVivien Didelot 26693e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 26793e18d61SVivien Didelot 26893e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 26993e18d61SVivien Didelot { 27093e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 27193e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 27293e18d61SVivien Didelot } 27393e18d61SVivien Didelot 274df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 275df63b0d9SRasmus Villemoes { 276df63b0d9SRasmus Villemoes /* Reset the IEEE Tag priorities to defaults */ 277df63b0d9SRasmus Villemoes return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 278df63b0d9SRasmus Villemoes } 279df63b0d9SRasmus Villemoes 28033641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 28133641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 28233641994SAndrew Lunn 2835c74c54cSIwan R Timmer int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 2845c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 2855c74c54cSIwan R Timmer int port) 28633641994SAndrew Lunn { 287f0942e00SIwan R Timmer int *dest_port_chip; 28833641994SAndrew Lunn u16 reg; 28933641994SAndrew Lunn int err; 29033641994SAndrew Lunn 291101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 29233641994SAndrew Lunn if (err) 29333641994SAndrew Lunn return err; 29433641994SAndrew Lunn 2955c74c54cSIwan R Timmer switch (direction) { 2965c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_INGRESS: 297f0942e00SIwan R Timmer dest_port_chip = &chip->ingress_dest_port; 2983ee339ebSAndrew Lunn reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK; 2995c74c54cSIwan R Timmer reg |= port << 3005c74c54cSIwan R Timmer __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK); 3015c74c54cSIwan R Timmer break; 3025c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_EGRESS: 303f0942e00SIwan R Timmer dest_port_chip = &chip->egress_dest_port; 3043ee339ebSAndrew Lunn reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK; 3055c74c54cSIwan R Timmer reg |= port << 3065c74c54cSIwan R Timmer __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 3075c74c54cSIwan R Timmer break; 3085c74c54cSIwan R Timmer default: 3095c74c54cSIwan R Timmer return -EINVAL; 3105c74c54cSIwan R Timmer } 31133641994SAndrew Lunn 312f0942e00SIwan R Timmer err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 313f0942e00SIwan R Timmer if (!err) 314f0942e00SIwan R Timmer *dest_port_chip = port; 315f0942e00SIwan R Timmer 316f0942e00SIwan R Timmer return err; 31733641994SAndrew Lunn } 31833641994SAndrew Lunn 31933641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 32033641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 32133641994SAndrew Lunn * egress it 32233641994SAndrew Lunn */ 32333641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 32433641994SAndrew Lunn { 32533641994SAndrew Lunn u16 reg; 32633641994SAndrew Lunn int err; 32733641994SAndrew Lunn 328101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 32933641994SAndrew Lunn if (err) 33033641994SAndrew Lunn return err; 33133641994SAndrew Lunn 332101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 333101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 33433641994SAndrew Lunn 335101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 33633641994SAndrew Lunn } 33733641994SAndrew Lunn 33833641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 33933641994SAndrew Lunn u16 pointer, u8 data) 34033641994SAndrew Lunn { 34133641994SAndrew Lunn u16 reg; 34233641994SAndrew Lunn 343101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 34433641994SAndrew Lunn 345101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 34633641994SAndrew Lunn } 34733641994SAndrew Lunn 3485c74c54cSIwan R Timmer int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 3495c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 3505c74c54cSIwan R Timmer int port) 35133641994SAndrew Lunn { 352f0942e00SIwan R Timmer int *dest_port_chip; 353101515c8SVivien Didelot u16 ptr; 35433641994SAndrew Lunn int err; 35533641994SAndrew Lunn 3565c74c54cSIwan R Timmer switch (direction) { 3575c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_INGRESS: 358f0942e00SIwan R Timmer dest_port_chip = &chip->ingress_dest_port; 359101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 3605c74c54cSIwan R Timmer break; 3615c74c54cSIwan R Timmer case MV88E6XXX_EGRESS_DIR_EGRESS: 362f0942e00SIwan R Timmer dest_port_chip = &chip->egress_dest_port; 363101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 3645c74c54cSIwan R Timmer break; 3655c74c54cSIwan R Timmer default: 3665c74c54cSIwan R Timmer return -EINVAL; 3675c74c54cSIwan R Timmer } 3685c74c54cSIwan R Timmer 369101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 370f0942e00SIwan R Timmer if (!err) 371f0942e00SIwan R Timmer *dest_port_chip = port; 372101515c8SVivien Didelot 373f0942e00SIwan R Timmer return err; 37433641994SAndrew Lunn } 37533641994SAndrew Lunn 37633641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 37733641994SAndrew Lunn { 378101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 379101515c8SVivien Didelot 380d8dc2c96SAndrew Lunn /* Use the default high priority for management frames sent to 381d8dc2c96SAndrew Lunn * the CPU. 382d8dc2c96SAndrew Lunn */ 383d8dc2c96SAndrew Lunn port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI; 384d8dc2c96SAndrew Lunn 385101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 38633641994SAndrew Lunn } 38733641994SAndrew Lunn 3886e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3896e55f698SAndrew Lunn { 390101515c8SVivien Didelot u16 ptr; 3916e55f698SAndrew Lunn int err; 3926e55f698SAndrew Lunn 393989f405aSRasmus Villemoes /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 394989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 395101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3966e55f698SAndrew Lunn if (err) 3976e55f698SAndrew Lunn return err; 3986e55f698SAndrew Lunn 399989f405aSRasmus Villemoes /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 400989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 401101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 4026e55f698SAndrew Lunn if (err) 4036e55f698SAndrew Lunn return err; 4046e55f698SAndrew Lunn 405989f405aSRasmus Villemoes /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 406989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 407101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 4086e55f698SAndrew Lunn if (err) 4096e55f698SAndrew Lunn return err; 4106e55f698SAndrew Lunn 411989f405aSRasmus Villemoes /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 412989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 413101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 414101515c8SVivien Didelot if (err) 415101515c8SVivien Didelot return err; 416101515c8SVivien Didelot 417101515c8SVivien Didelot return 0; 4186e55f698SAndrew Lunn } 4196e55f698SAndrew Lunn 420de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 421de227387SAndrew Lunn 42202317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 42302317e68SVivien Didelot u16 val) 42402317e68SVivien Didelot { 42502317e68SVivien Didelot u16 reg; 42602317e68SVivien Didelot int err; 42702317e68SVivien Didelot 42802317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 42902317e68SVivien Didelot if (err) 43002317e68SVivien Didelot return err; 43102317e68SVivien Didelot 43202317e68SVivien Didelot reg &= ~mask; 43302317e68SVivien Didelot reg |= val & mask; 43402317e68SVivien Didelot 43502317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 43602317e68SVivien Didelot } 43702317e68SVivien Didelot 43802317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 43902317e68SVivien Didelot { 44002317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 44102317e68SVivien Didelot 44202317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 44302317e68SVivien Didelot } 44402317e68SVivien Didelot 4459e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4469e5baf9bSVivien Didelot { 4479e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4489e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4499e5baf9bSVivien Didelot } 4509e5baf9bSVivien Didelot 4519e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4529e5baf9bSVivien Didelot { 4539e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4549e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4559e5baf9bSVivien Didelot } 4569e5baf9bSVivien Didelot 4579e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4589e5baf9bSVivien Didelot { 4599e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4609e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4619e5baf9bSVivien Didelot } 4629e5baf9bSVivien Didelot 463de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 464de227387SAndrew Lunn { 465408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 466408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 467408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 468de227387SAndrew Lunn } 469de227387SAndrew Lunn 47023c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 47123c98919SVivien Didelot { 47223c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 47323c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 47423c98919SVivien Didelot index); 47523c98919SVivien Didelot } 47623c98919SVivien Didelot 477de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 478de227387SAndrew Lunn 479cfd10888SRasmus Villemoes static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 480a605a0feSAndrew Lunn { 48119fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 48219fb7f69SVivien Didelot 48319fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 484a605a0feSAndrew Lunn } 485a605a0feSAndrew Lunn 48640cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 48740cff8fcSAndrew Lunn { 48840cff8fcSAndrew Lunn u16 val; 48940cff8fcSAndrew Lunn int err; 49040cff8fcSAndrew Lunn 49140cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 49240cff8fcSAndrew Lunn if (err) 49340cff8fcSAndrew Lunn return err; 49440cff8fcSAndrew Lunn 49540cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 49640cff8fcSAndrew Lunn 49740cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 49840cff8fcSAndrew Lunn 49940cff8fcSAndrew Lunn return err; 50040cff8fcSAndrew Lunn } 50140cff8fcSAndrew Lunn 502a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 503a605a0feSAndrew Lunn { 504a605a0feSAndrew Lunn int err; 505a605a0feSAndrew Lunn 506a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 50757d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 50857d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 50957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 51057d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 511a605a0feSAndrew Lunn if (err) 512a605a0feSAndrew Lunn return err; 513a605a0feSAndrew Lunn 514a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 515a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 516a605a0feSAndrew Lunn } 517a605a0feSAndrew Lunn 518a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 519a605a0feSAndrew Lunn { 520a605a0feSAndrew Lunn port = (port + 1) << 5; 521a605a0feSAndrew Lunn 522a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 523a605a0feSAndrew Lunn } 52479523473SAndrew Lunn 52579523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 52679523473SAndrew Lunn { 52779523473SAndrew Lunn int err; 52879523473SAndrew Lunn 52979523473SAndrew Lunn port = (port + 1) << 5; 53079523473SAndrew Lunn 53179523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 53257d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 53357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 53457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 53579523473SAndrew Lunn if (err) 53679523473SAndrew Lunn return err; 53779523473SAndrew Lunn 53879523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 53979523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 54079523473SAndrew Lunn } 5417f9ef3afSAndrew Lunn 5427f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 5437f9ef3afSAndrew Lunn { 5447f9ef3afSAndrew Lunn u32 value; 5457f9ef3afSAndrew Lunn u16 reg; 5467f9ef3afSAndrew Lunn int err; 5477f9ef3afSAndrew Lunn 5487f9ef3afSAndrew Lunn *val = 0; 5497f9ef3afSAndrew Lunn 55057d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 55157d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 55257d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5537f9ef3afSAndrew Lunn if (err) 5547f9ef3afSAndrew Lunn return; 5557f9ef3afSAndrew Lunn 5567f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5577f9ef3afSAndrew Lunn if (err) 5587f9ef3afSAndrew Lunn return; 5597f9ef3afSAndrew Lunn 56057d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5617f9ef3afSAndrew Lunn if (err) 5627f9ef3afSAndrew Lunn return; 5637f9ef3afSAndrew Lunn 5647f9ef3afSAndrew Lunn value = reg << 16; 5657f9ef3afSAndrew Lunn 56657d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5677f9ef3afSAndrew Lunn if (err) 5687f9ef3afSAndrew Lunn return; 5697f9ef3afSAndrew Lunn 5707f9ef3afSAndrew Lunn *val = value | reg; 5717f9ef3afSAndrew Lunn } 57240cff8fcSAndrew Lunn 57340cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 57440cff8fcSAndrew Lunn { 57540cff8fcSAndrew Lunn int err; 57640cff8fcSAndrew Lunn u16 val; 57740cff8fcSAndrew Lunn 57840cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 57940cff8fcSAndrew Lunn if (err) 58040cff8fcSAndrew Lunn return err; 58140cff8fcSAndrew Lunn 582a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 583a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 58440cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 58540cff8fcSAndrew Lunn 58640cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 58740cff8fcSAndrew Lunn if (err) 58840cff8fcSAndrew Lunn return err; 58940cff8fcSAndrew Lunn 59040cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 59140cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 59240cff8fcSAndrew Lunn } 593