12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11101515c8SVivien Didelot #include <linux/bitfield.h> 12101515c8SVivien Didelot 134d5f2ba7SVivien Didelot #include "chip.h" 14a935c052SVivien Didelot #include "global1.h" 15a935c052SVivien Didelot 16a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 17a935c052SVivien Didelot { 18a935c052SVivien Didelot int addr = chip->info->global1_addr; 19a935c052SVivien Didelot 20a935c052SVivien Didelot return mv88e6xxx_read(chip, addr, reg, val); 21a935c052SVivien Didelot } 22a935c052SVivien Didelot 23a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 24a935c052SVivien Didelot { 25a935c052SVivien Didelot int addr = chip->info->global1_addr; 26a935c052SVivien Didelot 27a935c052SVivien Didelot return mv88e6xxx_write(chip, addr, reg, val); 28a935c052SVivien Didelot } 29a935c052SVivien Didelot 30a935c052SVivien Didelot int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask) 31a935c052SVivien Didelot { 32a935c052SVivien Didelot return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask); 33a935c052SVivien Didelot } 34a605a0feSAndrew Lunn 3519fb7f69SVivien Didelot int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 3619fb7f69SVivien Didelot bit, int val) 3719fb7f69SVivien Didelot { 3819fb7f69SVivien Didelot return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg, 3919fb7f69SVivien Didelot bit, val); 4019fb7f69SVivien Didelot } 4119fb7f69SVivien Didelot 42683f2244SVivien Didelot int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 43683f2244SVivien Didelot u16 mask, u16 val) 44683f2244SVivien Didelot { 45683f2244SVivien Didelot return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg, 46683f2244SVivien Didelot mask, val); 47683f2244SVivien Didelot } 48683f2244SVivien Didelot 4917e708baSVivien Didelot /* Offset 0x00: Switch Global Status Register */ 5017e708baSVivien Didelot 51a199d8b6SVivien Didelot static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip) 52a199d8b6SVivien Didelot { 53683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 54683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 55683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_DISABLED); 56a199d8b6SVivien Didelot } 57a199d8b6SVivien Didelot 5817e708baSVivien Didelot static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 5917e708baSVivien Didelot { 60683f2244SVivien Didelot return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS, 61683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_MASK, 62683f2244SVivien Didelot MV88E6185_G1_STS_PPU_STATE_POLLING); 6317e708baSVivien Didelot } 6417e708baSVivien Didelot 6517e708baSVivien Didelot static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip) 6617e708baSVivien Didelot { 6719fb7f69SVivien Didelot int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE); 6817e708baSVivien Didelot 6919fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 7017e708baSVivien Didelot } 7117e708baSVivien Didelot 7217e708baSVivien Didelot static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip) 7317e708baSVivien Didelot { 7419fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY); 7517e708baSVivien Didelot 7617e708baSVivien Didelot /* Wait up to 1 second for the switch to be ready. The InitReady bit 11 7717e708baSVivien Didelot * is set to a one when all units inside the device (ATU, VTU, etc.) 7817e708baSVivien Didelot * have finished their initialization and are ready to accept frames. 7917e708baSVivien Didelot */ 8019fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1); 8117e708baSVivien Didelot } 8217e708baSVivien Didelot 834b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 844b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 854b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 864b0c4817SVivien Didelot */ 874b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 884b0c4817SVivien Didelot { 894b0c4817SVivien Didelot u16 reg; 904b0c4817SVivien Didelot int err; 914b0c4817SVivien Didelot 924b0c4817SVivien Didelot reg = (addr[0] << 8) | addr[1]; 934b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg); 944b0c4817SVivien Didelot if (err) 954b0c4817SVivien Didelot return err; 964b0c4817SVivien Didelot 974b0c4817SVivien Didelot reg = (addr[2] << 8) | addr[3]; 984b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg); 994b0c4817SVivien Didelot if (err) 1004b0c4817SVivien Didelot return err; 1014b0c4817SVivien Didelot 1024b0c4817SVivien Didelot reg = (addr[4] << 8) | addr[5]; 1034b0c4817SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg); 1044b0c4817SVivien Didelot if (err) 1054b0c4817SVivien Didelot return err; 1064b0c4817SVivien Didelot 1074b0c4817SVivien Didelot return 0; 1084b0c4817SVivien Didelot } 1094b0c4817SVivien Didelot 11017e708baSVivien Didelot /* Offset 0x04: Switch Global Control Register */ 11117e708baSVivien Didelot 11217e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip) 11317e708baSVivien Didelot { 11417e708baSVivien Didelot u16 val; 11517e708baSVivien Didelot int err; 11617e708baSVivien Didelot 11717e708baSVivien Didelot /* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart 11817e708baSVivien Didelot * the PPU, including re-doing PHY detection and initialization 11917e708baSVivien Didelot */ 120d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 12117e708baSVivien Didelot if (err) 12217e708baSVivien Didelot return err; 12317e708baSVivien Didelot 124d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_SW_RESET; 125d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 12617e708baSVivien Didelot 127d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 12817e708baSVivien Didelot if (err) 12917e708baSVivien Didelot return err; 13017e708baSVivien Didelot 13117e708baSVivien Didelot err = mv88e6xxx_g1_wait_init_ready(chip); 13217e708baSVivien Didelot if (err) 13317e708baSVivien Didelot return err; 13417e708baSVivien Didelot 13517e708baSVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 13617e708baSVivien Didelot } 13717e708baSVivien Didelot 1381f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip) 1391f71836fSRasmus Villemoes { 1401f71836fSRasmus Villemoes u16 val; 1411f71836fSRasmus Villemoes int err; 1421f71836fSRasmus Villemoes 1431f71836fSRasmus Villemoes /* Set the SWReset bit 15 */ 1441f71836fSRasmus Villemoes err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 1451f71836fSRasmus Villemoes if (err) 1461f71836fSRasmus Villemoes return err; 1471f71836fSRasmus Villemoes 1481f71836fSRasmus Villemoes val |= MV88E6XXX_G1_CTL1_SW_RESET; 1491f71836fSRasmus Villemoes 1501f71836fSRasmus Villemoes err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 1511f71836fSRasmus Villemoes if (err) 1521f71836fSRasmus Villemoes return err; 1531f71836fSRasmus Villemoes 1541f71836fSRasmus Villemoes return mv88e6xxx_g1_wait_init_ready(chip); 1551f71836fSRasmus Villemoes } 1561f71836fSRasmus Villemoes 15717e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip) 15817e708baSVivien Didelot { 15917e708baSVivien Didelot int err; 16017e708baSVivien Didelot 1617358fd80SRasmus Villemoes err = mv88e6250_g1_reset(chip); 16217e708baSVivien Didelot if (err) 16317e708baSVivien Didelot return err; 16417e708baSVivien Didelot 16517e708baSVivien Didelot return mv88e6352_g1_wait_ppu_polling(chip); 16617e708baSVivien Didelot } 16717e708baSVivien Didelot 168a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip) 169a199d8b6SVivien Didelot { 170a199d8b6SVivien Didelot u16 val; 171a199d8b6SVivien Didelot int err; 172a199d8b6SVivien Didelot 173d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 174a199d8b6SVivien Didelot if (err) 175a199d8b6SVivien Didelot return err; 176a199d8b6SVivien Didelot 177d77f4321SVivien Didelot val |= MV88E6XXX_G1_CTL1_PPU_ENABLE; 178a199d8b6SVivien Didelot 179d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 180a199d8b6SVivien Didelot if (err) 181a199d8b6SVivien Didelot return err; 182a199d8b6SVivien Didelot 183a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_polling(chip); 184a199d8b6SVivien Didelot } 185a199d8b6SVivien Didelot 186a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip) 187a199d8b6SVivien Didelot { 188a199d8b6SVivien Didelot u16 val; 189a199d8b6SVivien Didelot int err; 190a199d8b6SVivien Didelot 191d77f4321SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val); 192a199d8b6SVivien Didelot if (err) 193a199d8b6SVivien Didelot return err; 194a199d8b6SVivien Didelot 195d77f4321SVivien Didelot val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE; 196a199d8b6SVivien Didelot 197d77f4321SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val); 198a199d8b6SVivien Didelot if (err) 199a199d8b6SVivien Didelot return err; 200a199d8b6SVivien Didelot 201a199d8b6SVivien Didelot return mv88e6185_g1_wait_ppu_disabled(chip); 202a199d8b6SVivien Didelot } 203a199d8b6SVivien Didelot 20493e18d61SVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 20593e18d61SVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 20693e18d61SVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 20793e18d61SVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 20893e18d61SVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 20993e18d61SVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 21093e18d61SVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 21193e18d61SVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 21293e18d61SVivien Didelot */ 21393e18d61SVivien Didelot 21493e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip) 21593e18d61SVivien Didelot { 21693e18d61SVivien Didelot int err; 21793e18d61SVivien Didelot 21893e18d61SVivien Didelot /* Reset the IP TOS/DiffServ/Traffic priorities to defaults */ 21993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 22093e18d61SVivien Didelot if (err) 22193e18d61SVivien Didelot return err; 22293e18d61SVivien Didelot 22393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 22493e18d61SVivien Didelot if (err) 22593e18d61SVivien Didelot return err; 22693e18d61SVivien Didelot 22793e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 22893e18d61SVivien Didelot if (err) 22993e18d61SVivien Didelot return err; 23093e18d61SVivien Didelot 23193e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 23293e18d61SVivien Didelot if (err) 23393e18d61SVivien Didelot return err; 23493e18d61SVivien Didelot 23593e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 23693e18d61SVivien Didelot if (err) 23793e18d61SVivien Didelot return err; 23893e18d61SVivien Didelot 23993e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 24093e18d61SVivien Didelot if (err) 24193e18d61SVivien Didelot return err; 24293e18d61SVivien Didelot 24393e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 24493e18d61SVivien Didelot if (err) 24593e18d61SVivien Didelot return err; 24693e18d61SVivien Didelot 24793e18d61SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 24893e18d61SVivien Didelot if (err) 24993e18d61SVivien Didelot return err; 25093e18d61SVivien Didelot 25193e18d61SVivien Didelot return 0; 25293e18d61SVivien Didelot } 25393e18d61SVivien Didelot 25493e18d61SVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 25593e18d61SVivien Didelot 25693e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 25793e18d61SVivien Didelot { 25893e18d61SVivien Didelot /* Reset the IEEE Tag priorities to defaults */ 25993e18d61SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 26093e18d61SVivien Didelot } 26193e18d61SVivien Didelot 262df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip) 263df63b0d9SRasmus Villemoes { 264df63b0d9SRasmus Villemoes /* Reset the IEEE Tag priorities to defaults */ 265df63b0d9SRasmus Villemoes return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50); 266df63b0d9SRasmus Villemoes } 267df63b0d9SRasmus Villemoes 26833641994SAndrew Lunn /* Offset 0x1a: Monitor Control */ 26933641994SAndrew Lunn /* Offset 0x1a: Monitor & MGMT Control on some devices */ 27033641994SAndrew Lunn 27133641994SAndrew Lunn int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 27233641994SAndrew Lunn { 27333641994SAndrew Lunn u16 reg; 27433641994SAndrew Lunn int err; 27533641994SAndrew Lunn 276101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 27733641994SAndrew Lunn if (err) 27833641994SAndrew Lunn return err; 27933641994SAndrew Lunn 280101515c8SVivien Didelot reg &= ~(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK | 281101515c8SVivien Didelot MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 28233641994SAndrew Lunn 283101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK) | 284101515c8SVivien Didelot port << __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK); 28533641994SAndrew Lunn 286101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 28733641994SAndrew Lunn } 28833641994SAndrew Lunn 28933641994SAndrew Lunn /* Older generations also call this the ARP destination. It has been 29033641994SAndrew Lunn * generalized in more modern devices such that more than ARP can 29133641994SAndrew Lunn * egress it 29233641994SAndrew Lunn */ 29333641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 29433641994SAndrew Lunn { 29533641994SAndrew Lunn u16 reg; 29633641994SAndrew Lunn int err; 29733641994SAndrew Lunn 298101515c8SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, ®); 29933641994SAndrew Lunn if (err) 30033641994SAndrew Lunn return err; 30133641994SAndrew Lunn 302101515c8SVivien Didelot reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK; 303101515c8SVivien Didelot reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK); 30433641994SAndrew Lunn 305101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg); 30633641994SAndrew Lunn } 30733641994SAndrew Lunn 30833641994SAndrew Lunn static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip, 30933641994SAndrew Lunn u16 pointer, u8 data) 31033641994SAndrew Lunn { 31133641994SAndrew Lunn u16 reg; 31233641994SAndrew Lunn 313101515c8SVivien Didelot reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data; 31433641994SAndrew Lunn 315101515c8SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg); 31633641994SAndrew Lunn } 31733641994SAndrew Lunn 31833641994SAndrew Lunn int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, int port) 31933641994SAndrew Lunn { 320101515c8SVivien Didelot u16 ptr; 32133641994SAndrew Lunn int err; 32233641994SAndrew Lunn 323101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST; 324101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 32533641994SAndrew Lunn if (err) 32633641994SAndrew Lunn return err; 32733641994SAndrew Lunn 328101515c8SVivien Didelot ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST; 329101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, port); 330101515c8SVivien Didelot if (err) 331101515c8SVivien Didelot return err; 332101515c8SVivien Didelot 333101515c8SVivien Didelot return 0; 33433641994SAndrew Lunn } 33533641994SAndrew Lunn 33633641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port) 33733641994SAndrew Lunn { 338101515c8SVivien Didelot u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST; 339101515c8SVivien Didelot 340101515c8SVivien Didelot return mv88e6390_g1_monitor_write(chip, ptr, port); 34133641994SAndrew Lunn } 34233641994SAndrew Lunn 3436e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip) 3446e55f698SAndrew Lunn { 345101515c8SVivien Didelot u16 ptr; 3466e55f698SAndrew Lunn int err; 3476e55f698SAndrew Lunn 348989f405aSRasmus Villemoes /* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */ 349989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO; 350101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3516e55f698SAndrew Lunn if (err) 3526e55f698SAndrew Lunn return err; 3536e55f698SAndrew Lunn 354989f405aSRasmus Villemoes /* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */ 355989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI; 356101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3576e55f698SAndrew Lunn if (err) 3586e55f698SAndrew Lunn return err; 3596e55f698SAndrew Lunn 360989f405aSRasmus Villemoes /* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */ 361989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO; 362101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 3636e55f698SAndrew Lunn if (err) 3646e55f698SAndrew Lunn return err; 3656e55f698SAndrew Lunn 366989f405aSRasmus Villemoes /* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */ 367989f405aSRasmus Villemoes ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI; 368101515c8SVivien Didelot err = mv88e6390_g1_monitor_write(chip, ptr, 0xff); 369101515c8SVivien Didelot if (err) 370101515c8SVivien Didelot return err; 371101515c8SVivien Didelot 372101515c8SVivien Didelot return 0; 3736e55f698SAndrew Lunn } 3746e55f698SAndrew Lunn 375de227387SAndrew Lunn /* Offset 0x1c: Global Control 2 */ 376de227387SAndrew Lunn 37702317e68SVivien Didelot static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask, 37802317e68SVivien Didelot u16 val) 37902317e68SVivien Didelot { 38002317e68SVivien Didelot u16 reg; 38102317e68SVivien Didelot int err; 38202317e68SVivien Didelot 38302317e68SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, ®); 38402317e68SVivien Didelot if (err) 38502317e68SVivien Didelot return err; 38602317e68SVivien Didelot 38702317e68SVivien Didelot reg &= ~mask; 38802317e68SVivien Didelot reg |= val & mask; 38902317e68SVivien Didelot 39002317e68SVivien Didelot return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg); 39102317e68SVivien Didelot } 39202317e68SVivien Didelot 39302317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port) 39402317e68SVivien Didelot { 39502317e68SVivien Didelot const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK; 39602317e68SVivien Didelot 39702317e68SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask)); 39802317e68SVivien Didelot } 39902317e68SVivien Didelot 4009e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4019e5baf9bSVivien Didelot { 4029e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM | 4039e5baf9bSVivien Didelot MV88E6085_G1_CTL2_RM_ENABLE, 0); 4049e5baf9bSVivien Didelot } 4059e5baf9bSVivien Didelot 4069e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4079e5baf9bSVivien Didelot { 4089e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK, 4099e5baf9bSVivien Didelot MV88E6352_G1_CTL2_RMU_MODE_DISABLED); 4109e5baf9bSVivien Didelot } 4119e5baf9bSVivien Didelot 4129e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip) 4139e5baf9bSVivien Didelot { 4149e5baf9bSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK, 4159e5baf9bSVivien Didelot MV88E6390_G1_CTL2_RMU_MODE_DISABLED); 4169e5baf9bSVivien Didelot } 4179e5baf9bSVivien Didelot 418de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 419de227387SAndrew Lunn { 420408d2debSVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK, 421408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_RX | 422408d2debSVivien Didelot MV88E6390_G1_CTL2_HIST_MODE_TX); 423de227387SAndrew Lunn } 424de227387SAndrew Lunn 42523c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index) 42623c98919SVivien Didelot { 42723c98919SVivien Didelot return mv88e6xxx_g1_ctl2_mask(chip, 42823c98919SVivien Didelot MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK, 42923c98919SVivien Didelot index); 43023c98919SVivien Didelot } 43123c98919SVivien Didelot 432de227387SAndrew Lunn /* Offset 0x1d: Statistics Operation 2 */ 433de227387SAndrew Lunn 434cfd10888SRasmus Villemoes static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip) 435a605a0feSAndrew Lunn { 43619fb7f69SVivien Didelot int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY); 43719fb7f69SVivien Didelot 43819fb7f69SVivien Didelot return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0); 439a605a0feSAndrew Lunn } 440a605a0feSAndrew Lunn 44140cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip) 44240cff8fcSAndrew Lunn { 44340cff8fcSAndrew Lunn u16 val; 44440cff8fcSAndrew Lunn int err; 44540cff8fcSAndrew Lunn 44640cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 44740cff8fcSAndrew Lunn if (err) 44840cff8fcSAndrew Lunn return err; 44940cff8fcSAndrew Lunn 45040cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 45140cff8fcSAndrew Lunn 45240cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 45340cff8fcSAndrew Lunn 45440cff8fcSAndrew Lunn return err; 45540cff8fcSAndrew Lunn } 45640cff8fcSAndrew Lunn 457a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 458a605a0feSAndrew Lunn { 459a605a0feSAndrew Lunn int err; 460a605a0feSAndrew Lunn 461a605a0feSAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 46257d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 46357d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 46457d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | 46557d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port); 466a605a0feSAndrew Lunn if (err) 467a605a0feSAndrew Lunn return err; 468a605a0feSAndrew Lunn 469a605a0feSAndrew Lunn /* Wait for the snapshotting to complete. */ 470a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 471a605a0feSAndrew Lunn } 472a605a0feSAndrew Lunn 473a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 474a605a0feSAndrew Lunn { 475a605a0feSAndrew Lunn port = (port + 1) << 5; 476a605a0feSAndrew Lunn 477a605a0feSAndrew Lunn return mv88e6xxx_g1_stats_snapshot(chip, port); 478a605a0feSAndrew Lunn } 47979523473SAndrew Lunn 48079523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 48179523473SAndrew Lunn { 48279523473SAndrew Lunn int err; 48379523473SAndrew Lunn 48479523473SAndrew Lunn port = (port + 1) << 5; 48579523473SAndrew Lunn 48679523473SAndrew Lunn /* Snapshot the hardware statistics counters for this port. */ 48757d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 48857d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 48957d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port); 49079523473SAndrew Lunn if (err) 49179523473SAndrew Lunn return err; 49279523473SAndrew Lunn 49379523473SAndrew Lunn /* Wait for the snapshotting to complete. */ 49479523473SAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 49579523473SAndrew Lunn } 4967f9ef3afSAndrew Lunn 4977f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val) 4987f9ef3afSAndrew Lunn { 4997f9ef3afSAndrew Lunn u32 value; 5007f9ef3afSAndrew Lunn u16 reg; 5017f9ef3afSAndrew Lunn int err; 5027f9ef3afSAndrew Lunn 5037f9ef3afSAndrew Lunn *val = 0; 5047f9ef3afSAndrew Lunn 50557d1ef38SVivien Didelot err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 50657d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_BUSY | 50757d1ef38SVivien Didelot MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat); 5087f9ef3afSAndrew Lunn if (err) 5097f9ef3afSAndrew Lunn return; 5107f9ef3afSAndrew Lunn 5117f9ef3afSAndrew Lunn err = mv88e6xxx_g1_stats_wait(chip); 5127f9ef3afSAndrew Lunn if (err) 5137f9ef3afSAndrew Lunn return; 5147f9ef3afSAndrew Lunn 51557d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, ®); 5167f9ef3afSAndrew Lunn if (err) 5177f9ef3afSAndrew Lunn return; 5187f9ef3afSAndrew Lunn 5197f9ef3afSAndrew Lunn value = reg << 16; 5207f9ef3afSAndrew Lunn 52157d1ef38SVivien Didelot err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, ®); 5227f9ef3afSAndrew Lunn if (err) 5237f9ef3afSAndrew Lunn return; 5247f9ef3afSAndrew Lunn 5257f9ef3afSAndrew Lunn *val = value | reg; 5267f9ef3afSAndrew Lunn } 52740cff8fcSAndrew Lunn 52840cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip) 52940cff8fcSAndrew Lunn { 53040cff8fcSAndrew Lunn int err; 53140cff8fcSAndrew Lunn u16 val; 53240cff8fcSAndrew Lunn 53340cff8fcSAndrew Lunn err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val); 53440cff8fcSAndrew Lunn if (err) 53540cff8fcSAndrew Lunn return err; 53640cff8fcSAndrew Lunn 537a9049ff9SAndrew Lunn /* Keep the histogram mode bits */ 538a9049ff9SAndrew Lunn val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX; 53940cff8fcSAndrew Lunn val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL; 54040cff8fcSAndrew Lunn 54140cff8fcSAndrew Lunn err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val); 54240cff8fcSAndrew Lunn if (err) 54340cff8fcSAndrew Lunn return err; 54440cff8fcSAndrew Lunn 54540cff8fcSAndrew Lunn /* Wait for the flush to complete. */ 54640cff8fcSAndrew Lunn return mv88e6xxx_g1_stats_wait(chip); 54740cff8fcSAndrew Lunn } 548