1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Microchip KSZ8795 switch driver 4 * 5 * Copyright (C) 2017 Microchip Technology Inc. 6 * Tristram Ha <Tristram.Ha@microchip.com> 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/delay.h> 11 #include <linux/export.h> 12 #include <linux/gpio.h> 13 #include <linux/if_vlan.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/platform_data/microchip-ksz.h> 17 #include <linux/phy.h> 18 #include <linux/etherdevice.h> 19 #include <linux/if_bridge.h> 20 #include <linux/micrel_phy.h> 21 #include <net/dsa.h> 22 #include <net/switchdev.h> 23 #include <linux/phylink.h> 24 25 #include "ksz_common.h" 26 #include "ksz8795_reg.h" 27 #include "ksz8.h" 28 29 static const u8 ksz8795_regs[] = { 30 [REG_IND_CTRL_0] = 0x6E, 31 [REG_IND_DATA_8] = 0x70, 32 [REG_IND_DATA_CHECK] = 0x72, 33 [REG_IND_DATA_HI] = 0x71, 34 [REG_IND_DATA_LO] = 0x75, 35 [REG_IND_MIB_CHECK] = 0x74, 36 [REG_IND_BYTE] = 0xA0, 37 [P_FORCE_CTRL] = 0x0C, 38 [P_LINK_STATUS] = 0x0E, 39 [P_LOCAL_CTRL] = 0x07, 40 [P_NEG_RESTART_CTRL] = 0x0D, 41 [P_REMOTE_STATUS] = 0x08, 42 [P_SPEED_STATUS] = 0x09, 43 [S_TAIL_TAG_CTRL] = 0x0C, 44 }; 45 46 static const u32 ksz8795_masks[] = { 47 [PORT_802_1P_REMAPPING] = BIT(7), 48 [SW_TAIL_TAG_ENABLE] = BIT(1), 49 [MIB_COUNTER_OVERFLOW] = BIT(6), 50 [MIB_COUNTER_VALID] = BIT(5), 51 [VLAN_TABLE_FID] = GENMASK(6, 0), 52 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7), 53 [VLAN_TABLE_VALID] = BIT(12), 54 [STATIC_MAC_TABLE_VALID] = BIT(21), 55 [STATIC_MAC_TABLE_USE_FID] = BIT(23), 56 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24), 57 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26), 58 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20), 59 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0), 60 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8), 61 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 62 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29), 63 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20), 64 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24), 65 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27), 66 }; 67 68 static const u8 ksz8795_shifts[] = { 69 [VLAN_TABLE_MEMBERSHIP_S] = 7, 70 [VLAN_TABLE] = 16, 71 [STATIC_MAC_FWD_PORTS] = 16, 72 [STATIC_MAC_FID] = 24, 73 [DYNAMIC_MAC_ENTRIES_H] = 3, 74 [DYNAMIC_MAC_ENTRIES] = 29, 75 [DYNAMIC_MAC_FID] = 16, 76 [DYNAMIC_MAC_TIMESTAMP] = 27, 77 [DYNAMIC_MAC_SRC_PORT] = 24, 78 }; 79 80 static const u8 ksz8863_regs[] = { 81 [REG_IND_CTRL_0] = 0x79, 82 [REG_IND_DATA_8] = 0x7B, 83 [REG_IND_DATA_CHECK] = 0x7B, 84 [REG_IND_DATA_HI] = 0x7C, 85 [REG_IND_DATA_LO] = 0x80, 86 [REG_IND_MIB_CHECK] = 0x80, 87 [P_FORCE_CTRL] = 0x0C, 88 [P_LINK_STATUS] = 0x0E, 89 [P_LOCAL_CTRL] = 0x0C, 90 [P_NEG_RESTART_CTRL] = 0x0D, 91 [P_REMOTE_STATUS] = 0x0E, 92 [P_SPEED_STATUS] = 0x0F, 93 [S_TAIL_TAG_CTRL] = 0x03, 94 }; 95 96 static const u32 ksz8863_masks[] = { 97 [PORT_802_1P_REMAPPING] = BIT(3), 98 [SW_TAIL_TAG_ENABLE] = BIT(6), 99 [MIB_COUNTER_OVERFLOW] = BIT(7), 100 [MIB_COUNTER_VALID] = BIT(6), 101 [VLAN_TABLE_FID] = GENMASK(15, 12), 102 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16), 103 [VLAN_TABLE_VALID] = BIT(19), 104 [STATIC_MAC_TABLE_VALID] = BIT(19), 105 [STATIC_MAC_TABLE_USE_FID] = BIT(21), 106 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26), 107 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20), 108 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16), 109 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0), 110 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7), 111 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7), 112 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28), 113 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16), 114 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20), 115 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22), 116 }; 117 118 static u8 ksz8863_shifts[] = { 119 [VLAN_TABLE_MEMBERSHIP_S] = 16, 120 [STATIC_MAC_FWD_PORTS] = 16, 121 [STATIC_MAC_FID] = 22, 122 [DYNAMIC_MAC_ENTRIES_H] = 3, 123 [DYNAMIC_MAC_ENTRIES] = 24, 124 [DYNAMIC_MAC_FID] = 16, 125 [DYNAMIC_MAC_TIMESTAMP] = 24, 126 [DYNAMIC_MAC_SRC_PORT] = 20, 127 }; 128 129 static bool ksz_is_ksz88x3(struct ksz_device *dev) 130 { 131 return dev->chip_id == 0x8830; 132 } 133 134 static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set) 135 { 136 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0); 137 } 138 139 static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits, 140 bool set) 141 { 142 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset), 143 bits, set ? bits : 0); 144 } 145 146 static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data) 147 { 148 struct ksz8 *ksz8 = dev->priv; 149 const u8 *regs = ksz8->regs; 150 u16 ctrl_addr; 151 int ret = 0; 152 153 mutex_lock(&dev->alu_mutex); 154 155 ctrl_addr = IND_ACC_TABLE(table) | addr; 156 ret = ksz_write8(dev, regs[REG_IND_BYTE], data); 157 if (!ret) 158 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 159 160 mutex_unlock(&dev->alu_mutex); 161 162 return ret; 163 } 164 165 static int ksz8_reset_switch(struct ksz_device *dev) 166 { 167 if (ksz_is_ksz88x3(dev)) { 168 /* reset switch */ 169 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 170 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true); 171 ksz_cfg(dev, KSZ8863_REG_SW_RESET, 172 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false); 173 } else { 174 /* reset switch */ 175 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 176 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S); 177 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0); 178 } 179 180 return 0; 181 } 182 183 static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue) 184 { 185 u8 hi, lo; 186 187 /* Number of queues can only be 1, 2, or 4. */ 188 switch (queue) { 189 case 4: 190 case 3: 191 queue = PORT_QUEUE_SPLIT_4; 192 break; 193 case 2: 194 queue = PORT_QUEUE_SPLIT_2; 195 break; 196 default: 197 queue = PORT_QUEUE_SPLIT_1; 198 } 199 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo); 200 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi); 201 lo &= ~PORT_QUEUE_SPLIT_L; 202 if (queue & PORT_QUEUE_SPLIT_2) 203 lo |= PORT_QUEUE_SPLIT_L; 204 hi &= ~PORT_QUEUE_SPLIT_H; 205 if (queue & PORT_QUEUE_SPLIT_4) 206 hi |= PORT_QUEUE_SPLIT_H; 207 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo); 208 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi); 209 210 /* Default is port based for egress rate limit. */ 211 if (queue != PORT_QUEUE_SPLIT_1) 212 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED, 213 true); 214 } 215 216 static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt) 217 { 218 struct ksz8 *ksz8 = dev->priv; 219 const u32 *masks; 220 const u8 *regs; 221 u16 ctrl_addr; 222 u32 data; 223 u8 check; 224 int loop; 225 226 masks = ksz8->masks; 227 regs = ksz8->regs; 228 229 ctrl_addr = addr + dev->info->reg_mib_cnt * port; 230 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 231 232 mutex_lock(&dev->alu_mutex); 233 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 234 235 /* It is almost guaranteed to always read the valid bit because of 236 * slow SPI speed. 237 */ 238 for (loop = 2; loop > 0; loop--) { 239 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 240 241 if (check & masks[MIB_COUNTER_VALID]) { 242 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 243 if (check & masks[MIB_COUNTER_OVERFLOW]) 244 *cnt += MIB_COUNTER_VALUE + 1; 245 *cnt += data & MIB_COUNTER_VALUE; 246 break; 247 } 248 } 249 mutex_unlock(&dev->alu_mutex); 250 } 251 252 static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 253 u64 *dropped, u64 *cnt) 254 { 255 struct ksz8 *ksz8 = dev->priv; 256 const u32 *masks; 257 const u8 *regs; 258 u16 ctrl_addr; 259 u32 data; 260 u8 check; 261 int loop; 262 263 masks = ksz8->masks; 264 regs = ksz8->regs; 265 266 addr -= dev->info->reg_mib_cnt; 267 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port; 268 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0; 269 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 270 271 mutex_lock(&dev->alu_mutex); 272 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 273 274 /* It is almost guaranteed to always read the valid bit because of 275 * slow SPI speed. 276 */ 277 for (loop = 2; loop > 0; loop--) { 278 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check); 279 280 if (check & masks[MIB_COUNTER_VALID]) { 281 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 282 if (addr < 2) { 283 u64 total; 284 285 total = check & MIB_TOTAL_BYTES_H; 286 total <<= 32; 287 *cnt += total; 288 *cnt += data; 289 if (check & masks[MIB_COUNTER_OVERFLOW]) { 290 total = MIB_TOTAL_BYTES_H + 1; 291 total <<= 32; 292 *cnt += total; 293 } 294 } else { 295 if (check & masks[MIB_COUNTER_OVERFLOW]) 296 *cnt += MIB_PACKET_DROPPED + 1; 297 *cnt += data & MIB_PACKET_DROPPED; 298 } 299 break; 300 } 301 } 302 mutex_unlock(&dev->alu_mutex); 303 } 304 305 static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 306 u64 *dropped, u64 *cnt) 307 { 308 struct ksz8 *ksz8 = dev->priv; 309 const u8 *regs = ksz8->regs; 310 u32 *last = (u32 *)dropped; 311 u16 ctrl_addr; 312 u32 data; 313 u32 cur; 314 315 addr -= dev->info->reg_mib_cnt; 316 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 : 317 KSZ8863_MIB_PACKET_DROPPED_RX_0; 318 ctrl_addr += port; 319 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ); 320 321 mutex_lock(&dev->alu_mutex); 322 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 323 ksz_read32(dev, regs[REG_IND_DATA_LO], &data); 324 mutex_unlock(&dev->alu_mutex); 325 326 data &= MIB_PACKET_DROPPED; 327 cur = last[addr]; 328 if (data != cur) { 329 last[addr] = data; 330 if (data < cur) 331 data += MIB_PACKET_DROPPED + 1; 332 data -= cur; 333 *cnt += data; 334 } 335 } 336 337 static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr, 338 u64 *dropped, u64 *cnt) 339 { 340 if (ksz_is_ksz88x3(dev)) 341 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt); 342 else 343 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt); 344 } 345 346 static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze) 347 { 348 if (ksz_is_ksz88x3(dev)) 349 return; 350 351 /* enable the port for flush/freeze function */ 352 if (freeze) 353 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 354 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze); 355 356 /* disable the port after freeze is done */ 357 if (!freeze) 358 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 359 } 360 361 static void ksz8_port_init_cnt(struct ksz_device *dev, int port) 362 { 363 struct ksz_port_mib *mib = &dev->ports[port].mib; 364 u64 *dropped; 365 366 if (!ksz_is_ksz88x3(dev)) { 367 /* flush all enabled port MIB counters */ 368 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true); 369 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true); 370 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false); 371 } 372 373 mib->cnt_ptr = 0; 374 375 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */ 376 while (mib->cnt_ptr < dev->info->reg_mib_cnt) { 377 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr, 378 &mib->counters[mib->cnt_ptr]); 379 ++mib->cnt_ptr; 380 } 381 382 /* last one in storage */ 383 dropped = &mib->counters[dev->info->mib_cnt]; 384 385 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */ 386 while (mib->cnt_ptr < dev->info->mib_cnt) { 387 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr, 388 dropped, &mib->counters[mib->cnt_ptr]); 389 ++mib->cnt_ptr; 390 } 391 } 392 393 static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data) 394 { 395 struct ksz8 *ksz8 = dev->priv; 396 const u8 *regs = ksz8->regs; 397 u16 ctrl_addr; 398 399 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr; 400 401 mutex_lock(&dev->alu_mutex); 402 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 403 ksz_read64(dev, regs[REG_IND_DATA_HI], data); 404 mutex_unlock(&dev->alu_mutex); 405 } 406 407 static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data) 408 { 409 struct ksz8 *ksz8 = dev->priv; 410 const u8 *regs = ksz8->regs; 411 u16 ctrl_addr; 412 413 ctrl_addr = IND_ACC_TABLE(table) | addr; 414 415 mutex_lock(&dev->alu_mutex); 416 ksz_write64(dev, regs[REG_IND_DATA_HI], data); 417 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 418 mutex_unlock(&dev->alu_mutex); 419 } 420 421 static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data) 422 { 423 struct ksz8 *ksz8 = dev->priv; 424 int timeout = 100; 425 const u32 *masks; 426 const u8 *regs; 427 428 masks = ksz8->masks; 429 regs = ksz8->regs; 430 431 do { 432 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data); 433 timeout--; 434 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout); 435 436 /* Entry is not ready for accessing. */ 437 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) { 438 return -EAGAIN; 439 /* Entry is ready for accessing. */ 440 } else { 441 ksz_read8(dev, regs[REG_IND_DATA_8], data); 442 443 /* There is no valid entry in the table. */ 444 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY]) 445 return -ENXIO; 446 } 447 return 0; 448 } 449 450 static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, 451 u8 *mac_addr, u8 *fid, u8 *src_port, 452 u8 *timestamp, u16 *entries) 453 { 454 struct ksz8 *ksz8 = dev->priv; 455 u32 data_hi, data_lo; 456 const u8 *shifts; 457 const u32 *masks; 458 const u8 *regs; 459 u16 ctrl_addr; 460 u8 data; 461 int rc; 462 463 shifts = ksz8->shifts; 464 masks = ksz8->masks; 465 regs = ksz8->regs; 466 467 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr; 468 469 mutex_lock(&dev->alu_mutex); 470 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr); 471 472 rc = ksz8_valid_dyn_entry(dev, &data); 473 if (rc == -EAGAIN) { 474 if (addr == 0) 475 *entries = 0; 476 } else if (rc == -ENXIO) { 477 *entries = 0; 478 /* At least one valid entry in the table. */ 479 } else { 480 u64 buf = 0; 481 int cnt; 482 483 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf); 484 data_hi = (u32)(buf >> 32); 485 data_lo = (u32)buf; 486 487 /* Check out how many valid entry in the table. */ 488 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H]; 489 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H]; 490 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >> 491 shifts[DYNAMIC_MAC_ENTRIES]; 492 *entries = cnt + 1; 493 494 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >> 495 shifts[DYNAMIC_MAC_FID]; 496 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >> 497 shifts[DYNAMIC_MAC_SRC_PORT]; 498 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >> 499 shifts[DYNAMIC_MAC_TIMESTAMP]; 500 501 mac_addr[5] = (u8)data_lo; 502 mac_addr[4] = (u8)(data_lo >> 8); 503 mac_addr[3] = (u8)(data_lo >> 16); 504 mac_addr[2] = (u8)(data_lo >> 24); 505 506 mac_addr[1] = (u8)data_hi; 507 mac_addr[0] = (u8)(data_hi >> 8); 508 rc = 0; 509 } 510 mutex_unlock(&dev->alu_mutex); 511 512 return rc; 513 } 514 515 static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr, 516 struct alu_struct *alu) 517 { 518 struct ksz8 *ksz8 = dev->priv; 519 u32 data_hi, data_lo; 520 const u8 *shifts; 521 const u32 *masks; 522 u64 data; 523 524 shifts = ksz8->shifts; 525 masks = ksz8->masks; 526 527 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data); 528 data_hi = data >> 32; 529 data_lo = (u32)data; 530 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] | 531 masks[STATIC_MAC_TABLE_OVERRIDE])) { 532 alu->mac[5] = (u8)data_lo; 533 alu->mac[4] = (u8)(data_lo >> 8); 534 alu->mac[3] = (u8)(data_lo >> 16); 535 alu->mac[2] = (u8)(data_lo >> 24); 536 alu->mac[1] = (u8)data_hi; 537 alu->mac[0] = (u8)(data_hi >> 8); 538 alu->port_forward = 539 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >> 540 shifts[STATIC_MAC_FWD_PORTS]; 541 alu->is_override = 542 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0; 543 data_hi >>= 1; 544 alu->is_static = true; 545 alu->is_use_fid = 546 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0; 547 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >> 548 shifts[STATIC_MAC_FID]; 549 return 0; 550 } 551 return -ENXIO; 552 } 553 554 static void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr, 555 struct alu_struct *alu) 556 { 557 struct ksz8 *ksz8 = dev->priv; 558 u32 data_hi, data_lo; 559 const u8 *shifts; 560 const u32 *masks; 561 u64 data; 562 563 shifts = ksz8->shifts; 564 masks = ksz8->masks; 565 566 data_lo = ((u32)alu->mac[2] << 24) | 567 ((u32)alu->mac[3] << 16) | 568 ((u32)alu->mac[4] << 8) | alu->mac[5]; 569 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1]; 570 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS]; 571 572 if (alu->is_override) 573 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE]; 574 if (alu->is_use_fid) { 575 data_hi |= masks[STATIC_MAC_TABLE_USE_FID]; 576 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID]; 577 } 578 if (alu->is_static) 579 data_hi |= masks[STATIC_MAC_TABLE_VALID]; 580 else 581 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE]; 582 583 data = (u64)data_hi << 32 | data_lo; 584 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data); 585 } 586 587 static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid, 588 u8 *member, u8 *valid) 589 { 590 struct ksz8 *ksz8 = dev->priv; 591 const u8 *shifts; 592 const u32 *masks; 593 594 shifts = ksz8->shifts; 595 masks = ksz8->masks; 596 597 *fid = vlan & masks[VLAN_TABLE_FID]; 598 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >> 599 shifts[VLAN_TABLE_MEMBERSHIP_S]; 600 *valid = !!(vlan & masks[VLAN_TABLE_VALID]); 601 } 602 603 static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid, 604 u16 *vlan) 605 { 606 struct ksz8 *ksz8 = dev->priv; 607 const u8 *shifts; 608 const u32 *masks; 609 610 shifts = ksz8->shifts; 611 masks = ksz8->masks; 612 613 *vlan = fid; 614 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S]; 615 if (valid) 616 *vlan |= masks[VLAN_TABLE_VALID]; 617 } 618 619 static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr) 620 { 621 struct ksz8 *ksz8 = dev->priv; 622 const u8 *shifts; 623 u64 data; 624 int i; 625 626 shifts = ksz8->shifts; 627 628 ksz8_r_table(dev, TABLE_VLAN, addr, &data); 629 addr *= 4; 630 for (i = 0; i < 4; i++) { 631 dev->vlan_cache[addr + i].table[0] = (u16)data; 632 data >>= shifts[VLAN_TABLE]; 633 } 634 } 635 636 static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan) 637 { 638 int index; 639 u16 *data; 640 u16 addr; 641 u64 buf; 642 643 data = (u16 *)&buf; 644 addr = vid / 4; 645 index = vid & 3; 646 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 647 *vlan = data[index]; 648 } 649 650 static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan) 651 { 652 int index; 653 u16 *data; 654 u16 addr; 655 u64 buf; 656 657 data = (u16 *)&buf; 658 addr = vid / 4; 659 index = vid & 3; 660 ksz8_r_table(dev, TABLE_VLAN, addr, &buf); 661 data[index] = vlan; 662 dev->vlan_cache[vid].table[0] = vlan; 663 ksz8_w_table(dev, TABLE_VLAN, addr, buf); 664 } 665 666 static void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val) 667 { 668 struct ksz8 *ksz8 = dev->priv; 669 u8 restart, speed, ctrl, link; 670 const u8 *regs = ksz8->regs; 671 int processed = true; 672 u8 val1, val2; 673 u16 data = 0; 674 u8 p = phy; 675 676 switch (reg) { 677 case MII_BMCR: 678 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 679 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 680 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 681 if (restart & PORT_PHY_LOOPBACK) 682 data |= BMCR_LOOPBACK; 683 if (ctrl & PORT_FORCE_100_MBIT) 684 data |= BMCR_SPEED100; 685 if (ksz_is_ksz88x3(dev)) { 686 if ((ctrl & PORT_AUTO_NEG_ENABLE)) 687 data |= BMCR_ANENABLE; 688 } else { 689 if (!(ctrl & PORT_AUTO_NEG_DISABLE)) 690 data |= BMCR_ANENABLE; 691 } 692 if (restart & PORT_POWER_DOWN) 693 data |= BMCR_PDOWN; 694 if (restart & PORT_AUTO_NEG_RESTART) 695 data |= BMCR_ANRESTART; 696 if (ctrl & PORT_FORCE_FULL_DUPLEX) 697 data |= BMCR_FULLDPLX; 698 if (speed & PORT_HP_MDIX) 699 data |= KSZ886X_BMCR_HP_MDIX; 700 if (restart & PORT_FORCE_MDIX) 701 data |= KSZ886X_BMCR_FORCE_MDI; 702 if (restart & PORT_AUTO_MDIX_DISABLE) 703 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX; 704 if (restart & PORT_TX_DISABLE) 705 data |= KSZ886X_BMCR_DISABLE_TRANSMIT; 706 if (restart & PORT_LED_OFF) 707 data |= KSZ886X_BMCR_DISABLE_LED; 708 break; 709 case MII_BMSR: 710 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 711 data = BMSR_100FULL | 712 BMSR_100HALF | 713 BMSR_10FULL | 714 BMSR_10HALF | 715 BMSR_ANEGCAPABLE; 716 if (link & PORT_AUTO_NEG_COMPLETE) 717 data |= BMSR_ANEGCOMPLETE; 718 if (link & PORT_STAT_LINK_GOOD) 719 data |= BMSR_LSTATUS; 720 break; 721 case MII_PHYSID1: 722 data = KSZ8795_ID_HI; 723 break; 724 case MII_PHYSID2: 725 if (ksz_is_ksz88x3(dev)) 726 data = KSZ8863_ID_LO; 727 else 728 data = KSZ8795_ID_LO; 729 break; 730 case MII_ADVERTISE: 731 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 732 data = ADVERTISE_CSMA; 733 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE) 734 data |= ADVERTISE_PAUSE_CAP; 735 if (ctrl & PORT_AUTO_NEG_100BTX_FD) 736 data |= ADVERTISE_100FULL; 737 if (ctrl & PORT_AUTO_NEG_100BTX) 738 data |= ADVERTISE_100HALF; 739 if (ctrl & PORT_AUTO_NEG_10BT_FD) 740 data |= ADVERTISE_10FULL; 741 if (ctrl & PORT_AUTO_NEG_10BT) 742 data |= ADVERTISE_10HALF; 743 break; 744 case MII_LPA: 745 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link); 746 data = LPA_SLCT; 747 if (link & PORT_REMOTE_SYM_PAUSE) 748 data |= LPA_PAUSE_CAP; 749 if (link & PORT_REMOTE_100BTX_FD) 750 data |= LPA_100FULL; 751 if (link & PORT_REMOTE_100BTX) 752 data |= LPA_100HALF; 753 if (link & PORT_REMOTE_10BT_FD) 754 data |= LPA_10FULL; 755 if (link & PORT_REMOTE_10BT) 756 data |= LPA_10HALF; 757 if (data & ~LPA_SLCT) 758 data |= LPA_LPACK; 759 break; 760 case PHY_REG_LINK_MD: 761 ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1); 762 ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2); 763 if (val1 & PORT_START_CABLE_DIAG) 764 data |= PHY_START_CABLE_DIAG; 765 766 if (val1 & PORT_CABLE_10M_SHORT) 767 data |= PHY_CABLE_10M_SHORT; 768 769 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M, 770 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1)); 771 772 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M, 773 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) | 774 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2)); 775 break; 776 case PHY_REG_PHY_CTRL: 777 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link); 778 if (link & PORT_MDIX_STATUS) 779 data |= KSZ886X_CTRL_MDIX_STAT; 780 break; 781 default: 782 processed = false; 783 break; 784 } 785 if (processed) 786 *val = data; 787 } 788 789 static void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val) 790 { 791 struct ksz8 *ksz8 = dev->priv; 792 u8 restart, speed, ctrl, data; 793 const u8 *regs = ksz8->regs; 794 u8 p = phy; 795 796 switch (reg) { 797 case MII_BMCR: 798 799 /* Do not support PHY reset function. */ 800 if (val & BMCR_RESET) 801 break; 802 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed); 803 data = speed; 804 if (val & KSZ886X_BMCR_HP_MDIX) 805 data |= PORT_HP_MDIX; 806 else 807 data &= ~PORT_HP_MDIX; 808 if (data != speed) 809 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data); 810 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl); 811 data = ctrl; 812 if (ksz_is_ksz88x3(dev)) { 813 if ((val & BMCR_ANENABLE)) 814 data |= PORT_AUTO_NEG_ENABLE; 815 else 816 data &= ~PORT_AUTO_NEG_ENABLE; 817 } else { 818 if (!(val & BMCR_ANENABLE)) 819 data |= PORT_AUTO_NEG_DISABLE; 820 else 821 data &= ~PORT_AUTO_NEG_DISABLE; 822 823 /* Fiber port does not support auto-negotiation. */ 824 if (dev->ports[p].fiber) 825 data |= PORT_AUTO_NEG_DISABLE; 826 } 827 828 if (val & BMCR_SPEED100) 829 data |= PORT_FORCE_100_MBIT; 830 else 831 data &= ~PORT_FORCE_100_MBIT; 832 if (val & BMCR_FULLDPLX) 833 data |= PORT_FORCE_FULL_DUPLEX; 834 else 835 data &= ~PORT_FORCE_FULL_DUPLEX; 836 if (data != ctrl) 837 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data); 838 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart); 839 data = restart; 840 if (val & KSZ886X_BMCR_DISABLE_LED) 841 data |= PORT_LED_OFF; 842 else 843 data &= ~PORT_LED_OFF; 844 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT) 845 data |= PORT_TX_DISABLE; 846 else 847 data &= ~PORT_TX_DISABLE; 848 if (val & BMCR_ANRESTART) 849 data |= PORT_AUTO_NEG_RESTART; 850 else 851 data &= ~(PORT_AUTO_NEG_RESTART); 852 if (val & BMCR_PDOWN) 853 data |= PORT_POWER_DOWN; 854 else 855 data &= ~PORT_POWER_DOWN; 856 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX) 857 data |= PORT_AUTO_MDIX_DISABLE; 858 else 859 data &= ~PORT_AUTO_MDIX_DISABLE; 860 if (val & KSZ886X_BMCR_FORCE_MDI) 861 data |= PORT_FORCE_MDIX; 862 else 863 data &= ~PORT_FORCE_MDIX; 864 if (val & BMCR_LOOPBACK) 865 data |= PORT_PHY_LOOPBACK; 866 else 867 data &= ~PORT_PHY_LOOPBACK; 868 if (data != restart) 869 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data); 870 break; 871 case MII_ADVERTISE: 872 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl); 873 data = ctrl; 874 data &= ~(PORT_AUTO_NEG_SYM_PAUSE | 875 PORT_AUTO_NEG_100BTX_FD | 876 PORT_AUTO_NEG_100BTX | 877 PORT_AUTO_NEG_10BT_FD | 878 PORT_AUTO_NEG_10BT); 879 if (val & ADVERTISE_PAUSE_CAP) 880 data |= PORT_AUTO_NEG_SYM_PAUSE; 881 if (val & ADVERTISE_100FULL) 882 data |= PORT_AUTO_NEG_100BTX_FD; 883 if (val & ADVERTISE_100HALF) 884 data |= PORT_AUTO_NEG_100BTX; 885 if (val & ADVERTISE_10FULL) 886 data |= PORT_AUTO_NEG_10BT_FD; 887 if (val & ADVERTISE_10HALF) 888 data |= PORT_AUTO_NEG_10BT; 889 if (data != ctrl) 890 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data); 891 break; 892 case PHY_REG_LINK_MD: 893 if (val & PHY_START_CABLE_DIAG) 894 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true); 895 break; 896 default: 897 break; 898 } 899 } 900 901 static enum dsa_tag_protocol ksz8_get_tag_protocol(struct dsa_switch *ds, 902 int port, 903 enum dsa_tag_protocol mp) 904 { 905 struct ksz_device *dev = ds->priv; 906 907 /* ksz88x3 uses the same tag schema as KSZ9893 */ 908 return ksz_is_ksz88x3(dev) ? 909 DSA_TAG_PROTO_KSZ9893 : DSA_TAG_PROTO_KSZ8795; 910 } 911 912 static u32 ksz8_sw_get_phy_flags(struct dsa_switch *ds, int port) 913 { 914 /* Silicon Errata Sheet (DS80000830A): 915 * Port 1 does not work with LinkMD Cable-Testing. 916 * Port 1 does not respond to received PAUSE control frames. 917 */ 918 if (!port) 919 return MICREL_KSZ8_P1_ERRATA; 920 921 return 0; 922 } 923 924 static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member) 925 { 926 u8 data; 927 928 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 929 data &= ~PORT_VLAN_MEMBERSHIP; 930 data |= (member & dev->port_mask); 931 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data); 932 } 933 934 static void ksz8_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 935 { 936 ksz_port_stp_state_set(ds, port, state, P_STP_CTRL); 937 } 938 939 static void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port) 940 { 941 u8 learn[DSA_MAX_PORTS]; 942 int first, index, cnt; 943 struct ksz_port *p; 944 945 if ((uint)port < dev->info->port_cnt) { 946 first = port; 947 cnt = port + 1; 948 } else { 949 /* Flush all ports. */ 950 first = 0; 951 cnt = dev->info->port_cnt; 952 } 953 for (index = first; index < cnt; index++) { 954 p = &dev->ports[index]; 955 if (!p->on) 956 continue; 957 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]); 958 if (!(learn[index] & PORT_LEARN_DISABLE)) 959 ksz_pwrite8(dev, index, P_STP_CTRL, 960 learn[index] | PORT_LEARN_DISABLE); 961 } 962 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true); 963 for (index = first; index < cnt; index++) { 964 p = &dev->ports[index]; 965 if (!p->on) 966 continue; 967 if (!(learn[index] & PORT_LEARN_DISABLE)) 968 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]); 969 } 970 } 971 972 static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag, 973 struct netlink_ext_ack *extack) 974 { 975 struct ksz_device *dev = ds->priv; 976 977 if (ksz_is_ksz88x3(dev)) 978 return -ENOTSUPP; 979 980 /* Discard packets with VID not enabled on the switch */ 981 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag); 982 983 /* Discard packets with VID not enabled on the ingress port */ 984 for (port = 0; port < dev->phy_port_cnt; ++port) 985 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER, 986 flag); 987 988 return 0; 989 } 990 991 static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state) 992 { 993 if (ksz_is_ksz88x3(dev)) { 994 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID, 995 0x03 << (4 - 2 * port), state); 996 } else { 997 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00); 998 } 999 } 1000 1001 static int ksz8_port_vlan_add(struct dsa_switch *ds, int port, 1002 const struct switchdev_obj_port_vlan *vlan, 1003 struct netlink_ext_ack *extack) 1004 { 1005 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1006 struct ksz_device *dev = ds->priv; 1007 struct ksz_port *p = &dev->ports[port]; 1008 u16 data, new_pvid = 0; 1009 u8 fid, member, valid; 1010 1011 if (ksz_is_ksz88x3(dev)) 1012 return -ENOTSUPP; 1013 1014 /* If a VLAN is added with untagged flag different from the 1015 * port's Remove Tag flag, we need to change the latter. 1016 * Ignore VID 0, which is always untagged. 1017 * Ignore CPU port, which will always be tagged. 1018 */ 1019 if (untagged != p->remove_tag && vlan->vid != 0 && 1020 port != dev->cpu_port) { 1021 unsigned int vid; 1022 1023 /* Reject attempts to add a VLAN that requires the 1024 * Remove Tag flag to be changed, unless there are no 1025 * other VLANs currently configured. 1026 */ 1027 for (vid = 1; vid < dev->info->num_vlans; ++vid) { 1028 /* Skip the VID we are going to add or reconfigure */ 1029 if (vid == vlan->vid) 1030 continue; 1031 1032 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0], 1033 &fid, &member, &valid); 1034 if (valid && (member & BIT(port))) 1035 return -EINVAL; 1036 } 1037 1038 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged); 1039 p->remove_tag = untagged; 1040 } 1041 1042 ksz8_r_vlan_table(dev, vlan->vid, &data); 1043 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1044 1045 /* First time to setup the VLAN entry. */ 1046 if (!valid) { 1047 /* Need to find a way to map VID to FID. */ 1048 fid = 1; 1049 valid = 1; 1050 } 1051 member |= BIT(port); 1052 1053 ksz8_to_vlan(dev, fid, member, valid, &data); 1054 ksz8_w_vlan_table(dev, vlan->vid, data); 1055 1056 /* change PVID */ 1057 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) 1058 new_pvid = vlan->vid; 1059 1060 if (new_pvid) { 1061 u16 vid; 1062 1063 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid); 1064 vid &= ~VLAN_VID_MASK; 1065 vid |= new_pvid; 1066 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid); 1067 1068 ksz8_port_enable_pvid(dev, port, true); 1069 } 1070 1071 return 0; 1072 } 1073 1074 static int ksz8_port_vlan_del(struct dsa_switch *ds, int port, 1075 const struct switchdev_obj_port_vlan *vlan) 1076 { 1077 struct ksz_device *dev = ds->priv; 1078 u16 data, pvid; 1079 u8 fid, member, valid; 1080 1081 if (ksz_is_ksz88x3(dev)) 1082 return -ENOTSUPP; 1083 1084 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid); 1085 pvid = pvid & 0xFFF; 1086 1087 ksz8_r_vlan_table(dev, vlan->vid, &data); 1088 ksz8_from_vlan(dev, data, &fid, &member, &valid); 1089 1090 member &= ~BIT(port); 1091 1092 /* Invalidate the entry if no more member. */ 1093 if (!member) { 1094 fid = 0; 1095 valid = 0; 1096 } 1097 1098 ksz8_to_vlan(dev, fid, member, valid, &data); 1099 ksz8_w_vlan_table(dev, vlan->vid, data); 1100 1101 if (pvid == vlan->vid) 1102 ksz8_port_enable_pvid(dev, port, false); 1103 1104 return 0; 1105 } 1106 1107 static int ksz8_port_mirror_add(struct dsa_switch *ds, int port, 1108 struct dsa_mall_mirror_tc_entry *mirror, 1109 bool ingress, struct netlink_ext_ack *extack) 1110 { 1111 struct ksz_device *dev = ds->priv; 1112 1113 if (ingress) { 1114 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true); 1115 dev->mirror_rx |= BIT(port); 1116 } else { 1117 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true); 1118 dev->mirror_tx |= BIT(port); 1119 } 1120 1121 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false); 1122 1123 /* configure mirror port */ 1124 if (dev->mirror_rx || dev->mirror_tx) 1125 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1126 PORT_MIRROR_SNIFFER, true); 1127 1128 return 0; 1129 } 1130 1131 static void ksz8_port_mirror_del(struct dsa_switch *ds, int port, 1132 struct dsa_mall_mirror_tc_entry *mirror) 1133 { 1134 struct ksz_device *dev = ds->priv; 1135 u8 data; 1136 1137 if (mirror->ingress) { 1138 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false); 1139 dev->mirror_rx &= ~BIT(port); 1140 } else { 1141 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false); 1142 dev->mirror_tx &= ~BIT(port); 1143 } 1144 1145 ksz_pread8(dev, port, P_MIRROR_CTRL, &data); 1146 1147 if (!dev->mirror_rx && !dev->mirror_tx) 1148 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL, 1149 PORT_MIRROR_SNIFFER, false); 1150 } 1151 1152 static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port) 1153 { 1154 struct ksz_port *p = &dev->ports[port]; 1155 u8 data8; 1156 1157 if (!p->interface && dev->compat_interface) { 1158 dev_warn(dev->dev, 1159 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. " 1160 "Please update your device tree.\n", 1161 port); 1162 p->interface = dev->compat_interface; 1163 } 1164 1165 /* Configure MII interface for proper network communication. */ 1166 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8); 1167 data8 &= ~PORT_INTERFACE_TYPE; 1168 data8 &= ~PORT_GMII_1GPS_MODE; 1169 switch (p->interface) { 1170 case PHY_INTERFACE_MODE_MII: 1171 p->phydev.speed = SPEED_100; 1172 break; 1173 case PHY_INTERFACE_MODE_RMII: 1174 data8 |= PORT_INTERFACE_RMII; 1175 p->phydev.speed = SPEED_100; 1176 break; 1177 case PHY_INTERFACE_MODE_GMII: 1178 data8 |= PORT_GMII_1GPS_MODE; 1179 data8 |= PORT_INTERFACE_GMII; 1180 p->phydev.speed = SPEED_1000; 1181 break; 1182 default: 1183 data8 &= ~PORT_RGMII_ID_IN_ENABLE; 1184 data8 &= ~PORT_RGMII_ID_OUT_ENABLE; 1185 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1186 p->interface == PHY_INTERFACE_MODE_RGMII_RXID) 1187 data8 |= PORT_RGMII_ID_IN_ENABLE; 1188 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID || 1189 p->interface == PHY_INTERFACE_MODE_RGMII_TXID) 1190 data8 |= PORT_RGMII_ID_OUT_ENABLE; 1191 data8 |= PORT_GMII_1GPS_MODE; 1192 data8 |= PORT_INTERFACE_RGMII; 1193 p->phydev.speed = SPEED_1000; 1194 break; 1195 } 1196 ksz_write8(dev, REG_PORT_5_CTRL_6, data8); 1197 p->phydev.duplex = 1; 1198 } 1199 1200 static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port) 1201 { 1202 struct dsa_switch *ds = dev->ds; 1203 struct ksz8 *ksz8 = dev->priv; 1204 const u32 *masks; 1205 u8 member; 1206 1207 masks = ksz8->masks; 1208 1209 /* enable broadcast storm limit */ 1210 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true); 1211 1212 if (!ksz_is_ksz88x3(dev)) 1213 ksz8795_set_prio_queue(dev, port, 4); 1214 1215 /* disable DiffServ priority */ 1216 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false); 1217 1218 /* replace priority */ 1219 ksz_port_cfg(dev, port, P_802_1P_CTRL, 1220 masks[PORT_802_1P_REMAPPING], false); 1221 1222 /* enable 802.1p priority */ 1223 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true); 1224 1225 if (cpu_port) { 1226 if (!ksz_is_ksz88x3(dev)) 1227 ksz8795_cpu_interface_select(dev, port); 1228 1229 member = dsa_user_ports(ds); 1230 } else { 1231 member = BIT(dsa_upstream_port(ds, port)); 1232 } 1233 1234 ksz8_cfg_port_member(dev, port, member); 1235 } 1236 1237 static void ksz8_config_cpu_port(struct dsa_switch *ds) 1238 { 1239 struct ksz_device *dev = ds->priv; 1240 struct ksz8 *ksz8 = dev->priv; 1241 const u8 *regs = ksz8->regs; 1242 struct ksz_port *p; 1243 const u32 *masks; 1244 u8 remote; 1245 int i; 1246 1247 masks = ksz8->masks; 1248 1249 /* Switch marks the maximum frame with extra byte as oversize. */ 1250 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true); 1251 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true); 1252 1253 p = &dev->ports[dev->cpu_port]; 1254 p->on = 1; 1255 1256 ksz8_port_setup(dev, dev->cpu_port, true); 1257 1258 for (i = 0; i < dev->phy_port_cnt; i++) { 1259 p = &dev->ports[i]; 1260 1261 ksz8_port_stp_state_set(ds, i, BR_STATE_DISABLED); 1262 1263 /* Last port may be disabled. */ 1264 if (i == dev->phy_port_cnt) 1265 break; 1266 p->on = 1; 1267 p->phy = 1; 1268 } 1269 for (i = 0; i < dev->phy_port_cnt; i++) { 1270 p = &dev->ports[i]; 1271 if (!p->on) 1272 continue; 1273 if (!ksz_is_ksz88x3(dev)) { 1274 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote); 1275 if (remote & PORT_FIBER_MODE) 1276 p->fiber = 1; 1277 } 1278 if (p->fiber) 1279 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1280 true); 1281 else 1282 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL, 1283 false); 1284 } 1285 } 1286 1287 static int ksz8_handle_global_errata(struct dsa_switch *ds) 1288 { 1289 struct ksz_device *dev = ds->priv; 1290 int ret = 0; 1291 1292 /* KSZ87xx Errata DS80000687C. 1293 * Module 2: Link drops with some EEE link partners. 1294 * An issue with the EEE next page exchange between the 1295 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in 1296 * the link dropping. 1297 */ 1298 if (dev->info->ksz87xx_eee_link_erratum) 1299 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0); 1300 1301 return ret; 1302 } 1303 1304 static int ksz8_setup(struct dsa_switch *ds) 1305 { 1306 struct ksz_device *dev = ds->priv; 1307 struct alu_struct alu; 1308 int i, ret = 0; 1309 1310 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table), 1311 dev->info->num_vlans, GFP_KERNEL); 1312 if (!dev->vlan_cache) 1313 return -ENOMEM; 1314 1315 ret = ksz8_reset_switch(dev); 1316 if (ret) { 1317 dev_err(ds->dev, "failed to reset switch\n"); 1318 return ret; 1319 } 1320 1321 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true); 1322 1323 /* Enable automatic fast aging when link changed detected. */ 1324 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true); 1325 1326 /* Enable aggressive back off algorithm in half duplex mode. */ 1327 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1, 1328 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF); 1329 1330 /* 1331 * Make sure unicast VLAN boundary is set as default and 1332 * enable no excessive collision drop. 1333 */ 1334 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2, 1335 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP, 1336 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP); 1337 1338 ksz8_config_cpu_port(ds); 1339 1340 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true); 1341 1342 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false); 1343 1344 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false); 1345 1346 if (!ksz_is_ksz88x3(dev)) 1347 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true); 1348 1349 /* set broadcast storm protection 10% rate */ 1350 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL, 1351 BROADCAST_STORM_RATE, 1352 (BROADCAST_STORM_VALUE * 1353 BROADCAST_STORM_PROT_RATE) / 100); 1354 1355 for (i = 0; i < (dev->info->num_vlans / 4); i++) 1356 ksz8_r_vlan_entries(dev, i); 1357 1358 /* Setup STP address for STP operation. */ 1359 memset(&alu, 0, sizeof(alu)); 1360 ether_addr_copy(alu.mac, eth_stp_addr); 1361 alu.is_static = true; 1362 alu.is_override = true; 1363 alu.port_forward = dev->info->cpu_ports; 1364 1365 ksz8_w_sta_mac_table(dev, 0, &alu); 1366 1367 ksz_init_mib_timer(dev); 1368 1369 ds->configure_vlan_while_not_filtering = false; 1370 1371 return ksz8_handle_global_errata(ds); 1372 } 1373 1374 static void ksz8_get_caps(struct dsa_switch *ds, int port, 1375 struct phylink_config *config) 1376 { 1377 struct ksz_device *dev = ds->priv; 1378 1379 ksz_phylink_get_caps(ds, port, config); 1380 1381 config->mac_capabilities = MAC_10 | MAC_100; 1382 1383 /* Silicon Errata Sheet (DS80000830A): 1384 * "Port 1 does not respond to received flow control PAUSE frames" 1385 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3 1386 * switches. 1387 */ 1388 if (!ksz_is_ksz88x3(dev) || port) 1389 config->mac_capabilities |= MAC_SYM_PAUSE; 1390 1391 /* Asym pause is not supported on KSZ8863 and KSZ8873 */ 1392 if (!ksz_is_ksz88x3(dev)) 1393 config->mac_capabilities |= MAC_ASYM_PAUSE; 1394 } 1395 1396 static const struct dsa_switch_ops ksz8_switch_ops = { 1397 .get_tag_protocol = ksz8_get_tag_protocol, 1398 .get_phy_flags = ksz8_sw_get_phy_flags, 1399 .setup = ksz8_setup, 1400 .phy_read = ksz_phy_read16, 1401 .phy_write = ksz_phy_write16, 1402 .phylink_get_caps = ksz8_get_caps, 1403 .phylink_mac_link_down = ksz_mac_link_down, 1404 .port_enable = ksz_enable_port, 1405 .get_strings = ksz_get_strings, 1406 .get_ethtool_stats = ksz_get_ethtool_stats, 1407 .get_sset_count = ksz_sset_count, 1408 .port_bridge_join = ksz_port_bridge_join, 1409 .port_bridge_leave = ksz_port_bridge_leave, 1410 .port_stp_state_set = ksz8_port_stp_state_set, 1411 .port_fast_age = ksz_port_fast_age, 1412 .port_vlan_filtering = ksz8_port_vlan_filtering, 1413 .port_vlan_add = ksz8_port_vlan_add, 1414 .port_vlan_del = ksz8_port_vlan_del, 1415 .port_fdb_dump = ksz_port_fdb_dump, 1416 .port_mdb_add = ksz_port_mdb_add, 1417 .port_mdb_del = ksz_port_mdb_del, 1418 .port_mirror_add = ksz8_port_mirror_add, 1419 .port_mirror_del = ksz8_port_mirror_del, 1420 }; 1421 1422 static u32 ksz8_get_port_addr(int port, int offset) 1423 { 1424 return PORT_CTRL_ADDR(port, offset); 1425 } 1426 1427 static int ksz8_switch_detect(struct ksz_device *dev) 1428 { 1429 u8 id1, id2; 1430 u16 id16; 1431 int ret; 1432 1433 /* read chip id */ 1434 ret = ksz_read16(dev, REG_CHIP_ID0, &id16); 1435 if (ret) 1436 return ret; 1437 1438 id1 = id16 >> 8; 1439 id2 = id16 & SW_CHIP_ID_M; 1440 1441 switch (id1) { 1442 case KSZ87_FAMILY_ID: 1443 if ((id2 != CHIP_ID_94 && id2 != CHIP_ID_95)) 1444 return -ENODEV; 1445 1446 if (id2 == CHIP_ID_95) { 1447 u8 val; 1448 1449 id2 = 0x95; 1450 ksz_read8(dev, REG_PORT_STATUS_0, &val); 1451 if (val & PORT_FIBER_MODE) 1452 id2 = 0x65; 1453 } else if (id2 == CHIP_ID_94) { 1454 id2 = 0x94; 1455 } 1456 break; 1457 case KSZ88_FAMILY_ID: 1458 if (id2 != CHIP_ID_63) 1459 return -ENODEV; 1460 break; 1461 default: 1462 dev_err(dev->dev, "invalid family id: %d\n", id1); 1463 return -ENODEV; 1464 } 1465 id16 &= ~0xff; 1466 id16 |= id2; 1467 dev->chip_id = id16; 1468 1469 return 0; 1470 } 1471 1472 static int ksz8_switch_init(struct ksz_device *dev) 1473 { 1474 struct ksz8 *ksz8 = dev->priv; 1475 1476 dev->ds->ops = &ksz8_switch_ops; 1477 1478 dev->cpu_port = fls(dev->info->cpu_ports) - 1; 1479 dev->phy_port_cnt = dev->info->port_cnt - 1; 1480 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports; 1481 1482 if (ksz_is_ksz88x3(dev)) { 1483 ksz8->regs = ksz8863_regs; 1484 ksz8->masks = ksz8863_masks; 1485 ksz8->shifts = ksz8863_shifts; 1486 } else { 1487 ksz8->regs = ksz8795_regs; 1488 ksz8->masks = ksz8795_masks; 1489 ksz8->shifts = ksz8795_shifts; 1490 } 1491 1492 /* We rely on software untagging on the CPU port, so that we 1493 * can support both tagged and untagged VLANs 1494 */ 1495 dev->ds->untag_bridge_pvid = true; 1496 1497 /* VLAN filtering is partly controlled by the global VLAN 1498 * Enable flag 1499 */ 1500 dev->ds->vlan_filtering_is_global = true; 1501 1502 return 0; 1503 } 1504 1505 static void ksz8_switch_exit(struct ksz_device *dev) 1506 { 1507 ksz8_reset_switch(dev); 1508 } 1509 1510 static const struct ksz_dev_ops ksz8_dev_ops = { 1511 .get_port_addr = ksz8_get_port_addr, 1512 .cfg_port_member = ksz8_cfg_port_member, 1513 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table, 1514 .port_setup = ksz8_port_setup, 1515 .r_phy = ksz8_r_phy, 1516 .w_phy = ksz8_w_phy, 1517 .r_dyn_mac_table = ksz8_r_dyn_mac_table, 1518 .r_sta_mac_table = ksz8_r_sta_mac_table, 1519 .w_sta_mac_table = ksz8_w_sta_mac_table, 1520 .r_mib_cnt = ksz8_r_mib_cnt, 1521 .r_mib_pkt = ksz8_r_mib_pkt, 1522 .freeze_mib = ksz8_freeze_mib, 1523 .port_init_cnt = ksz8_port_init_cnt, 1524 .shutdown = ksz8_reset_switch, 1525 .detect = ksz8_switch_detect, 1526 .init = ksz8_switch_init, 1527 .exit = ksz8_switch_exit, 1528 }; 1529 1530 int ksz8_switch_register(struct ksz_device *dev) 1531 { 1532 return ksz_switch_register(dev, &ksz8_dev_ops); 1533 } 1534 EXPORT_SYMBOL(ksz8_switch_register); 1535 1536 MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>"); 1537 MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver"); 1538 MODULE_LICENSE("GPL"); 1539