1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver 4 // 5 // Copyright (c) 2019, 2020 Pengutronix, 6 // Marc Kleine-Budde <kernel@pengutronix.de> 7 // 8 // Based on: 9 // 10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface 11 // 12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org> 13 // 14 15 #include <linux/bitfield.h> 16 #include <linux/clk.h> 17 #include <linux/device.h> 18 #include <linux/module.h> 19 #include <linux/netdevice.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/pm_runtime.h> 23 24 #include <asm/unaligned.h> 25 26 #include "mcp251xfd.h" 27 28 #define DEVICE_NAME "mcp251xfd" 29 30 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = { 31 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG | 32 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX | 33 MCP251XFD_QUIRK_ECC, 34 .model = MCP251XFD_MODEL_MCP2517FD, 35 }; 36 37 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = { 38 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 39 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 40 .model = MCP251XFD_MODEL_MCP2518FD, 41 }; 42 43 /* Autodetect model, start with CRC enabled. */ 44 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = { 45 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 46 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 47 .model = MCP251XFD_MODEL_MCP251XFD, 48 }; 49 50 static const struct can_bittiming_const mcp251xfd_bittiming_const = { 51 .name = DEVICE_NAME, 52 .tseg1_min = 2, 53 .tseg1_max = 256, 54 .tseg2_min = 1, 55 .tseg2_max = 128, 56 .sjw_max = 128, 57 .brp_min = 1, 58 .brp_max = 256, 59 .brp_inc = 1, 60 }; 61 62 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = { 63 .name = DEVICE_NAME, 64 .tseg1_min = 1, 65 .tseg1_max = 32, 66 .tseg2_min = 1, 67 .tseg2_max = 16, 68 .sjw_max = 16, 69 .brp_min = 1, 70 .brp_max = 256, 71 .brp_inc = 1, 72 }; 73 74 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model) 75 { 76 switch (model) { 77 case MCP251XFD_MODEL_MCP2517FD: 78 return "MCP2517FD"; 79 case MCP251XFD_MODEL_MCP2518FD: 80 return "MCP2518FD"; 81 case MCP251XFD_MODEL_MCP251XFD: 82 return "MCP251xFD"; 83 } 84 85 return "<unknown>"; 86 } 87 88 static inline const char * 89 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv) 90 { 91 return __mcp251xfd_get_model_str(priv->devtype_data.model); 92 } 93 94 static const char *mcp251xfd_get_mode_str(const u8 mode) 95 { 96 switch (mode) { 97 case MCP251XFD_REG_CON_MODE_MIXED: 98 return "Mixed (CAN FD/CAN 2.0)"; 99 case MCP251XFD_REG_CON_MODE_SLEEP: 100 return "Sleep"; 101 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK: 102 return "Internal Loopback"; 103 case MCP251XFD_REG_CON_MODE_LISTENONLY: 104 return "Listen Only"; 105 case MCP251XFD_REG_CON_MODE_CONFIG: 106 return "Configuration"; 107 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK: 108 return "External Loopback"; 109 case MCP251XFD_REG_CON_MODE_CAN2_0: 110 return "CAN 2.0"; 111 case MCP251XFD_REG_CON_MODE_RESTRICTED: 112 return "Restricted Operation"; 113 } 114 115 return "<unknown>"; 116 } 117 118 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv) 119 { 120 if (!priv->reg_vdd) 121 return 0; 122 123 return regulator_enable(priv->reg_vdd); 124 } 125 126 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv) 127 { 128 if (!priv->reg_vdd) 129 return 0; 130 131 return regulator_disable(priv->reg_vdd); 132 } 133 134 static inline int 135 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv) 136 { 137 if (!priv->reg_xceiver) 138 return 0; 139 140 return regulator_enable(priv->reg_xceiver); 141 } 142 143 static inline int 144 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv) 145 { 146 if (!priv->reg_xceiver) 147 return 0; 148 149 return regulator_disable(priv->reg_xceiver); 150 } 151 152 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv) 153 { 154 int err; 155 156 err = clk_prepare_enable(priv->clk); 157 if (err) 158 return err; 159 160 err = mcp251xfd_vdd_enable(priv); 161 if (err) 162 clk_disable_unprepare(priv->clk); 163 164 /* Wait for oscillator stabilisation time after power up */ 165 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US, 166 2 * MCP251XFD_OSC_STAB_SLEEP_US); 167 168 return err; 169 } 170 171 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv) 172 { 173 int err; 174 175 err = mcp251xfd_vdd_disable(priv); 176 if (err) 177 return err; 178 179 clk_disable_unprepare(priv->clk); 180 181 return 0; 182 } 183 184 static inline u8 185 mcp251xfd_cmd_prepare_write_reg(const struct mcp251xfd_priv *priv, 186 union mcp251xfd_write_reg_buf *write_reg_buf, 187 const u16 reg, const u32 mask, const u32 val) 188 { 189 u8 first_byte, last_byte, len; 190 u8 *data; 191 __le32 val_le32; 192 193 first_byte = mcp251xfd_first_byte_set(mask); 194 last_byte = mcp251xfd_last_byte_set(mask); 195 len = last_byte - first_byte + 1; 196 197 data = mcp251xfd_spi_cmd_write(priv, write_reg_buf, reg + first_byte); 198 val_le32 = cpu_to_le32(val >> BITS_PER_BYTE * first_byte); 199 memcpy(data, &val_le32, len); 200 201 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_REG) { 202 u16 crc; 203 204 mcp251xfd_spi_cmd_crc_set_len_in_reg(&write_reg_buf->crc.cmd, 205 len); 206 /* CRC */ 207 len += sizeof(write_reg_buf->crc.cmd); 208 crc = mcp251xfd_crc16_compute(&write_reg_buf->crc, len); 209 put_unaligned_be16(crc, (void *)write_reg_buf + len); 210 211 /* Total length */ 212 len += sizeof(write_reg_buf->crc.crc); 213 } else { 214 len += sizeof(write_reg_buf->nocrc.cmd); 215 } 216 217 return len; 218 } 219 220 static inline int 221 mcp251xfd_tef_tail_get_from_chip(const struct mcp251xfd_priv *priv, 222 u8 *tef_tail) 223 { 224 u32 tef_ua; 225 int err; 226 227 err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFUA, &tef_ua); 228 if (err) 229 return err; 230 231 *tef_tail = tef_ua / sizeof(struct mcp251xfd_hw_tef_obj); 232 233 return 0; 234 } 235 236 static inline int 237 mcp251xfd_tx_tail_get_from_chip(const struct mcp251xfd_priv *priv, 238 u8 *tx_tail) 239 { 240 u32 fifo_sta; 241 int err; 242 243 err = regmap_read(priv->map_reg, 244 MCP251XFD_REG_FIFOSTA(MCP251XFD_TX_FIFO), 245 &fifo_sta); 246 if (err) 247 return err; 248 249 *tx_tail = FIELD_GET(MCP251XFD_REG_FIFOSTA_FIFOCI_MASK, fifo_sta); 250 251 return 0; 252 } 253 254 static inline int 255 mcp251xfd_rx_head_get_from_chip(const struct mcp251xfd_priv *priv, 256 const struct mcp251xfd_rx_ring *ring, 257 u8 *rx_head) 258 { 259 u32 fifo_sta; 260 int err; 261 262 err = regmap_read(priv->map_reg, MCP251XFD_REG_FIFOSTA(ring->fifo_nr), 263 &fifo_sta); 264 if (err) 265 return err; 266 267 *rx_head = FIELD_GET(MCP251XFD_REG_FIFOSTA_FIFOCI_MASK, fifo_sta); 268 269 return 0; 270 } 271 272 static inline int 273 mcp251xfd_rx_tail_get_from_chip(const struct mcp251xfd_priv *priv, 274 const struct mcp251xfd_rx_ring *ring, 275 u8 *rx_tail) 276 { 277 u32 fifo_ua; 278 int err; 279 280 err = regmap_read(priv->map_reg, MCP251XFD_REG_FIFOUA(ring->fifo_nr), 281 &fifo_ua); 282 if (err) 283 return err; 284 285 fifo_ua -= ring->base - MCP251XFD_RAM_START; 286 *rx_tail = fifo_ua / ring->obj_size; 287 288 return 0; 289 } 290 291 static void 292 mcp251xfd_tx_ring_init_tx_obj(const struct mcp251xfd_priv *priv, 293 const struct mcp251xfd_tx_ring *ring, 294 struct mcp251xfd_tx_obj *tx_obj, 295 const u8 rts_buf_len, 296 const u8 n) 297 { 298 struct spi_transfer *xfer; 299 u16 addr; 300 301 /* FIFO load */ 302 addr = mcp251xfd_get_tx_obj_addr(ring, n); 303 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_TX) 304 mcp251xfd_spi_cmd_write_crc_set_addr(&tx_obj->buf.crc.cmd, 305 addr); 306 else 307 mcp251xfd_spi_cmd_write_nocrc(&tx_obj->buf.nocrc.cmd, 308 addr); 309 310 xfer = &tx_obj->xfer[0]; 311 xfer->tx_buf = &tx_obj->buf; 312 xfer->len = 0; /* actual len is assigned on the fly */ 313 xfer->cs_change = 1; 314 xfer->cs_change_delay.value = 0; 315 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 316 317 /* FIFO request to send */ 318 xfer = &tx_obj->xfer[1]; 319 xfer->tx_buf = &ring->rts_buf; 320 xfer->len = rts_buf_len; 321 322 /* SPI message */ 323 spi_message_init_with_transfers(&tx_obj->msg, tx_obj->xfer, 324 ARRAY_SIZE(tx_obj->xfer)); 325 } 326 327 static void mcp251xfd_ring_init(struct mcp251xfd_priv *priv) 328 { 329 struct mcp251xfd_tef_ring *tef_ring; 330 struct mcp251xfd_tx_ring *tx_ring; 331 struct mcp251xfd_rx_ring *rx_ring, *prev_rx_ring = NULL; 332 struct mcp251xfd_tx_obj *tx_obj; 333 u32 val; 334 u16 addr; 335 u8 len; 336 int i, j; 337 338 /* TEF */ 339 tef_ring = priv->tef; 340 tef_ring->head = 0; 341 tef_ring->tail = 0; 342 343 /* FIFO increment TEF tail pointer */ 344 addr = MCP251XFD_REG_TEFCON; 345 val = MCP251XFD_REG_TEFCON_UINC; 346 len = mcp251xfd_cmd_prepare_write_reg(priv, &tef_ring->uinc_buf, 347 addr, val, val); 348 349 for (j = 0; j < ARRAY_SIZE(tef_ring->uinc_xfer); j++) { 350 struct spi_transfer *xfer; 351 352 xfer = &tef_ring->uinc_xfer[j]; 353 xfer->tx_buf = &tef_ring->uinc_buf; 354 xfer->len = len; 355 xfer->cs_change = 1; 356 xfer->cs_change_delay.value = 0; 357 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 358 } 359 360 /* TX */ 361 tx_ring = priv->tx; 362 tx_ring->head = 0; 363 tx_ring->tail = 0; 364 tx_ring->base = mcp251xfd_get_tef_obj_addr(tx_ring->obj_num); 365 366 /* FIFO request to send */ 367 addr = MCP251XFD_REG_FIFOCON(MCP251XFD_TX_FIFO); 368 val = MCP251XFD_REG_FIFOCON_TXREQ | MCP251XFD_REG_FIFOCON_UINC; 369 len = mcp251xfd_cmd_prepare_write_reg(priv, &tx_ring->rts_buf, 370 addr, val, val); 371 372 mcp251xfd_for_each_tx_obj(tx_ring, tx_obj, i) 373 mcp251xfd_tx_ring_init_tx_obj(priv, tx_ring, tx_obj, len, i); 374 375 /* RX */ 376 mcp251xfd_for_each_rx_ring(priv, rx_ring, i) { 377 rx_ring->head = 0; 378 rx_ring->tail = 0; 379 rx_ring->nr = i; 380 rx_ring->fifo_nr = MCP251XFD_RX_FIFO(i); 381 382 if (!prev_rx_ring) 383 rx_ring->base = 384 mcp251xfd_get_tx_obj_addr(tx_ring, 385 tx_ring->obj_num); 386 else 387 rx_ring->base = prev_rx_ring->base + 388 prev_rx_ring->obj_size * 389 prev_rx_ring->obj_num; 390 391 prev_rx_ring = rx_ring; 392 393 /* FIFO increment RX tail pointer */ 394 addr = MCP251XFD_REG_FIFOCON(rx_ring->fifo_nr); 395 val = MCP251XFD_REG_FIFOCON_UINC; 396 len = mcp251xfd_cmd_prepare_write_reg(priv, &rx_ring->uinc_buf, 397 addr, val, val); 398 399 for (j = 0; j < ARRAY_SIZE(rx_ring->uinc_xfer); j++) { 400 struct spi_transfer *xfer; 401 402 xfer = &rx_ring->uinc_xfer[j]; 403 xfer->tx_buf = &rx_ring->uinc_buf; 404 xfer->len = len; 405 xfer->cs_change = 1; 406 xfer->cs_change_delay.value = 0; 407 xfer->cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 408 } 409 } 410 } 411 412 static void mcp251xfd_ring_free(struct mcp251xfd_priv *priv) 413 { 414 int i; 415 416 for (i = ARRAY_SIZE(priv->rx) - 1; i >= 0; i--) { 417 kfree(priv->rx[i]); 418 priv->rx[i] = NULL; 419 } 420 } 421 422 static int mcp251xfd_ring_alloc(struct mcp251xfd_priv *priv) 423 { 424 struct mcp251xfd_tx_ring *tx_ring; 425 struct mcp251xfd_rx_ring *rx_ring; 426 int tef_obj_size, tx_obj_size, rx_obj_size; 427 int tx_obj_num; 428 int ram_free, i; 429 430 tef_obj_size = sizeof(struct mcp251xfd_hw_tef_obj); 431 /* listen-only mode works like FD mode */ 432 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_FD)) { 433 tx_obj_num = MCP251XFD_TX_OBJ_NUM_CANFD; 434 tx_obj_size = sizeof(struct mcp251xfd_hw_tx_obj_canfd); 435 rx_obj_size = sizeof(struct mcp251xfd_hw_rx_obj_canfd); 436 } else { 437 tx_obj_num = MCP251XFD_TX_OBJ_NUM_CAN; 438 tx_obj_size = sizeof(struct mcp251xfd_hw_tx_obj_can); 439 rx_obj_size = sizeof(struct mcp251xfd_hw_rx_obj_can); 440 } 441 442 tx_ring = priv->tx; 443 tx_ring->obj_num = tx_obj_num; 444 tx_ring->obj_size = tx_obj_size; 445 446 ram_free = MCP251XFD_RAM_SIZE - tx_obj_num * 447 (tef_obj_size + tx_obj_size); 448 449 for (i = 0; 450 i < ARRAY_SIZE(priv->rx) && ram_free >= rx_obj_size; 451 i++) { 452 int rx_obj_num; 453 454 rx_obj_num = ram_free / rx_obj_size; 455 rx_obj_num = min(1 << (fls(rx_obj_num) - 1), 456 MCP251XFD_RX_OBJ_NUM_MAX); 457 458 rx_ring = kzalloc(sizeof(*rx_ring) + rx_obj_size * rx_obj_num, 459 GFP_KERNEL); 460 if (!rx_ring) { 461 mcp251xfd_ring_free(priv); 462 return -ENOMEM; 463 } 464 rx_ring->obj_num = rx_obj_num; 465 rx_ring->obj_size = rx_obj_size; 466 priv->rx[i] = rx_ring; 467 468 ram_free -= rx_ring->obj_num * rx_ring->obj_size; 469 } 470 priv->rx_ring_num = i; 471 472 netdev_dbg(priv->ndev, 473 "FIFO setup: TEF: %d*%d bytes = %d bytes, TX: %d*%d bytes = %d bytes\n", 474 tx_obj_num, tef_obj_size, tef_obj_size * tx_obj_num, 475 tx_obj_num, tx_obj_size, tx_obj_size * tx_obj_num); 476 477 mcp251xfd_for_each_rx_ring(priv, rx_ring, i) { 478 netdev_dbg(priv->ndev, 479 "FIFO setup: RX-%d: %d*%d bytes = %d bytes\n", 480 i, rx_ring->obj_num, rx_ring->obj_size, 481 rx_ring->obj_size * rx_ring->obj_num); 482 } 483 484 netdev_dbg(priv->ndev, 485 "FIFO setup: free: %d bytes\n", 486 ram_free); 487 488 return 0; 489 } 490 491 static inline int 492 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode) 493 { 494 u32 val; 495 int err; 496 497 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val); 498 if (err) 499 return err; 500 501 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val); 502 503 return 0; 504 } 505 506 static int 507 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 508 const u8 mode_req, bool nowait) 509 { 510 u32 con, con_reqop; 511 int err; 512 513 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req); 514 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON, 515 MCP251XFD_REG_CON_REQOP_MASK, con_reqop); 516 if (err) 517 return err; 518 519 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait) 520 return 0; 521 522 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con, 523 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, 524 con) == mode_req, 525 MCP251XFD_POLL_SLEEP_US, 526 MCP251XFD_POLL_TIMEOUT_US); 527 if (err) { 528 u8 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con); 529 530 netdev_err(priv->ndev, 531 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u).\n", 532 mcp251xfd_get_mode_str(mode_req), mode_req, 533 mcp251xfd_get_mode_str(mode), mode); 534 return err; 535 } 536 537 return 0; 538 } 539 540 static inline int 541 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 542 const u8 mode_req) 543 { 544 return __mcp251xfd_chip_set_mode(priv, mode_req, false); 545 } 546 547 static inline int 548 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, 549 const u8 mode_req) 550 { 551 return __mcp251xfd_chip_set_mode(priv, mode_req, true); 552 } 553 554 static inline bool mcp251xfd_osc_invalid(u32 reg) 555 { 556 return reg == 0x0 || reg == 0xffffffff; 557 } 558 559 static int mcp251xfd_chip_clock_enable(const struct mcp251xfd_priv *priv) 560 { 561 u32 osc, osc_reference, osc_mask; 562 int err; 563 564 /* Set Power On Defaults for "Clock Output Divisor" and remove 565 * "Oscillator Disable" bit. 566 */ 567 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 568 MCP251XFD_REG_OSC_CLKODIV_10); 569 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 570 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY; 571 572 /* Note: 573 * 574 * If the controller is in Sleep Mode the following write only 575 * removes the "Oscillator Disable" bit and powers it up. All 576 * other bits are unaffected. 577 */ 578 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 579 if (err) 580 return err; 581 582 /* Wait for "Oscillator Ready" bit */ 583 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc, 584 (osc & osc_mask) == osc_reference, 585 MCP251XFD_OSC_STAB_SLEEP_US, 586 MCP251XFD_OSC_STAB_TIMEOUT_US); 587 if (mcp251xfd_osc_invalid(osc)) { 588 netdev_err(priv->ndev, 589 "Failed to detect %s (osc=0x%08x).\n", 590 mcp251xfd_get_model_str(priv), osc); 591 return -ENODEV; 592 } else if (err == -ETIMEDOUT) { 593 netdev_err(priv->ndev, 594 "Timeout waiting for Oscillator Ready (osc=0x%08x, osc_reference=0x%08x)\n", 595 osc, osc_reference); 596 return -ETIMEDOUT; 597 } else if (err) { 598 return err; 599 } 600 601 return 0; 602 } 603 604 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv) 605 { 606 const __be16 cmd = mcp251xfd_cmd_reset(); 607 int err; 608 609 /* The Set Mode and SPI Reset command only seems to works if 610 * the controller is not in Sleep Mode. 611 */ 612 err = mcp251xfd_chip_clock_enable(priv); 613 if (err) 614 return err; 615 616 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); 617 if (err) 618 return err; 619 620 /* spi_write_then_read() works with non DMA-safe buffers */ 621 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); 622 } 623 624 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv) 625 { 626 u32 osc, osc_reference; 627 u8 mode; 628 int err; 629 630 err = mcp251xfd_chip_get_mode(priv, &mode); 631 if (err) 632 return err; 633 634 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) { 635 netdev_info(priv->ndev, 636 "Controller not in Config Mode after reset, but in %s Mode (%u).\n", 637 mcp251xfd_get_mode_str(mode), mode); 638 return -ETIMEDOUT; 639 } 640 641 osc_reference = MCP251XFD_REG_OSC_OSCRDY | 642 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 643 MCP251XFD_REG_OSC_CLKODIV_10); 644 645 /* check reset defaults of OSC reg */ 646 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 647 if (err) 648 return err; 649 650 if (osc != osc_reference) { 651 netdev_info(priv->ndev, 652 "Controller failed to reset. osc=0x%08x, reference value=0x%08x\n", 653 osc, osc_reference); 654 return -ETIMEDOUT; 655 } 656 657 return 0; 658 } 659 660 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv) 661 { 662 int err, i; 663 664 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) { 665 if (i) 666 netdev_info(priv->ndev, 667 "Retrying to reset Controller.\n"); 668 669 err = mcp251xfd_chip_softreset_do(priv); 670 if (err == -ETIMEDOUT) 671 continue; 672 if (err) 673 return err; 674 675 err = mcp251xfd_chip_softreset_check(priv); 676 if (err == -ETIMEDOUT) 677 continue; 678 if (err) 679 return err; 680 681 return 0; 682 } 683 684 return err; 685 } 686 687 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv) 688 { 689 u32 osc; 690 int err; 691 692 /* Activate Low Power Mode on Oscillator Disable. This only 693 * works on the MCP2518FD. The MCP2517FD will go into normal 694 * Sleep Mode instead. 695 */ 696 osc = MCP251XFD_REG_OSC_LPMEN | 697 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 698 MCP251XFD_REG_OSC_CLKODIV_10); 699 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 700 if (err) 701 return err; 702 703 /* Set Time Base Counter Prescaler to 1. 704 * 705 * This means an overflow of the 32 bit Time Base Counter 706 * register at 40 MHz every 107 seconds. 707 */ 708 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON, 709 MCP251XFD_REG_TSCON_TBCEN); 710 } 711 712 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv) 713 { 714 const struct can_bittiming *bt = &priv->can.bittiming; 715 const struct can_bittiming *dbt = &priv->can.data_bittiming; 716 u32 val = 0; 717 s8 tdco; 718 int err; 719 720 /* CAN Control Register 721 * 722 * - no transmit bandwidth sharing 723 * - config mode 724 * - disable transmit queue 725 * - store in transmit FIFO event 726 * - transition to restricted operation mode on system error 727 * - ESI is transmitted recessive when ESI of message is high or 728 * CAN controller error passive 729 * - restricted retransmission attempts, 730 * use TQXCON_TXAT and FIFOCON_TXAT 731 * - wake-up filter bits T11FILTER 732 * - use CAN bus line filter for wakeup 733 * - protocol exception is treated as a form error 734 * - Do not compare data bytes 735 */ 736 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, 737 MCP251XFD_REG_CON_MODE_CONFIG) | 738 MCP251XFD_REG_CON_STEF | 739 MCP251XFD_REG_CON_ESIGM | 740 MCP251XFD_REG_CON_RTXAT | 741 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK, 742 MCP251XFD_REG_CON_WFT_T11FILTER) | 743 MCP251XFD_REG_CON_WAKFIL | 744 MCP251XFD_REG_CON_PXEDIS; 745 746 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 747 val |= MCP251XFD_REG_CON_ISOCRCEN; 748 749 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val); 750 if (err) 751 return err; 752 753 /* Nominal Bit Time */ 754 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) | 755 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK, 756 bt->prop_seg + bt->phase_seg1 - 1) | 757 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK, 758 bt->phase_seg2 - 1) | 759 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1); 760 761 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val); 762 if (err) 763 return err; 764 765 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) 766 return 0; 767 768 /* Data Bit Time */ 769 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) | 770 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK, 771 dbt->prop_seg + dbt->phase_seg1 - 1) | 772 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK, 773 dbt->phase_seg2 - 1) | 774 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1); 775 776 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val); 777 if (err) 778 return err; 779 780 /* Transmitter Delay Compensation */ 781 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1), 782 -64, 63); 783 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, 784 MCP251XFD_REG_TDC_TDCMOD_AUTO) | 785 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco); 786 787 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val); 788 } 789 790 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) 791 { 792 u32 val; 793 794 if (!priv->rx_int) 795 return 0; 796 797 /* Configure GPIOs: 798 * - PIN0: GPIO Input 799 * - PIN1: GPIO Input/RX Interrupt 800 * 801 * PIN1 must be Input, otherwise there is a glitch on the 802 * rx-INT line. It happens between setting the PIN as output 803 * (in the first byte of the SPI transfer) and configuring the 804 * PIN as interrupt (in the last byte of the SPI transfer). 805 */ 806 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | 807 MCP251XFD_REG_IOCON_TRIS0; 808 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 809 } 810 811 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) 812 { 813 u32 val; 814 815 if (!priv->rx_int) 816 return 0; 817 818 /* Configure GPIOs: 819 * - PIN0: GPIO Input 820 * - PIN1: GPIO Input 821 */ 822 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | 823 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; 824 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 825 } 826 827 static int 828 mcp251xfd_chip_rx_fifo_init_one(const struct mcp251xfd_priv *priv, 829 const struct mcp251xfd_rx_ring *ring) 830 { 831 u32 fifo_con; 832 833 /* Enable RXOVIE on _all_ RX FIFOs, not just the last one. 834 * 835 * FIFOs hit by a RX MAB overflow and RXOVIE enabled will 836 * generate a RXOVIF, use this to properly detect RX MAB 837 * overflows. 838 */ 839 fifo_con = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK, 840 ring->obj_num - 1) | 841 MCP251XFD_REG_FIFOCON_RXTSEN | 842 MCP251XFD_REG_FIFOCON_RXOVIE | 843 MCP251XFD_REG_FIFOCON_TFNRFNIE; 844 845 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_FD)) 846 fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 847 MCP251XFD_REG_FIFOCON_PLSIZE_64); 848 else 849 fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 850 MCP251XFD_REG_FIFOCON_PLSIZE_8); 851 852 return regmap_write(priv->map_reg, 853 MCP251XFD_REG_FIFOCON(ring->fifo_nr), fifo_con); 854 } 855 856 static int 857 mcp251xfd_chip_rx_filter_init_one(const struct mcp251xfd_priv *priv, 858 const struct mcp251xfd_rx_ring *ring) 859 { 860 u32 fltcon; 861 862 fltcon = MCP251XFD_REG_FLTCON_FLTEN(ring->nr) | 863 MCP251XFD_REG_FLTCON_FBP(ring->nr, ring->fifo_nr); 864 865 return regmap_update_bits(priv->map_reg, 866 MCP251XFD_REG_FLTCON(ring->nr >> 2), 867 MCP251XFD_REG_FLTCON_FLT_MASK(ring->nr), 868 fltcon); 869 } 870 871 static int mcp251xfd_chip_fifo_init(const struct mcp251xfd_priv *priv) 872 { 873 const struct mcp251xfd_tx_ring *tx_ring = priv->tx; 874 const struct mcp251xfd_rx_ring *rx_ring; 875 u32 val; 876 int err, n; 877 878 /* TEF */ 879 val = FIELD_PREP(MCP251XFD_REG_TEFCON_FSIZE_MASK, 880 tx_ring->obj_num - 1) | 881 MCP251XFD_REG_TEFCON_TEFTSEN | 882 MCP251XFD_REG_TEFCON_TEFOVIE | 883 MCP251XFD_REG_TEFCON_TEFNEIE; 884 885 err = regmap_write(priv->map_reg, MCP251XFD_REG_TEFCON, val); 886 if (err) 887 return err; 888 889 /* FIFO 1 - TX */ 890 val = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK, 891 tx_ring->obj_num - 1) | 892 MCP251XFD_REG_FIFOCON_TXEN | 893 MCP251XFD_REG_FIFOCON_TXATIE; 894 895 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_FD)) 896 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 897 MCP251XFD_REG_FIFOCON_PLSIZE_64); 898 else 899 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 900 MCP251XFD_REG_FIFOCON_PLSIZE_8); 901 902 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) 903 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK, 904 MCP251XFD_REG_FIFOCON_TXAT_ONE_SHOT); 905 else 906 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK, 907 MCP251XFD_REG_FIFOCON_TXAT_UNLIMITED); 908 909 err = regmap_write(priv->map_reg, 910 MCP251XFD_REG_FIFOCON(MCP251XFD_TX_FIFO), 911 val); 912 if (err) 913 return err; 914 915 /* RX FIFOs */ 916 mcp251xfd_for_each_rx_ring(priv, rx_ring, n) { 917 err = mcp251xfd_chip_rx_fifo_init_one(priv, rx_ring); 918 if (err) 919 return err; 920 921 err = mcp251xfd_chip_rx_filter_init_one(priv, rx_ring); 922 if (err) 923 return err; 924 } 925 926 return 0; 927 } 928 929 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) 930 { 931 struct mcp251xfd_ecc *ecc = &priv->ecc; 932 void *ram; 933 u32 val = 0; 934 int err; 935 936 ecc->ecc_stat = 0; 937 938 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC) 939 val = MCP251XFD_REG_ECCCON_ECCEN; 940 941 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 942 MCP251XFD_REG_ECCCON_ECCEN, val); 943 if (err) 944 return err; 945 946 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL); 947 if (!ram) 948 return -ENOMEM; 949 950 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram, 951 MCP251XFD_RAM_SIZE); 952 kfree(ram); 953 954 return err; 955 } 956 957 static inline void mcp251xfd_ecc_tefif_successful(struct mcp251xfd_priv *priv) 958 { 959 struct mcp251xfd_ecc *ecc = &priv->ecc; 960 961 ecc->ecc_stat = 0; 962 } 963 964 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv) 965 { 966 u8 mode; 967 968 969 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 970 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK; 971 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 972 mode = MCP251XFD_REG_CON_MODE_LISTENONLY; 973 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 974 mode = MCP251XFD_REG_CON_MODE_MIXED; 975 else 976 mode = MCP251XFD_REG_CON_MODE_CAN2_0; 977 978 return mode; 979 } 980 981 static int 982 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv, 983 bool nowait) 984 { 985 u8 mode; 986 987 mode = mcp251xfd_get_normal_mode(priv); 988 989 return __mcp251xfd_chip_set_mode(priv, mode, nowait); 990 } 991 992 static inline int 993 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv) 994 { 995 return __mcp251xfd_chip_set_normal_mode(priv, false); 996 } 997 998 static inline int 999 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv) 1000 { 1001 return __mcp251xfd_chip_set_normal_mode(priv, true); 1002 } 1003 1004 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv) 1005 { 1006 u32 val; 1007 int err; 1008 1009 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE; 1010 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val); 1011 if (err) 1012 return err; 1013 1014 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 1015 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val); 1016 if (err) 1017 return err; 1018 1019 val = MCP251XFD_REG_INT_CERRIE | 1020 MCP251XFD_REG_INT_SERRIE | 1021 MCP251XFD_REG_INT_RXOVIE | 1022 MCP251XFD_REG_INT_TXATIE | 1023 MCP251XFD_REG_INT_SPICRCIE | 1024 MCP251XFD_REG_INT_ECCIE | 1025 MCP251XFD_REG_INT_TEFIE | 1026 MCP251XFD_REG_INT_MODIE | 1027 MCP251XFD_REG_INT_RXIE; 1028 1029 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 1030 val |= MCP251XFD_REG_INT_IVMIE; 1031 1032 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val); 1033 } 1034 1035 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv) 1036 { 1037 int err; 1038 u32 mask; 1039 1040 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0); 1041 if (err) 1042 return err; 1043 1044 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 1045 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 1046 mask, 0x0); 1047 if (err) 1048 return err; 1049 1050 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0); 1051 } 1052 1053 static int mcp251xfd_chip_stop(struct mcp251xfd_priv *priv, 1054 const enum can_state state) 1055 { 1056 priv->can.state = state; 1057 1058 mcp251xfd_chip_interrupts_disable(priv); 1059 mcp251xfd_chip_rx_int_disable(priv); 1060 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 1061 } 1062 1063 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) 1064 { 1065 int err; 1066 1067 err = mcp251xfd_chip_softreset(priv); 1068 if (err) 1069 goto out_chip_stop; 1070 1071 err = mcp251xfd_chip_clock_init(priv); 1072 if (err) 1073 goto out_chip_stop; 1074 1075 err = mcp251xfd_set_bittiming(priv); 1076 if (err) 1077 goto out_chip_stop; 1078 1079 err = mcp251xfd_chip_rx_int_enable(priv); 1080 if (err) 1081 return err; 1082 1083 err = mcp251xfd_chip_ecc_init(priv); 1084 if (err) 1085 goto out_chip_stop; 1086 1087 mcp251xfd_ring_init(priv); 1088 1089 err = mcp251xfd_chip_fifo_init(priv); 1090 if (err) 1091 goto out_chip_stop; 1092 1093 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1094 1095 err = mcp251xfd_chip_set_normal_mode(priv); 1096 if (err) 1097 goto out_chip_stop; 1098 1099 return 0; 1100 1101 out_chip_stop: 1102 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1103 1104 return err; 1105 } 1106 1107 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode) 1108 { 1109 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1110 int err; 1111 1112 switch (mode) { 1113 case CAN_MODE_START: 1114 err = mcp251xfd_chip_start(priv); 1115 if (err) 1116 return err; 1117 1118 err = mcp251xfd_chip_interrupts_enable(priv); 1119 if (err) { 1120 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1121 return err; 1122 } 1123 1124 netif_wake_queue(ndev); 1125 break; 1126 1127 default: 1128 return -EOPNOTSUPP; 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev, 1135 struct can_berr_counter *bec) 1136 { 1137 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 1138 u32 trec; 1139 int err; 1140 1141 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 1142 if (err) 1143 return err; 1144 1145 if (trec & MCP251XFD_REG_TREC_TXBO) 1146 bec->txerr = 256; 1147 else 1148 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec); 1149 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec); 1150 1151 return 0; 1152 } 1153 1154 static int mcp251xfd_get_berr_counter(const struct net_device *ndev, 1155 struct can_berr_counter *bec) 1156 { 1157 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 1158 1159 /* Avoid waking up the controller if the interface is down */ 1160 if (!(ndev->flags & IFF_UP)) 1161 return 0; 1162 1163 /* The controller is powered down during Bus Off, use saved 1164 * bec values. 1165 */ 1166 if (priv->can.state == CAN_STATE_BUS_OFF) { 1167 *bec = priv->bec; 1168 return 0; 1169 } 1170 1171 return __mcp251xfd_get_berr_counter(ndev, bec); 1172 } 1173 1174 static int mcp251xfd_check_tef_tail(const struct mcp251xfd_priv *priv) 1175 { 1176 u8 tef_tail_chip, tef_tail; 1177 int err; 1178 1179 if (!IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY)) 1180 return 0; 1181 1182 err = mcp251xfd_tef_tail_get_from_chip(priv, &tef_tail_chip); 1183 if (err) 1184 return err; 1185 1186 tef_tail = mcp251xfd_get_tef_tail(priv); 1187 if (tef_tail_chip != tef_tail) { 1188 netdev_err(priv->ndev, 1189 "TEF tail of chip (0x%02x) and ours (0x%08x) inconsistent.\n", 1190 tef_tail_chip, tef_tail); 1191 return -EILSEQ; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int 1198 mcp251xfd_check_rx_tail(const struct mcp251xfd_priv *priv, 1199 const struct mcp251xfd_rx_ring *ring) 1200 { 1201 u8 rx_tail_chip, rx_tail; 1202 int err; 1203 1204 if (!IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY)) 1205 return 0; 1206 1207 err = mcp251xfd_rx_tail_get_from_chip(priv, ring, &rx_tail_chip); 1208 if (err) 1209 return err; 1210 1211 rx_tail = mcp251xfd_get_rx_tail(ring); 1212 if (rx_tail_chip != rx_tail) { 1213 netdev_err(priv->ndev, 1214 "RX tail of chip (%d) and ours (%d) inconsistent.\n", 1215 rx_tail_chip, rx_tail); 1216 return -EILSEQ; 1217 } 1218 1219 return 0; 1220 } 1221 1222 static int 1223 mcp251xfd_handle_tefif_recover(const struct mcp251xfd_priv *priv, const u32 seq) 1224 { 1225 const struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1226 u32 tef_sta; 1227 int err; 1228 1229 err = regmap_read(priv->map_reg, MCP251XFD_REG_TEFSTA, &tef_sta); 1230 if (err) 1231 return err; 1232 1233 if (tef_sta & MCP251XFD_REG_TEFSTA_TEFOVIF) { 1234 netdev_err(priv->ndev, 1235 "Transmit Event FIFO buffer overflow.\n"); 1236 return -ENOBUFS; 1237 } 1238 1239 netdev_info(priv->ndev, 1240 "Transmit Event FIFO buffer %s. (seq=0x%08x, tef_tail=0x%08x, tef_head=0x%08x, tx_head=0x%08x)\n", 1241 tef_sta & MCP251XFD_REG_TEFSTA_TEFFIF ? 1242 "full" : tef_sta & MCP251XFD_REG_TEFSTA_TEFNEIF ? 1243 "not empty" : "empty", 1244 seq, priv->tef->tail, priv->tef->head, tx_ring->head); 1245 1246 /* The Sequence Number in the TEF doesn't match our tef_tail. */ 1247 return -EAGAIN; 1248 } 1249 1250 static int 1251 mcp251xfd_handle_tefif_one(struct mcp251xfd_priv *priv, 1252 const struct mcp251xfd_hw_tef_obj *hw_tef_obj) 1253 { 1254 struct net_device_stats *stats = &priv->ndev->stats; 1255 u32 seq, seq_masked, tef_tail_masked; 1256 1257 seq = FIELD_GET(MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK, 1258 hw_tef_obj->flags); 1259 1260 /* Use the MCP2517FD mask on the MCP2518FD, too. We only 1261 * compare 7 bits, this should be enough to detect 1262 * net-yet-completed, i.e. old TEF objects. 1263 */ 1264 seq_masked = seq & 1265 field_mask(MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK); 1266 tef_tail_masked = priv->tef->tail & 1267 field_mask(MCP251XFD_OBJ_FLAGS_SEQ_MCP2517FD_MASK); 1268 if (seq_masked != tef_tail_masked) 1269 return mcp251xfd_handle_tefif_recover(priv, seq); 1270 1271 stats->tx_bytes += 1272 can_rx_offload_get_echo_skb(&priv->offload, 1273 mcp251xfd_get_tef_tail(priv), 1274 hw_tef_obj->ts); 1275 stats->tx_packets++; 1276 priv->tef->tail++; 1277 1278 return 0; 1279 } 1280 1281 static int mcp251xfd_tef_ring_update(struct mcp251xfd_priv *priv) 1282 { 1283 const struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1284 unsigned int new_head; 1285 u8 chip_tx_tail; 1286 int err; 1287 1288 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail); 1289 if (err) 1290 return err; 1291 1292 /* chip_tx_tail, is the next TX-Object send by the HW. 1293 * The new TEF head must be >= the old head, ... 1294 */ 1295 new_head = round_down(priv->tef->head, tx_ring->obj_num) + chip_tx_tail; 1296 if (new_head <= priv->tef->head) 1297 new_head += tx_ring->obj_num; 1298 1299 /* ... but it cannot exceed the TX head. */ 1300 priv->tef->head = min(new_head, tx_ring->head); 1301 1302 return mcp251xfd_check_tef_tail(priv); 1303 } 1304 1305 static inline int 1306 mcp251xfd_tef_obj_read(const struct mcp251xfd_priv *priv, 1307 struct mcp251xfd_hw_tef_obj *hw_tef_obj, 1308 const u8 offset, const u8 len) 1309 { 1310 const struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1311 1312 if (IS_ENABLED(CONFIG_CAN_MCP251XFD_SANITY) && 1313 (offset > tx_ring->obj_num || 1314 len > tx_ring->obj_num || 1315 offset + len > tx_ring->obj_num)) { 1316 netdev_err(priv->ndev, 1317 "Trying to read to many TEF objects (max=%d, offset=%d, len=%d).\n", 1318 tx_ring->obj_num, offset, len); 1319 return -ERANGE; 1320 } 1321 1322 return regmap_bulk_read(priv->map_rx, 1323 mcp251xfd_get_tef_obj_addr(offset), 1324 hw_tef_obj, 1325 sizeof(*hw_tef_obj) / sizeof(u32) * len); 1326 } 1327 1328 static int mcp251xfd_handle_tefif(struct mcp251xfd_priv *priv) 1329 { 1330 struct mcp251xfd_hw_tef_obj hw_tef_obj[MCP251XFD_TX_OBJ_NUM_MAX]; 1331 u8 tef_tail, len, l; 1332 int err, i; 1333 1334 err = mcp251xfd_tef_ring_update(priv); 1335 if (err) 1336 return err; 1337 1338 tef_tail = mcp251xfd_get_tef_tail(priv); 1339 len = mcp251xfd_get_tef_len(priv); 1340 l = mcp251xfd_get_tef_linear_len(priv); 1341 err = mcp251xfd_tef_obj_read(priv, hw_tef_obj, tef_tail, l); 1342 if (err) 1343 return err; 1344 1345 if (l < len) { 1346 err = mcp251xfd_tef_obj_read(priv, &hw_tef_obj[l], 0, len - l); 1347 if (err) 1348 return err; 1349 } 1350 1351 for (i = 0; i < len; i++) { 1352 err = mcp251xfd_handle_tefif_one(priv, &hw_tef_obj[i]); 1353 /* -EAGAIN means the Sequence Number in the TEF 1354 * doesn't match our tef_tail. This can happen if we 1355 * read the TEF objects too early. Leave loop let the 1356 * interrupt handler call us again. 1357 */ 1358 if (err == -EAGAIN) 1359 goto out_netif_wake_queue; 1360 if (err) 1361 return err; 1362 } 1363 1364 out_netif_wake_queue: 1365 len = i; /* number of handled goods TEFs */ 1366 if (len) { 1367 struct mcp251xfd_tef_ring *ring = priv->tef; 1368 struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1369 struct spi_transfer *last_xfer; 1370 1371 tx_ring->tail += len; 1372 1373 /* Increment the TEF FIFO tail pointer 'len' times in 1374 * a single SPI message. 1375 */ 1376 1377 /* Note: 1378 * 1379 * "cs_change == 1" on the last transfer results in an 1380 * active chip select after the complete SPI 1381 * message. This causes the controller to interpret 1382 * the next register access as data. Temporary set 1383 * "cs_change" of the last transfer to "0" to properly 1384 * deactivate the chip select at the end of the 1385 * message. 1386 */ 1387 last_xfer = &ring->uinc_xfer[len - 1]; 1388 last_xfer->cs_change = 0; 1389 err = spi_sync_transfer(priv->spi, ring->uinc_xfer, len); 1390 last_xfer->cs_change = 1; 1391 if (err) 1392 return err; 1393 1394 err = mcp251xfd_check_tef_tail(priv); 1395 if (err) 1396 return err; 1397 } 1398 1399 mcp251xfd_ecc_tefif_successful(priv); 1400 1401 if (mcp251xfd_get_tx_free(priv->tx)) { 1402 /* Make sure that anybody stopping the queue after 1403 * this sees the new tx_ring->tail. 1404 */ 1405 smp_mb(); 1406 netif_wake_queue(priv->ndev); 1407 } 1408 1409 return 0; 1410 } 1411 1412 static int 1413 mcp251xfd_rx_ring_update(const struct mcp251xfd_priv *priv, 1414 struct mcp251xfd_rx_ring *ring) 1415 { 1416 u32 new_head; 1417 u8 chip_rx_head; 1418 int err; 1419 1420 err = mcp251xfd_rx_head_get_from_chip(priv, ring, &chip_rx_head); 1421 if (err) 1422 return err; 1423 1424 /* chip_rx_head, is the next RX-Object filled by the HW. 1425 * The new RX head must be >= the old head. 1426 */ 1427 new_head = round_down(ring->head, ring->obj_num) + chip_rx_head; 1428 if (new_head <= ring->head) 1429 new_head += ring->obj_num; 1430 1431 ring->head = new_head; 1432 1433 return mcp251xfd_check_rx_tail(priv, ring); 1434 } 1435 1436 static void 1437 mcp251xfd_hw_rx_obj_to_skb(const struct mcp251xfd_priv *priv, 1438 const struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj, 1439 struct sk_buff *skb) 1440 { 1441 struct canfd_frame *cfd = (struct canfd_frame *)skb->data; 1442 1443 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_IDE) { 1444 u32 sid, eid; 1445 1446 eid = FIELD_GET(MCP251XFD_OBJ_ID_EID_MASK, hw_rx_obj->id); 1447 sid = FIELD_GET(MCP251XFD_OBJ_ID_SID_MASK, hw_rx_obj->id); 1448 1449 cfd->can_id = CAN_EFF_FLAG | 1450 FIELD_PREP(MCP251XFD_REG_FRAME_EFF_EID_MASK, eid) | 1451 FIELD_PREP(MCP251XFD_REG_FRAME_EFF_SID_MASK, sid); 1452 } else { 1453 cfd->can_id = FIELD_GET(MCP251XFD_OBJ_ID_SID_MASK, 1454 hw_rx_obj->id); 1455 } 1456 1457 /* CANFD */ 1458 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_FDF) { 1459 u8 dlc; 1460 1461 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_ESI) 1462 cfd->flags |= CANFD_ESI; 1463 1464 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_BRS) 1465 cfd->flags |= CANFD_BRS; 1466 1467 dlc = FIELD_GET(MCP251XFD_OBJ_FLAGS_DLC, hw_rx_obj->flags); 1468 cfd->len = can_fd_dlc2len(dlc); 1469 } else { 1470 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_RTR) 1471 cfd->can_id |= CAN_RTR_FLAG; 1472 1473 cfd->len = can_cc_dlc2len(FIELD_GET(MCP251XFD_OBJ_FLAGS_DLC, 1474 hw_rx_obj->flags)); 1475 } 1476 1477 memcpy(cfd->data, hw_rx_obj->data, cfd->len); 1478 } 1479 1480 static int 1481 mcp251xfd_handle_rxif_one(struct mcp251xfd_priv *priv, 1482 struct mcp251xfd_rx_ring *ring, 1483 const struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj) 1484 { 1485 struct net_device_stats *stats = &priv->ndev->stats; 1486 struct sk_buff *skb; 1487 struct canfd_frame *cfd; 1488 int err; 1489 1490 if (hw_rx_obj->flags & MCP251XFD_OBJ_FLAGS_FDF) 1491 skb = alloc_canfd_skb(priv->ndev, &cfd); 1492 else 1493 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cfd); 1494 1495 if (!cfd) { 1496 stats->rx_dropped++; 1497 return 0; 1498 } 1499 1500 mcp251xfd_hw_rx_obj_to_skb(priv, hw_rx_obj, skb); 1501 err = can_rx_offload_queue_sorted(&priv->offload, skb, hw_rx_obj->ts); 1502 if (err) 1503 stats->rx_fifo_errors++; 1504 1505 return 0; 1506 } 1507 1508 static inline int 1509 mcp251xfd_rx_obj_read(const struct mcp251xfd_priv *priv, 1510 const struct mcp251xfd_rx_ring *ring, 1511 struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj, 1512 const u8 offset, const u8 len) 1513 { 1514 int err; 1515 1516 err = regmap_bulk_read(priv->map_rx, 1517 mcp251xfd_get_rx_obj_addr(ring, offset), 1518 hw_rx_obj, 1519 len * ring->obj_size / sizeof(u32)); 1520 1521 return err; 1522 } 1523 1524 static int 1525 mcp251xfd_handle_rxif_ring(struct mcp251xfd_priv *priv, 1526 struct mcp251xfd_rx_ring *ring) 1527 { 1528 struct mcp251xfd_hw_rx_obj_canfd *hw_rx_obj = ring->obj; 1529 u8 rx_tail, len; 1530 int err, i; 1531 1532 err = mcp251xfd_rx_ring_update(priv, ring); 1533 if (err) 1534 return err; 1535 1536 while ((len = mcp251xfd_get_rx_linear_len(ring))) { 1537 struct spi_transfer *last_xfer; 1538 1539 rx_tail = mcp251xfd_get_rx_tail(ring); 1540 1541 err = mcp251xfd_rx_obj_read(priv, ring, hw_rx_obj, 1542 rx_tail, len); 1543 if (err) 1544 return err; 1545 1546 for (i = 0; i < len; i++) { 1547 err = mcp251xfd_handle_rxif_one(priv, ring, 1548 (void *)hw_rx_obj + 1549 i * ring->obj_size); 1550 if (err) 1551 return err; 1552 } 1553 1554 /* Increment the RX FIFO tail pointer 'len' times in a 1555 * single SPI message. 1556 */ 1557 ring->tail += len; 1558 1559 /* Note: 1560 * 1561 * "cs_change == 1" on the last transfer results in an 1562 * active chip select after the complete SPI 1563 * message. This causes the controller to interpret 1564 * the next register access as data. Temporary set 1565 * "cs_change" of the last transfer to "0" to properly 1566 * deactivate the chip select at the end of the 1567 * message. 1568 */ 1569 last_xfer = &ring->uinc_xfer[len - 1]; 1570 last_xfer->cs_change = 0; 1571 err = spi_sync_transfer(priv->spi, ring->uinc_xfer, len); 1572 last_xfer->cs_change = 1; 1573 if (err) 1574 return err; 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int mcp251xfd_handle_rxif(struct mcp251xfd_priv *priv) 1581 { 1582 struct mcp251xfd_rx_ring *ring; 1583 int err, n; 1584 1585 mcp251xfd_for_each_rx_ring(priv, ring, n) { 1586 err = mcp251xfd_handle_rxif_ring(priv, ring); 1587 if (err) 1588 return err; 1589 } 1590 1591 return 0; 1592 } 1593 1594 static inline int mcp251xfd_get_timestamp(const struct mcp251xfd_priv *priv, 1595 u32 *timestamp) 1596 { 1597 return regmap_read(priv->map_reg, MCP251XFD_REG_TBC, timestamp); 1598 } 1599 1600 static struct sk_buff * 1601 mcp251xfd_alloc_can_err_skb(const struct mcp251xfd_priv *priv, 1602 struct can_frame **cf, u32 *timestamp) 1603 { 1604 int err; 1605 1606 err = mcp251xfd_get_timestamp(priv, timestamp); 1607 if (err) 1608 return NULL; 1609 1610 return alloc_can_err_skb(priv->ndev, cf); 1611 } 1612 1613 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv) 1614 { 1615 struct net_device_stats *stats = &priv->ndev->stats; 1616 struct mcp251xfd_rx_ring *ring; 1617 struct sk_buff *skb; 1618 struct can_frame *cf; 1619 u32 timestamp, rxovif; 1620 int err, i; 1621 1622 stats->rx_over_errors++; 1623 stats->rx_errors++; 1624 1625 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif); 1626 if (err) 1627 return err; 1628 1629 mcp251xfd_for_each_rx_ring(priv, ring, i) { 1630 if (!(rxovif & BIT(ring->fifo_nr))) 1631 continue; 1632 1633 /* If SERRIF is active, there was a RX MAB overflow. */ 1634 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) { 1635 netdev_info(priv->ndev, 1636 "RX-%d: MAB overflow detected.\n", 1637 ring->nr); 1638 } else { 1639 netdev_info(priv->ndev, 1640 "RX-%d: FIFO overflow.\n", ring->nr); 1641 } 1642 1643 err = regmap_update_bits(priv->map_reg, 1644 MCP251XFD_REG_FIFOSTA(ring->fifo_nr), 1645 MCP251XFD_REG_FIFOSTA_RXOVIF, 1646 0x0); 1647 if (err) 1648 return err; 1649 } 1650 1651 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 1652 if (!skb) 1653 return 0; 1654 1655 cf->can_id |= CAN_ERR_CRTL; 1656 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 1657 1658 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 1659 if (err) 1660 stats->rx_fifo_errors++; 1661 1662 return 0; 1663 } 1664 1665 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv) 1666 { 1667 netdev_info(priv->ndev, "%s\n", __func__); 1668 1669 return 0; 1670 } 1671 1672 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv) 1673 { 1674 struct net_device_stats *stats = &priv->ndev->stats; 1675 u32 bdiag1, timestamp; 1676 struct sk_buff *skb; 1677 struct can_frame *cf = NULL; 1678 int err; 1679 1680 err = mcp251xfd_get_timestamp(priv, ×tamp); 1681 if (err) 1682 return err; 1683 1684 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1); 1685 if (err) 1686 return err; 1687 1688 /* Write 0s to clear error bits, don't write 1s to non active 1689 * bits, as they will be set. 1690 */ 1691 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0); 1692 if (err) 1693 return err; 1694 1695 priv->can.can_stats.bus_error++; 1696 1697 skb = alloc_can_err_skb(priv->ndev, &cf); 1698 if (cf) 1699 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 1700 1701 /* Controller misconfiguration */ 1702 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM)) 1703 netdev_err(priv->ndev, 1704 "recv'd DLC is larger than PLSIZE of FIFO element."); 1705 1706 /* RX errors */ 1707 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR | 1708 MCP251XFD_REG_BDIAG1_NCRCERR)) { 1709 netdev_dbg(priv->ndev, "CRC error\n"); 1710 1711 stats->rx_errors++; 1712 if (cf) 1713 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 1714 } 1715 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR | 1716 MCP251XFD_REG_BDIAG1_NSTUFERR)) { 1717 netdev_dbg(priv->ndev, "Stuff error\n"); 1718 1719 stats->rx_errors++; 1720 if (cf) 1721 cf->data[2] |= CAN_ERR_PROT_STUFF; 1722 } 1723 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR | 1724 MCP251XFD_REG_BDIAG1_NFORMERR)) { 1725 netdev_dbg(priv->ndev, "Format error\n"); 1726 1727 stats->rx_errors++; 1728 if (cf) 1729 cf->data[2] |= CAN_ERR_PROT_FORM; 1730 } 1731 1732 /* TX errors */ 1733 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) { 1734 netdev_dbg(priv->ndev, "NACK error\n"); 1735 1736 stats->tx_errors++; 1737 if (cf) { 1738 cf->can_id |= CAN_ERR_ACK; 1739 cf->data[2] |= CAN_ERR_PROT_TX; 1740 } 1741 } 1742 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR | 1743 MCP251XFD_REG_BDIAG1_NBIT1ERR)) { 1744 netdev_dbg(priv->ndev, "Bit1 error\n"); 1745 1746 stats->tx_errors++; 1747 if (cf) 1748 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1; 1749 } 1750 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR | 1751 MCP251XFD_REG_BDIAG1_NBIT0ERR)) { 1752 netdev_dbg(priv->ndev, "Bit0 error\n"); 1753 1754 stats->tx_errors++; 1755 if (cf) 1756 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0; 1757 } 1758 1759 if (!cf) 1760 return 0; 1761 1762 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 1763 if (err) 1764 stats->rx_fifo_errors++; 1765 1766 return 0; 1767 } 1768 1769 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv) 1770 { 1771 struct net_device_stats *stats = &priv->ndev->stats; 1772 struct sk_buff *skb; 1773 struct can_frame *cf = NULL; 1774 enum can_state new_state, rx_state, tx_state; 1775 u32 trec, timestamp; 1776 int err; 1777 1778 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 1779 if (err) 1780 return err; 1781 1782 if (trec & MCP251XFD_REG_TREC_TXBO) 1783 tx_state = CAN_STATE_BUS_OFF; 1784 else if (trec & MCP251XFD_REG_TREC_TXBP) 1785 tx_state = CAN_STATE_ERROR_PASSIVE; 1786 else if (trec & MCP251XFD_REG_TREC_TXWARN) 1787 tx_state = CAN_STATE_ERROR_WARNING; 1788 else 1789 tx_state = CAN_STATE_ERROR_ACTIVE; 1790 1791 if (trec & MCP251XFD_REG_TREC_RXBP) 1792 rx_state = CAN_STATE_ERROR_PASSIVE; 1793 else if (trec & MCP251XFD_REG_TREC_RXWARN) 1794 rx_state = CAN_STATE_ERROR_WARNING; 1795 else 1796 rx_state = CAN_STATE_ERROR_ACTIVE; 1797 1798 new_state = max(tx_state, rx_state); 1799 if (new_state == priv->can.state) 1800 return 0; 1801 1802 /* The skb allocation might fail, but can_change_state() 1803 * handles cf == NULL. 1804 */ 1805 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 1806 can_change_state(priv->ndev, cf, tx_state, rx_state); 1807 1808 if (new_state == CAN_STATE_BUS_OFF) { 1809 /* As we're going to switch off the chip now, let's 1810 * save the error counters and return them to 1811 * userspace, if do_get_berr_counter() is called while 1812 * the chip is in Bus Off. 1813 */ 1814 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec); 1815 if (err) 1816 return err; 1817 1818 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF); 1819 can_bus_off(priv->ndev); 1820 } 1821 1822 if (!skb) 1823 return 0; 1824 1825 if (new_state != CAN_STATE_BUS_OFF) { 1826 struct can_berr_counter bec; 1827 1828 err = mcp251xfd_get_berr_counter(priv->ndev, &bec); 1829 if (err) 1830 return err; 1831 cf->data[6] = bec.txerr; 1832 cf->data[7] = bec.rxerr; 1833 } 1834 1835 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); 1836 if (err) 1837 stats->rx_fifo_errors++; 1838 1839 return 0; 1840 } 1841 1842 static int 1843 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode) 1844 { 1845 const u8 mode_reference = mcp251xfd_get_normal_mode(priv); 1846 u8 mode; 1847 int err; 1848 1849 err = mcp251xfd_chip_get_mode(priv, &mode); 1850 if (err) 1851 return err; 1852 1853 if (mode == mode_reference) { 1854 netdev_dbg(priv->ndev, 1855 "Controller changed into %s Mode (%u).\n", 1856 mcp251xfd_get_mode_str(mode), mode); 1857 return 0; 1858 } 1859 1860 /* According to MCP2517FD errata DS80000792B 1., during a TX 1861 * MAB underflow, the controller will transition to Restricted 1862 * Operation Mode or Listen Only Mode (depending on SERR2LOM). 1863 * 1864 * However this is not always the case. If SERR2LOM is 1865 * configured for Restricted Operation Mode (SERR2LOM not set) 1866 * the MCP2517FD will sometimes transition to Listen Only Mode 1867 * first. When polling this bit we see that it will transition 1868 * to Restricted Operation Mode shortly after. 1869 */ 1870 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) && 1871 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED || 1872 mode == MCP251XFD_REG_CON_MODE_LISTENONLY)) 1873 netdev_dbg(priv->ndev, 1874 "Controller changed into %s Mode (%u).\n", 1875 mcp251xfd_get_mode_str(mode), mode); 1876 else 1877 netdev_err(priv->ndev, 1878 "Controller changed into %s Mode (%u).\n", 1879 mcp251xfd_get_mode_str(mode), mode); 1880 1881 /* After the application requests Normal mode, the Controller 1882 * will automatically attempt to retransmit the message that 1883 * caused the TX MAB underflow. 1884 * 1885 * However, if there is an ECC error in the TX-RAM, we first 1886 * have to reload the tx-object before requesting Normal 1887 * mode. This is done later in mcp251xfd_handle_eccif(). 1888 */ 1889 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) { 1890 *set_normal_mode = true; 1891 return 0; 1892 } 1893 1894 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1895 } 1896 1897 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv) 1898 { 1899 struct mcp251xfd_ecc *ecc = &priv->ecc; 1900 struct net_device_stats *stats = &priv->ndev->stats; 1901 bool handled = false; 1902 1903 /* TX MAB underflow 1904 * 1905 * According to MCP2517FD Errata DS80000792B 1. a TX MAB 1906 * underflow is indicated by SERRIF and MODIF. 1907 * 1908 * In addition to the effects mentioned in the Errata, there 1909 * are Bus Errors due to the aborted CAN frame, so a IVMIF 1910 * will be seen as well. 1911 * 1912 * Sometimes there is an ECC error in the TX-RAM, which leads 1913 * to a TX MAB underflow. 1914 * 1915 * However, probably due to a race condition, there is no 1916 * associated MODIF pending. 1917 * 1918 * Further, there are situations, where the SERRIF is caused 1919 * by an ECC error in the TX-RAM, but not even the ECCIF is 1920 * set. This only seems to happen _after_ the first occurrence 1921 * of a ECCIF (which is tracked in ecc->cnt). 1922 * 1923 * Treat all as a known system errors.. 1924 */ 1925 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF && 1926 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) || 1927 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1928 ecc->cnt) { 1929 const char *msg; 1930 1931 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1932 ecc->cnt) 1933 msg = "TX MAB underflow due to ECC error detected."; 1934 else 1935 msg = "TX MAB underflow detected."; 1936 1937 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) 1938 netdev_dbg(priv->ndev, "%s\n", msg); 1939 else 1940 netdev_info(priv->ndev, "%s\n", msg); 1941 1942 stats->tx_aborted_errors++; 1943 stats->tx_errors++; 1944 handled = true; 1945 } 1946 1947 /* RX MAB overflow 1948 * 1949 * According to MCP2517FD Errata DS80000792B 1. a RX MAB 1950 * overflow is indicated by SERRIF. 1951 * 1952 * In addition to the effects mentioned in the Errata, (most 1953 * of the times) a RXOVIF is raised, if the FIFO that is being 1954 * received into has the RXOVIE activated (and we have enabled 1955 * RXOVIE on all FIFOs). 1956 * 1957 * Sometimes there is no RXOVIF just a RXIF is pending. 1958 * 1959 * Treat all as a known system errors.. 1960 */ 1961 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF || 1962 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) { 1963 stats->rx_dropped++; 1964 handled = true; 1965 } 1966 1967 if (!handled) 1968 netdev_err(priv->ndev, 1969 "Unhandled System Error Interrupt (intf=0x%08x)!\n", 1970 priv->regs_status.intf); 1971 1972 return 0; 1973 } 1974 1975 static int 1976 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr) 1977 { 1978 struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1979 struct mcp251xfd_ecc *ecc = &priv->ecc; 1980 struct mcp251xfd_tx_obj *tx_obj; 1981 u8 chip_tx_tail, tx_tail, offset; 1982 u16 addr; 1983 int err; 1984 1985 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat); 1986 1987 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail); 1988 if (err) 1989 return err; 1990 1991 tx_tail = mcp251xfd_get_tx_tail(tx_ring); 1992 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1); 1993 1994 /* Bail out if one of the following is met: 1995 * - tx_tail information is inconsistent 1996 * - for mcp2517fd: offset not 0 1997 * - for mcp2518fd: offset not 0 or 1 1998 */ 1999 if (chip_tx_tail != tx_tail || 2000 !(offset == 0 || (offset == 1 && mcp251xfd_is_2518(priv)))) { 2001 netdev_err(priv->ndev, 2002 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n", 2003 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail, 2004 offset); 2005 return -EINVAL; 2006 } 2007 2008 netdev_info(priv->ndev, 2009 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n", 2010 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ? 2011 "Single" : "Double", 2012 addr, nr, tx_ring->tail, tx_tail, offset); 2013 2014 /* reload tx_obj into controller RAM ... */ 2015 tx_obj = &tx_ring->obj[nr]; 2016 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1); 2017 if (err) 2018 return err; 2019 2020 /* ... and trigger retransmit */ 2021 return mcp251xfd_chip_set_normal_mode(priv); 2022 } 2023 2024 static int 2025 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode) 2026 { 2027 struct mcp251xfd_ecc *ecc = &priv->ecc; 2028 const char *msg; 2029 bool in_tx_ram; 2030 u32 ecc_stat; 2031 u16 addr; 2032 u8 nr; 2033 int err; 2034 2035 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat); 2036 if (err) 2037 return err; 2038 2039 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT, 2040 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat); 2041 if (err) 2042 return err; 2043 2044 /* Check if ECC error occurred in TX-RAM */ 2045 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat); 2046 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr); 2047 if (!err) 2048 in_tx_ram = true; 2049 else if (err == -ENOENT) 2050 in_tx_ram = false; 2051 else 2052 return err; 2053 2054 /* Errata Reference: 2055 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2. 2056 * 2057 * ECC single error correction does not work in all cases: 2058 * 2059 * Fix/Work Around: 2060 * Enable single error correction and double error detection 2061 * interrupts by setting SECIE and DEDIE. Handle SECIF as a 2062 * detection interrupt and do not rely on the error 2063 * correction. Instead, handle both interrupts as a 2064 * notification that the RAM word at ERRADDR was corrupted. 2065 */ 2066 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF) 2067 msg = "Single ECC Error detected at address"; 2068 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF) 2069 msg = "Double ECC Error detected at address"; 2070 else 2071 return -EINVAL; 2072 2073 if (!in_tx_ram) { 2074 ecc->ecc_stat = 0; 2075 2076 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr); 2077 } else { 2078 /* Re-occurring error? */ 2079 if (ecc->ecc_stat == ecc_stat) { 2080 ecc->cnt++; 2081 } else { 2082 ecc->ecc_stat = ecc_stat; 2083 ecc->cnt = 1; 2084 } 2085 2086 netdev_info(priv->ndev, 2087 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n", 2088 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : ""); 2089 2090 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX) 2091 return mcp251xfd_handle_eccif_recover(priv, nr); 2092 } 2093 2094 if (set_normal_mode) 2095 return mcp251xfd_chip_set_normal_mode_nowait(priv); 2096 2097 return 0; 2098 } 2099 2100 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv) 2101 { 2102 int err; 2103 u32 crc; 2104 2105 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc); 2106 if (err) 2107 return err; 2108 2109 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC, 2110 MCP251XFD_REG_CRC_IF_MASK, 2111 ~crc); 2112 if (err) 2113 return err; 2114 2115 if (crc & MCP251XFD_REG_CRC_FERRIF) 2116 netdev_notice(priv->ndev, "CRC write command format error.\n"); 2117 else if (crc & MCP251XFD_REG_CRC_CRCERRIF) 2118 netdev_notice(priv->ndev, 2119 "CRC write error detected. CRC=0x%04lx.\n", 2120 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc)); 2121 2122 return 0; 2123 } 2124 2125 #define mcp251xfd_handle(priv, irq, ...) \ 2126 ({ \ 2127 struct mcp251xfd_priv *_priv = (priv); \ 2128 int err; \ 2129 \ 2130 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \ 2131 if (err) \ 2132 netdev_err(_priv->ndev, \ 2133 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \ 2134 __stringify(irq), err); \ 2135 err; \ 2136 }) 2137 2138 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id) 2139 { 2140 struct mcp251xfd_priv *priv = dev_id; 2141 irqreturn_t handled = IRQ_NONE; 2142 int err; 2143 2144 if (priv->rx_int) 2145 do { 2146 int rx_pending; 2147 2148 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 2149 if (!rx_pending) 2150 break; 2151 2152 err = mcp251xfd_handle(priv, rxif); 2153 if (err) 2154 goto out_fail; 2155 2156 handled = IRQ_HANDLED; 2157 } while (1); 2158 2159 do { 2160 u32 intf_pending, intf_pending_clearable; 2161 bool set_normal_mode = false; 2162 2163 err = regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT, 2164 &priv->regs_status, 2165 sizeof(priv->regs_status) / 2166 sizeof(u32)); 2167 if (err) 2168 goto out_fail; 2169 2170 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK, 2171 priv->regs_status.intf) & 2172 FIELD_GET(MCP251XFD_REG_INT_IE_MASK, 2173 priv->regs_status.intf); 2174 2175 if (!(intf_pending)) 2176 return handled; 2177 2178 /* Some interrupts must be ACKed in the 2179 * MCP251XFD_REG_INT register. 2180 * - First ACK then handle, to avoid lost-IRQ race 2181 * condition on fast re-occurring interrupts. 2182 * - Write "0" to clear active IRQs, "1" to all other, 2183 * to avoid r/m/w race condition on the 2184 * MCP251XFD_REG_INT register. 2185 */ 2186 intf_pending_clearable = intf_pending & 2187 MCP251XFD_REG_INT_IF_CLEARABLE_MASK; 2188 if (intf_pending_clearable) { 2189 err = regmap_update_bits(priv->map_reg, 2190 MCP251XFD_REG_INT, 2191 MCP251XFD_REG_INT_IF_MASK, 2192 ~intf_pending_clearable); 2193 if (err) 2194 goto out_fail; 2195 } 2196 2197 if (intf_pending & MCP251XFD_REG_INT_MODIF) { 2198 err = mcp251xfd_handle(priv, modif, &set_normal_mode); 2199 if (err) 2200 goto out_fail; 2201 } 2202 2203 if (intf_pending & MCP251XFD_REG_INT_RXIF) { 2204 err = mcp251xfd_handle(priv, rxif); 2205 if (err) 2206 goto out_fail; 2207 } 2208 2209 if (intf_pending & MCP251XFD_REG_INT_TEFIF) { 2210 err = mcp251xfd_handle(priv, tefif); 2211 if (err) 2212 goto out_fail; 2213 } 2214 2215 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) { 2216 err = mcp251xfd_handle(priv, rxovif); 2217 if (err) 2218 goto out_fail; 2219 } 2220 2221 if (intf_pending & MCP251XFD_REG_INT_TXATIF) { 2222 err = mcp251xfd_handle(priv, txatif); 2223 if (err) 2224 goto out_fail; 2225 } 2226 2227 if (intf_pending & MCP251XFD_REG_INT_IVMIF) { 2228 err = mcp251xfd_handle(priv, ivmif); 2229 if (err) 2230 goto out_fail; 2231 } 2232 2233 if (intf_pending & MCP251XFD_REG_INT_SERRIF) { 2234 err = mcp251xfd_handle(priv, serrif); 2235 if (err) 2236 goto out_fail; 2237 } 2238 2239 if (intf_pending & MCP251XFD_REG_INT_ECCIF) { 2240 err = mcp251xfd_handle(priv, eccif, set_normal_mode); 2241 if (err) 2242 goto out_fail; 2243 } 2244 2245 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) { 2246 err = mcp251xfd_handle(priv, spicrcif); 2247 if (err) 2248 goto out_fail; 2249 } 2250 2251 /* On the MCP2527FD and MCP2518FD, we don't get a 2252 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX 2253 * ERROR_ACTIVE. 2254 */ 2255 if (intf_pending & MCP251XFD_REG_INT_CERRIF || 2256 priv->can.state > CAN_STATE_ERROR_ACTIVE) { 2257 err = mcp251xfd_handle(priv, cerrif); 2258 if (err) 2259 goto out_fail; 2260 2261 /* In Bus Off we completely shut down the 2262 * controller. Every subsequent register read 2263 * will read bogus data, and if 2264 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC 2265 * check will fail, too. So leave IRQ handler 2266 * directly. 2267 */ 2268 if (priv->can.state == CAN_STATE_BUS_OFF) 2269 return IRQ_HANDLED; 2270 } 2271 2272 handled = IRQ_HANDLED; 2273 } while (1); 2274 2275 out_fail: 2276 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n", 2277 err, priv->regs_status.intf); 2278 mcp251xfd_chip_interrupts_disable(priv); 2279 2280 return handled; 2281 } 2282 2283 static inline struct 2284 mcp251xfd_tx_obj *mcp251xfd_get_tx_obj_next(struct mcp251xfd_tx_ring *tx_ring) 2285 { 2286 u8 tx_head; 2287 2288 tx_head = mcp251xfd_get_tx_head(tx_ring); 2289 2290 return &tx_ring->obj[tx_head]; 2291 } 2292 2293 static void 2294 mcp251xfd_tx_obj_from_skb(const struct mcp251xfd_priv *priv, 2295 struct mcp251xfd_tx_obj *tx_obj, 2296 const struct sk_buff *skb, 2297 unsigned int seq) 2298 { 2299 const struct canfd_frame *cfd = (struct canfd_frame *)skb->data; 2300 struct mcp251xfd_hw_tx_obj_raw *hw_tx_obj; 2301 union mcp251xfd_tx_obj_load_buf *load_buf; 2302 u8 dlc; 2303 u32 id, flags; 2304 int offset, len; 2305 2306 if (cfd->can_id & CAN_EFF_FLAG) { 2307 u32 sid, eid; 2308 2309 sid = FIELD_GET(MCP251XFD_REG_FRAME_EFF_SID_MASK, cfd->can_id); 2310 eid = FIELD_GET(MCP251XFD_REG_FRAME_EFF_EID_MASK, cfd->can_id); 2311 2312 id = FIELD_PREP(MCP251XFD_OBJ_ID_EID_MASK, eid) | 2313 FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, sid); 2314 2315 flags = MCP251XFD_OBJ_FLAGS_IDE; 2316 } else { 2317 id = FIELD_PREP(MCP251XFD_OBJ_ID_SID_MASK, cfd->can_id); 2318 flags = 0; 2319 } 2320 2321 /* Use the MCP2518FD mask even on the MCP2517FD. It doesn't 2322 * harm, only the lower 7 bits will be transferred into the 2323 * TEF object. 2324 */ 2325 dlc = can_fd_len2dlc(cfd->len); 2326 flags |= FIELD_PREP(MCP251XFD_OBJ_FLAGS_SEQ_MCP2518FD_MASK, seq) | 2327 FIELD_PREP(MCP251XFD_OBJ_FLAGS_DLC, dlc); 2328 2329 if (cfd->can_id & CAN_RTR_FLAG) 2330 flags |= MCP251XFD_OBJ_FLAGS_RTR; 2331 2332 /* CANFD */ 2333 if (can_is_canfd_skb(skb)) { 2334 if (cfd->flags & CANFD_ESI) 2335 flags |= MCP251XFD_OBJ_FLAGS_ESI; 2336 2337 flags |= MCP251XFD_OBJ_FLAGS_FDF; 2338 2339 if (cfd->flags & CANFD_BRS) 2340 flags |= MCP251XFD_OBJ_FLAGS_BRS; 2341 } 2342 2343 load_buf = &tx_obj->buf; 2344 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_TX) 2345 hw_tx_obj = &load_buf->crc.hw_tx_obj; 2346 else 2347 hw_tx_obj = &load_buf->nocrc.hw_tx_obj; 2348 2349 put_unaligned_le32(id, &hw_tx_obj->id); 2350 put_unaligned_le32(flags, &hw_tx_obj->flags); 2351 2352 /* Clear data at end of CAN frame */ 2353 offset = round_down(cfd->len, sizeof(u32)); 2354 len = round_up(can_fd_dlc2len(dlc), sizeof(u32)) - offset; 2355 if (MCP251XFD_SANITIZE_CAN && len) 2356 memset(hw_tx_obj->data + offset, 0x0, len); 2357 memcpy(hw_tx_obj->data, cfd->data, cfd->len); 2358 2359 /* Number of bytes to be written into the RAM of the controller */ 2360 len = sizeof(hw_tx_obj->id) + sizeof(hw_tx_obj->flags); 2361 if (MCP251XFD_SANITIZE_CAN) 2362 len += round_up(can_fd_dlc2len(dlc), sizeof(u32)); 2363 else 2364 len += round_up(cfd->len, sizeof(u32)); 2365 2366 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_CRC_TX) { 2367 u16 crc; 2368 2369 mcp251xfd_spi_cmd_crc_set_len_in_ram(&load_buf->crc.cmd, 2370 len); 2371 /* CRC */ 2372 len += sizeof(load_buf->crc.cmd); 2373 crc = mcp251xfd_crc16_compute(&load_buf->crc, len); 2374 put_unaligned_be16(crc, (void *)load_buf + len); 2375 2376 /* Total length */ 2377 len += sizeof(load_buf->crc.crc); 2378 } else { 2379 len += sizeof(load_buf->nocrc.cmd); 2380 } 2381 2382 tx_obj->xfer[0].len = len; 2383 } 2384 2385 static int mcp251xfd_tx_obj_write(const struct mcp251xfd_priv *priv, 2386 struct mcp251xfd_tx_obj *tx_obj) 2387 { 2388 return spi_async(priv->spi, &tx_obj->msg); 2389 } 2390 2391 static bool mcp251xfd_tx_busy(const struct mcp251xfd_priv *priv, 2392 struct mcp251xfd_tx_ring *tx_ring) 2393 { 2394 if (mcp251xfd_get_tx_free(tx_ring) > 0) 2395 return false; 2396 2397 netif_stop_queue(priv->ndev); 2398 2399 /* Memory barrier before checking tx_free (head and tail) */ 2400 smp_mb(); 2401 2402 if (mcp251xfd_get_tx_free(tx_ring) == 0) { 2403 netdev_dbg(priv->ndev, 2404 "Stopping tx-queue (tx_head=0x%08x, tx_tail=0x%08x, len=%d).\n", 2405 tx_ring->head, tx_ring->tail, 2406 tx_ring->head - tx_ring->tail); 2407 2408 return true; 2409 } 2410 2411 netif_start_queue(priv->ndev); 2412 2413 return false; 2414 } 2415 2416 static netdev_tx_t mcp251xfd_start_xmit(struct sk_buff *skb, 2417 struct net_device *ndev) 2418 { 2419 struct mcp251xfd_priv *priv = netdev_priv(ndev); 2420 struct mcp251xfd_tx_ring *tx_ring = priv->tx; 2421 struct mcp251xfd_tx_obj *tx_obj; 2422 u8 tx_head; 2423 int err; 2424 2425 if (can_dropped_invalid_skb(ndev, skb)) 2426 return NETDEV_TX_OK; 2427 2428 if (mcp251xfd_tx_busy(priv, tx_ring)) 2429 return NETDEV_TX_BUSY; 2430 2431 tx_obj = mcp251xfd_get_tx_obj_next(tx_ring); 2432 mcp251xfd_tx_obj_from_skb(priv, tx_obj, skb, tx_ring->head); 2433 2434 /* Stop queue if we occupy the complete TX FIFO */ 2435 tx_head = mcp251xfd_get_tx_head(tx_ring); 2436 tx_ring->head++; 2437 if (tx_ring->head - tx_ring->tail >= tx_ring->obj_num) 2438 netif_stop_queue(ndev); 2439 2440 can_put_echo_skb(skb, ndev, tx_head); 2441 2442 err = mcp251xfd_tx_obj_write(priv, tx_obj); 2443 if (err) 2444 goto out_err; 2445 2446 return NETDEV_TX_OK; 2447 2448 out_err: 2449 netdev_err(priv->ndev, "ERROR in %s: %d\n", __func__, err); 2450 2451 return NETDEV_TX_OK; 2452 } 2453 2454 static int mcp251xfd_open(struct net_device *ndev) 2455 { 2456 struct mcp251xfd_priv *priv = netdev_priv(ndev); 2457 const struct spi_device *spi = priv->spi; 2458 int err; 2459 2460 err = pm_runtime_get_sync(ndev->dev.parent); 2461 if (err < 0) { 2462 pm_runtime_put_noidle(ndev->dev.parent); 2463 return err; 2464 } 2465 2466 err = open_candev(ndev); 2467 if (err) 2468 goto out_pm_runtime_put; 2469 2470 err = mcp251xfd_ring_alloc(priv); 2471 if (err) 2472 goto out_close_candev; 2473 2474 err = mcp251xfd_transceiver_enable(priv); 2475 if (err) 2476 goto out_mcp251xfd_ring_free; 2477 2478 err = mcp251xfd_chip_start(priv); 2479 if (err) 2480 goto out_transceiver_disable; 2481 2482 can_rx_offload_enable(&priv->offload); 2483 2484 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq, 2485 IRQF_ONESHOT, dev_name(&spi->dev), 2486 priv); 2487 if (err) 2488 goto out_can_rx_offload_disable; 2489 2490 err = mcp251xfd_chip_interrupts_enable(priv); 2491 if (err) 2492 goto out_free_irq; 2493 2494 netif_start_queue(ndev); 2495 2496 return 0; 2497 2498 out_free_irq: 2499 free_irq(spi->irq, priv); 2500 out_can_rx_offload_disable: 2501 can_rx_offload_disable(&priv->offload); 2502 out_transceiver_disable: 2503 mcp251xfd_transceiver_disable(priv); 2504 out_mcp251xfd_ring_free: 2505 mcp251xfd_ring_free(priv); 2506 out_close_candev: 2507 close_candev(ndev); 2508 out_pm_runtime_put: 2509 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 2510 pm_runtime_put(ndev->dev.parent); 2511 2512 return err; 2513 } 2514 2515 static int mcp251xfd_stop(struct net_device *ndev) 2516 { 2517 struct mcp251xfd_priv *priv = netdev_priv(ndev); 2518 2519 netif_stop_queue(ndev); 2520 mcp251xfd_chip_interrupts_disable(priv); 2521 free_irq(ndev->irq, priv); 2522 can_rx_offload_disable(&priv->offload); 2523 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 2524 mcp251xfd_transceiver_disable(priv); 2525 mcp251xfd_ring_free(priv); 2526 close_candev(ndev); 2527 2528 pm_runtime_put(ndev->dev.parent); 2529 2530 return 0; 2531 } 2532 2533 static const struct net_device_ops mcp251xfd_netdev_ops = { 2534 .ndo_open = mcp251xfd_open, 2535 .ndo_stop = mcp251xfd_stop, 2536 .ndo_start_xmit = mcp251xfd_start_xmit, 2537 .ndo_change_mtu = can_change_mtu, 2538 }; 2539 2540 static void 2541 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv) 2542 { 2543 const struct spi_device *spi = priv->spi; 2544 const struct spi_controller *ctlr = spi->controller; 2545 2546 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX) 2547 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX; 2548 } 2549 2550 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv) 2551 { 2552 const struct net_device *ndev = priv->ndev; 2553 const struct mcp251xfd_devtype_data *devtype_data; 2554 u32 osc; 2555 int err; 2556 2557 /* The OSC_LPMEN is only supported on MCP2518FD, so use it to 2558 * autodetect the model. 2559 */ 2560 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC, 2561 MCP251XFD_REG_OSC_LPMEN, 2562 MCP251XFD_REG_OSC_LPMEN); 2563 if (err) 2564 return err; 2565 2566 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 2567 if (err) 2568 return err; 2569 2570 if (osc & MCP251XFD_REG_OSC_LPMEN) 2571 devtype_data = &mcp251xfd_devtype_data_mcp2518fd; 2572 else 2573 devtype_data = &mcp251xfd_devtype_data_mcp2517fd; 2574 2575 if (!mcp251xfd_is_251X(priv) && 2576 priv->devtype_data.model != devtype_data->model) { 2577 netdev_info(ndev, 2578 "Detected %s, but firmware specifies a %s. Fixing up.", 2579 __mcp251xfd_get_model_str(devtype_data->model), 2580 mcp251xfd_get_model_str(priv)); 2581 } 2582 priv->devtype_data = *devtype_data; 2583 2584 /* We need to preserve the Half Duplex Quirk. */ 2585 mcp251xfd_register_quirks(priv); 2586 2587 /* Re-init regmap with quirks of detected model. */ 2588 return mcp251xfd_regmap_init(priv); 2589 } 2590 2591 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv) 2592 { 2593 int err, rx_pending; 2594 2595 if (!priv->rx_int) 2596 return 0; 2597 2598 err = mcp251xfd_chip_rx_int_enable(priv); 2599 if (err) 2600 return err; 2601 2602 /* Check if RX_INT is properly working. The RX_INT should not 2603 * be active after a softreset. 2604 */ 2605 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 2606 2607 err = mcp251xfd_chip_rx_int_disable(priv); 2608 if (err) 2609 return err; 2610 2611 if (!rx_pending) 2612 return 0; 2613 2614 netdev_info(priv->ndev, 2615 "RX_INT active after softreset, disabling RX_INT support."); 2616 devm_gpiod_put(&priv->spi->dev, priv->rx_int); 2617 priv->rx_int = NULL; 2618 2619 return 0; 2620 } 2621 2622 static int 2623 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, 2624 u32 *dev_id, u32 *effective_speed_hz) 2625 { 2626 struct mcp251xfd_map_buf_nocrc *buf_rx; 2627 struct mcp251xfd_map_buf_nocrc *buf_tx; 2628 struct spi_transfer xfer[2] = { }; 2629 int err; 2630 2631 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL); 2632 if (!buf_rx) 2633 return -ENOMEM; 2634 2635 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL); 2636 if (!buf_tx) { 2637 err = -ENOMEM; 2638 goto out_kfree_buf_rx; 2639 } 2640 2641 xfer[0].tx_buf = buf_tx; 2642 xfer[0].len = sizeof(buf_tx->cmd); 2643 xfer[1].rx_buf = buf_rx->data; 2644 xfer[1].len = sizeof(dev_id); 2645 2646 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID); 2647 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer)); 2648 if (err) 2649 goto out_kfree_buf_tx; 2650 2651 *dev_id = be32_to_cpup((__be32 *)buf_rx->data); 2652 *effective_speed_hz = xfer->effective_speed_hz; 2653 2654 out_kfree_buf_tx: 2655 kfree(buf_tx); 2656 out_kfree_buf_rx: 2657 kfree(buf_rx); 2658 2659 return 0; 2660 } 2661 2662 #define MCP251XFD_QUIRK_ACTIVE(quirk) \ 2663 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-') 2664 2665 static int 2666 mcp251xfd_register_done(const struct mcp251xfd_priv *priv) 2667 { 2668 u32 dev_id, effective_speed_hz; 2669 int err; 2670 2671 err = mcp251xfd_register_get_dev_id(priv, &dev_id, 2672 &effective_speed_hz); 2673 if (err) 2674 return err; 2675 2676 netdev_info(priv->ndev, 2677 "%s rev%lu.%lu (%cRX_INT %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD c:%u.%02uMHz m:%u.%02uMHz r:%u.%02uMHz e:%u.%02uMHz) successfully initialized.\n", 2678 mcp251xfd_get_model_str(priv), 2679 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id), 2680 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id), 2681 priv->rx_int ? '+' : '-', 2682 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN), 2683 MCP251XFD_QUIRK_ACTIVE(CRC_REG), 2684 MCP251XFD_QUIRK_ACTIVE(CRC_RX), 2685 MCP251XFD_QUIRK_ACTIVE(CRC_TX), 2686 MCP251XFD_QUIRK_ACTIVE(ECC), 2687 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX), 2688 priv->can.clock.freq / 1000000, 2689 priv->can.clock.freq % 1000000 / 1000 / 10, 2690 priv->spi_max_speed_hz_orig / 1000000, 2691 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10, 2692 priv->spi->max_speed_hz / 1000000, 2693 priv->spi->max_speed_hz % 1000000 / 1000 / 10, 2694 effective_speed_hz / 1000000, 2695 effective_speed_hz % 1000000 / 1000 / 10); 2696 2697 return 0; 2698 } 2699 2700 static int mcp251xfd_register(struct mcp251xfd_priv *priv) 2701 { 2702 struct net_device *ndev = priv->ndev; 2703 int err; 2704 2705 err = mcp251xfd_clks_and_vdd_enable(priv); 2706 if (err) 2707 return err; 2708 2709 pm_runtime_get_noresume(ndev->dev.parent); 2710 err = pm_runtime_set_active(ndev->dev.parent); 2711 if (err) 2712 goto out_runtime_put_noidle; 2713 pm_runtime_enable(ndev->dev.parent); 2714 2715 mcp251xfd_register_quirks(priv); 2716 2717 err = mcp251xfd_chip_softreset(priv); 2718 if (err == -ENODEV) 2719 goto out_runtime_disable; 2720 if (err) 2721 goto out_chip_set_mode_sleep; 2722 2723 err = mcp251xfd_register_chip_detect(priv); 2724 if (err) 2725 goto out_chip_set_mode_sleep; 2726 2727 err = mcp251xfd_register_check_rx_int(priv); 2728 if (err) 2729 goto out_chip_set_mode_sleep; 2730 2731 err = register_candev(ndev); 2732 if (err) 2733 goto out_chip_set_mode_sleep; 2734 2735 err = mcp251xfd_register_done(priv); 2736 if (err) 2737 goto out_unregister_candev; 2738 2739 /* Put controller into sleep mode and let pm_runtime_put() 2740 * disable the clocks and vdd. If CONFIG_PM is not enabled, 2741 * the clocks and vdd will stay powered. 2742 */ 2743 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 2744 if (err) 2745 goto out_unregister_candev; 2746 2747 pm_runtime_put(ndev->dev.parent); 2748 2749 return 0; 2750 2751 out_unregister_candev: 2752 unregister_candev(ndev); 2753 out_chip_set_mode_sleep: 2754 mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 2755 out_runtime_disable: 2756 pm_runtime_disable(ndev->dev.parent); 2757 out_runtime_put_noidle: 2758 pm_runtime_put_noidle(ndev->dev.parent); 2759 mcp251xfd_clks_and_vdd_disable(priv); 2760 2761 return err; 2762 } 2763 2764 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv) 2765 { 2766 struct net_device *ndev = priv->ndev; 2767 2768 unregister_candev(ndev); 2769 2770 pm_runtime_get_sync(ndev->dev.parent); 2771 pm_runtime_put_noidle(ndev->dev.parent); 2772 mcp251xfd_clks_and_vdd_disable(priv); 2773 pm_runtime_disable(ndev->dev.parent); 2774 } 2775 2776 static const struct of_device_id mcp251xfd_of_match[] = { 2777 { 2778 .compatible = "microchip,mcp2517fd", 2779 .data = &mcp251xfd_devtype_data_mcp2517fd, 2780 }, { 2781 .compatible = "microchip,mcp2518fd", 2782 .data = &mcp251xfd_devtype_data_mcp2518fd, 2783 }, { 2784 .compatible = "microchip,mcp251xfd", 2785 .data = &mcp251xfd_devtype_data_mcp251xfd, 2786 }, { 2787 /* sentinel */ 2788 }, 2789 }; 2790 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match); 2791 2792 static const struct spi_device_id mcp251xfd_id_table[] = { 2793 { 2794 .name = "mcp2517fd", 2795 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd, 2796 }, { 2797 .name = "mcp2518fd", 2798 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd, 2799 }, { 2800 .name = "mcp251xfd", 2801 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd, 2802 }, { 2803 /* sentinel */ 2804 }, 2805 }; 2806 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table); 2807 2808 static int mcp251xfd_probe(struct spi_device *spi) 2809 { 2810 const void *match; 2811 struct net_device *ndev; 2812 struct mcp251xfd_priv *priv; 2813 struct gpio_desc *rx_int; 2814 struct regulator *reg_vdd, *reg_xceiver; 2815 struct clk *clk; 2816 u32 freq; 2817 int err; 2818 2819 if (!spi->irq) 2820 return dev_err_probe(&spi->dev, -ENXIO, 2821 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n"); 2822 2823 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int", 2824 GPIOD_IN); 2825 if (PTR_ERR(rx_int) == -EPROBE_DEFER) 2826 return -EPROBE_DEFER; 2827 else if (IS_ERR(rx_int)) 2828 return PTR_ERR(rx_int); 2829 2830 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd"); 2831 if (PTR_ERR(reg_vdd) == -EPROBE_DEFER) 2832 return -EPROBE_DEFER; 2833 else if (PTR_ERR(reg_vdd) == -ENODEV) 2834 reg_vdd = NULL; 2835 else if (IS_ERR(reg_vdd)) 2836 return PTR_ERR(reg_vdd); 2837 2838 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 2839 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) 2840 return -EPROBE_DEFER; 2841 else if (PTR_ERR(reg_xceiver) == -ENODEV) 2842 reg_xceiver = NULL; 2843 else if (IS_ERR(reg_xceiver)) 2844 return PTR_ERR(reg_xceiver); 2845 2846 clk = devm_clk_get(&spi->dev, NULL); 2847 if (IS_ERR(clk)) { 2848 dev_err(&spi->dev, "No Oscillator (clock) defined.\n"); 2849 return PTR_ERR(clk); 2850 } 2851 freq = clk_get_rate(clk); 2852 2853 /* Sanity check */ 2854 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN || 2855 freq > MCP251XFD_SYSCLOCK_HZ_MAX) { 2856 dev_err(&spi->dev, 2857 "Oscillator frequency (%u Hz) is too low or high.\n", 2858 freq); 2859 return -ERANGE; 2860 } 2861 2862 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER) { 2863 dev_err(&spi->dev, 2864 "Oscillator frequency (%u Hz) is too low and PLL is not supported.\n", 2865 freq); 2866 return -ERANGE; 2867 } 2868 2869 ndev = alloc_candev(sizeof(struct mcp251xfd_priv), 2870 MCP251XFD_TX_OBJ_NUM_MAX); 2871 if (!ndev) 2872 return -ENOMEM; 2873 2874 SET_NETDEV_DEV(ndev, &spi->dev); 2875 2876 ndev->netdev_ops = &mcp251xfd_netdev_ops; 2877 ndev->irq = spi->irq; 2878 ndev->flags |= IFF_ECHO; 2879 2880 priv = netdev_priv(ndev); 2881 spi_set_drvdata(spi, priv); 2882 priv->can.clock.freq = freq; 2883 priv->can.do_set_mode = mcp251xfd_set_mode; 2884 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter; 2885 priv->can.bittiming_const = &mcp251xfd_bittiming_const; 2886 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const; 2887 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 2888 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | 2889 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO; 2890 priv->ndev = ndev; 2891 priv->spi = spi; 2892 priv->rx_int = rx_int; 2893 priv->clk = clk; 2894 priv->reg_vdd = reg_vdd; 2895 priv->reg_xceiver = reg_xceiver; 2896 2897 match = device_get_match_data(&spi->dev); 2898 if (match) 2899 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match; 2900 else 2901 priv->devtype_data = *(struct mcp251xfd_devtype_data *) 2902 spi_get_device_id(spi)->driver_data; 2903 2904 /* Errata Reference: 2905 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 4. 2906 * 2907 * The SPI can write corrupted data to the RAM at fast SPI 2908 * speeds: 2909 * 2910 * Simultaneous activity on the CAN bus while writing data to 2911 * RAM via the SPI interface, with high SCK frequency, can 2912 * lead to corrupted data being written to RAM. 2913 * 2914 * Fix/Work Around: 2915 * Ensure that FSCK is less than or equal to 0.85 * 2916 * (FSYSCLK/2). 2917 * 2918 * Known good and bad combinations are: 2919 * 2920 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk Status config 2921 * 2922 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz good assigned-clocks = <&ccu CLK_SPIx> 2923 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 9375000 Hz 93.75% 600000000 Hz bad assigned-clocks = <&ccu CLK_SPIx> 2924 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz good assigned-clocks = <&ccu CLK_SPIx> 2925 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 18750000 Hz 93.75% 600000000 Hz bad assigned-clocks = <&ccu CLK_SPIx> 2926 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz good assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> 2927 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 9523809 Hz 95.34% 28571429 Hz bad assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> 2928 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz good default 2929 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz good default 2930 * 2931 */ 2932 priv->spi_max_speed_hz_orig = spi->max_speed_hz; 2933 spi->max_speed_hz = min(spi->max_speed_hz, freq / 2 / 1000 * 850); 2934 spi->bits_per_word = 8; 2935 spi->rt = true; 2936 err = spi_setup(spi); 2937 if (err) 2938 goto out_free_candev; 2939 2940 err = mcp251xfd_regmap_init(priv); 2941 if (err) 2942 goto out_free_candev; 2943 2944 err = can_rx_offload_add_manual(ndev, &priv->offload, 2945 MCP251XFD_NAPI_WEIGHT); 2946 if (err) 2947 goto out_free_candev; 2948 2949 err = mcp251xfd_register(priv); 2950 if (err) 2951 goto out_free_candev; 2952 2953 return 0; 2954 2955 out_free_candev: 2956 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2957 2958 free_candev(ndev); 2959 2960 return err; 2961 } 2962 2963 static int mcp251xfd_remove(struct spi_device *spi) 2964 { 2965 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 2966 struct net_device *ndev = priv->ndev; 2967 2968 can_rx_offload_del(&priv->offload); 2969 mcp251xfd_unregister(priv); 2970 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2971 free_candev(ndev); 2972 2973 return 0; 2974 } 2975 2976 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) 2977 { 2978 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2979 2980 return mcp251xfd_clks_and_vdd_disable(priv); 2981 } 2982 2983 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) 2984 { 2985 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2986 2987 return mcp251xfd_clks_and_vdd_enable(priv); 2988 } 2989 2990 static const struct dev_pm_ops mcp251xfd_pm_ops = { 2991 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend, 2992 mcp251xfd_runtime_resume, NULL) 2993 }; 2994 2995 static struct spi_driver mcp251xfd_driver = { 2996 .driver = { 2997 .name = DEVICE_NAME, 2998 .pm = &mcp251xfd_pm_ops, 2999 .of_match_table = mcp251xfd_of_match, 3000 }, 3001 .probe = mcp251xfd_probe, 3002 .remove = mcp251xfd_remove, 3003 .id_table = mcp251xfd_id_table, 3004 }; 3005 module_spi_driver(mcp251xfd_driver); 3006 3007 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 3008 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver"); 3009 MODULE_LICENSE("GPL v2"); 3010