1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mcp251xfd - Microchip MCP251xFD Family CAN controller driver 4 // 5 // Copyright (c) 2019, 2020, 2021 Pengutronix, 6 // Marc Kleine-Budde <kernel@pengutronix.de> 7 // 8 // Based on: 9 // 10 // CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface 11 // 12 // Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org> 13 // 14 15 #include <linux/bitfield.h> 16 #include <linux/clk.h> 17 #include <linux/device.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/module.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 23 #include "mcp251xfd.h" 24 25 #define DEVICE_NAME "mcp251xfd" 26 27 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = { 28 .quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG | 29 MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX | 30 MCP251XFD_QUIRK_ECC, 31 .model = MCP251XFD_MODEL_MCP2517FD, 32 }; 33 34 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = { 35 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 36 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 37 .model = MCP251XFD_MODEL_MCP2518FD, 38 }; 39 40 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = { 41 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 42 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 43 .model = MCP251XFD_MODEL_MCP251863, 44 }; 45 46 /* Autodetect model, start with CRC enabled. */ 47 static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = { 48 .quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX | 49 MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC, 50 .model = MCP251XFD_MODEL_MCP251XFD, 51 }; 52 53 static const struct can_bittiming_const mcp251xfd_bittiming_const = { 54 .name = DEVICE_NAME, 55 .tseg1_min = 2, 56 .tseg1_max = 256, 57 .tseg2_min = 1, 58 .tseg2_max = 128, 59 .sjw_max = 128, 60 .brp_min = 1, 61 .brp_max = 256, 62 .brp_inc = 1, 63 }; 64 65 static const struct can_bittiming_const mcp251xfd_data_bittiming_const = { 66 .name = DEVICE_NAME, 67 .tseg1_min = 1, 68 .tseg1_max = 32, 69 .tseg2_min = 1, 70 .tseg2_max = 16, 71 .sjw_max = 16, 72 .brp_min = 1, 73 .brp_max = 256, 74 .brp_inc = 1, 75 }; 76 77 static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model) 78 { 79 switch (model) { 80 case MCP251XFD_MODEL_MCP2517FD: 81 return "MCP2517FD"; 82 case MCP251XFD_MODEL_MCP2518FD: 83 return "MCP2518FD"; 84 case MCP251XFD_MODEL_MCP251863: 85 return "MCP251863"; 86 case MCP251XFD_MODEL_MCP251XFD: 87 return "MCP251xFD"; 88 } 89 90 return "<unknown>"; 91 } 92 93 static inline const char * 94 mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv) 95 { 96 return __mcp251xfd_get_model_str(priv->devtype_data.model); 97 } 98 99 static const char *mcp251xfd_get_mode_str(const u8 mode) 100 { 101 switch (mode) { 102 case MCP251XFD_REG_CON_MODE_MIXED: 103 return "Mixed (CAN FD/CAN 2.0)"; 104 case MCP251XFD_REG_CON_MODE_SLEEP: 105 return "Sleep"; 106 case MCP251XFD_REG_CON_MODE_INT_LOOPBACK: 107 return "Internal Loopback"; 108 case MCP251XFD_REG_CON_MODE_LISTENONLY: 109 return "Listen Only"; 110 case MCP251XFD_REG_CON_MODE_CONFIG: 111 return "Configuration"; 112 case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK: 113 return "External Loopback"; 114 case MCP251XFD_REG_CON_MODE_CAN2_0: 115 return "CAN 2.0"; 116 case MCP251XFD_REG_CON_MODE_RESTRICTED: 117 return "Restricted Operation"; 118 } 119 120 return "<unknown>"; 121 } 122 123 static const char * 124 mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference) 125 { 126 switch (~osc & osc_reference & 127 (MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) { 128 case MCP251XFD_REG_OSC_PLLRDY: 129 return "PLL"; 130 case MCP251XFD_REG_OSC_OSCRDY: 131 return "Oscillator"; 132 case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY: 133 return "Oscillator/PLL"; 134 } 135 136 return "<unknown>"; 137 } 138 139 static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv) 140 { 141 if (!priv->reg_vdd) 142 return 0; 143 144 return regulator_enable(priv->reg_vdd); 145 } 146 147 static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv) 148 { 149 if (!priv->reg_vdd) 150 return 0; 151 152 return regulator_disable(priv->reg_vdd); 153 } 154 155 static inline int 156 mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv) 157 { 158 if (!priv->reg_xceiver) 159 return 0; 160 161 return regulator_enable(priv->reg_xceiver); 162 } 163 164 static inline int 165 mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv) 166 { 167 if (!priv->reg_xceiver) 168 return 0; 169 170 return regulator_disable(priv->reg_xceiver); 171 } 172 173 static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv) 174 { 175 int err; 176 177 err = clk_prepare_enable(priv->clk); 178 if (err) 179 return err; 180 181 err = mcp251xfd_vdd_enable(priv); 182 if (err) 183 clk_disable_unprepare(priv->clk); 184 185 /* Wait for oscillator stabilisation time after power up */ 186 usleep_range(MCP251XFD_OSC_STAB_SLEEP_US, 187 2 * MCP251XFD_OSC_STAB_SLEEP_US); 188 189 return err; 190 } 191 192 static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv) 193 { 194 int err; 195 196 err = mcp251xfd_vdd_disable(priv); 197 if (err) 198 return err; 199 200 clk_disable_unprepare(priv->clk); 201 202 return 0; 203 } 204 205 static inline bool mcp251xfd_reg_invalid(u32 reg) 206 { 207 return reg == 0x0 || reg == 0xffffffff; 208 } 209 210 static inline int 211 mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode) 212 { 213 u32 val; 214 int err; 215 216 err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val); 217 if (err) 218 return err; 219 220 *mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val); 221 222 return 0; 223 } 224 225 static int 226 __mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 227 const u8 mode_req, bool nowait) 228 { 229 u32 con = 0, con_reqop, osc = 0; 230 u8 mode; 231 int err; 232 233 con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req); 234 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON, 235 MCP251XFD_REG_CON_REQOP_MASK, con_reqop); 236 if (err == -EBADMSG) { 237 netdev_err(priv->ndev, 238 "Failed to set Requested Operation Mode.\n"); 239 240 return -ENODEV; 241 } else if (err) { 242 return err; 243 } 244 245 if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait) 246 return 0; 247 248 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con, 249 !mcp251xfd_reg_invalid(con) && 250 FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, 251 con) == mode_req, 252 MCP251XFD_POLL_SLEEP_US, 253 MCP251XFD_POLL_TIMEOUT_US); 254 if (err != -ETIMEDOUT && err != -EBADMSG) 255 return err; 256 257 /* Ignore return value. 258 * Print below error messages, even if this fails. 259 */ 260 regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 261 262 if (mcp251xfd_reg_invalid(con)) { 263 netdev_err(priv->ndev, 264 "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n", 265 con, osc); 266 267 return -ENODEV; 268 } 269 270 mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con); 271 netdev_err(priv->ndev, 272 "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n", 273 mcp251xfd_get_mode_str(mode_req), mode_req, 274 mcp251xfd_get_mode_str(mode), mode, 275 con, osc); 276 277 return -ETIMEDOUT; 278 } 279 280 static inline int 281 mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, 282 const u8 mode_req) 283 { 284 return __mcp251xfd_chip_set_mode(priv, mode_req, false); 285 } 286 287 static inline int __maybe_unused 288 mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, 289 const u8 mode_req) 290 { 291 return __mcp251xfd_chip_set_mode(priv, mode_req, true); 292 } 293 294 static int 295 mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv, 296 u32 osc_reference, u32 osc_mask) 297 { 298 u32 osc; 299 int err; 300 301 err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc, 302 !mcp251xfd_reg_invalid(osc) && 303 (osc & osc_mask) == osc_reference, 304 MCP251XFD_OSC_STAB_SLEEP_US, 305 MCP251XFD_OSC_STAB_TIMEOUT_US); 306 if (err != -ETIMEDOUT) 307 return err; 308 309 if (mcp251xfd_reg_invalid(osc)) { 310 netdev_err(priv->ndev, 311 "Failed to read Oscillator Configuration Register (osc=0x%08x).\n", 312 osc); 313 return -ENODEV; 314 } 315 316 netdev_err(priv->ndev, 317 "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n", 318 mcp251xfd_get_osc_str(osc, osc_reference), 319 osc, osc_reference, osc_mask); 320 321 return -ETIMEDOUT; 322 } 323 324 static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv) 325 { 326 u32 osc, osc_reference, osc_mask; 327 int err; 328 329 /* For normal sleep on MCP2517FD and MCP2518FD, clearing 330 * "Oscillator Disable" will wake the chip. For low power mode 331 * on MCP2518FD, asserting the chip select will wake the 332 * chip. Writing to the Oscillator register will wake it in 333 * both cases. 334 */ 335 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 336 MCP251XFD_REG_OSC_CLKODIV_10); 337 338 /* We cannot check for the PLL ready bit (either set or 339 * unset), as the PLL might be enabled. This can happen if the 340 * system reboots, while the mcp251xfd stays powered. 341 */ 342 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 343 osc_mask = MCP251XFD_REG_OSC_OSCRDY; 344 345 /* If the controller is in Sleep Mode the following write only 346 * removes the "Oscillator Disable" bit and powers it up. All 347 * other bits are unaffected. 348 */ 349 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 350 if (err) 351 return err; 352 353 /* Sometimes the PLL is stuck enabled, the controller never 354 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our 355 * caller takes care of retry. 356 */ 357 return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 358 } 359 360 static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv) 361 { 362 if (priv->pll_enable) { 363 u32 osc; 364 int err; 365 366 /* Turn off PLL */ 367 osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 368 MCP251XFD_REG_OSC_CLKODIV_10); 369 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 370 if (err) 371 netdev_err(priv->ndev, 372 "Failed to disable PLL.\n"); 373 374 priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow; 375 } 376 377 return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP); 378 } 379 380 static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv) 381 { 382 const __be16 cmd = mcp251xfd_cmd_reset(); 383 int err; 384 385 /* The Set Mode and SPI Reset command only works if the 386 * controller is not in Sleep Mode. 387 */ 388 err = mcp251xfd_chip_wake(priv); 389 if (err) 390 return err; 391 392 err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG); 393 if (err) 394 return err; 395 396 /* spi_write_then_read() works with non DMA-safe buffers */ 397 return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0); 398 } 399 400 static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv) 401 { 402 u32 osc_reference, osc_mask; 403 u8 mode; 404 int err; 405 406 /* Check for reset defaults of OSC reg. 407 * This will take care of stabilization period. 408 */ 409 osc_reference = MCP251XFD_REG_OSC_OSCRDY | 410 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 411 MCP251XFD_REG_OSC_CLKODIV_10); 412 osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY; 413 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 414 if (err) 415 return err; 416 417 err = mcp251xfd_chip_get_mode(priv, &mode); 418 if (err) 419 return err; 420 421 if (mode != MCP251XFD_REG_CON_MODE_CONFIG) { 422 netdev_info(priv->ndev, 423 "Controller not in Config Mode after reset, but in %s Mode (%u).\n", 424 mcp251xfd_get_mode_str(mode), mode); 425 return -ETIMEDOUT; 426 } 427 428 return 0; 429 } 430 431 static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv) 432 { 433 int err, i; 434 435 for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) { 436 if (i) 437 netdev_info(priv->ndev, 438 "Retrying to reset controller.\n"); 439 440 err = mcp251xfd_chip_softreset_do(priv); 441 if (err == -ETIMEDOUT) 442 continue; 443 if (err) 444 return err; 445 446 err = mcp251xfd_chip_softreset_check(priv); 447 if (err == -ETIMEDOUT) 448 continue; 449 if (err) 450 return err; 451 452 return 0; 453 } 454 455 return err; 456 } 457 458 static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv) 459 { 460 u32 osc, osc_reference, osc_mask; 461 int err; 462 463 /* Activate Low Power Mode on Oscillator Disable. This only 464 * works on the MCP2518FD. The MCP2517FD will go into normal 465 * Sleep Mode instead. 466 */ 467 osc = MCP251XFD_REG_OSC_LPMEN | 468 FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK, 469 MCP251XFD_REG_OSC_CLKODIV_10); 470 osc_reference = MCP251XFD_REG_OSC_OSCRDY; 471 osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY; 472 473 if (priv->pll_enable) { 474 osc |= MCP251XFD_REG_OSC_PLLEN; 475 osc_reference |= MCP251XFD_REG_OSC_PLLRDY; 476 } 477 478 err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc); 479 if (err) 480 return err; 481 482 err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask); 483 if (err) 484 return err; 485 486 priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast; 487 488 return 0; 489 } 490 491 static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv) 492 { 493 /* Set Time Base Counter Prescaler to 1. 494 * 495 * This means an overflow of the 32 bit Time Base Counter 496 * register at 40 MHz every 107 seconds. 497 */ 498 return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON, 499 MCP251XFD_REG_TSCON_TBCEN); 500 } 501 502 static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv) 503 { 504 const struct can_bittiming *bt = &priv->can.bittiming; 505 const struct can_bittiming *dbt = &priv->can.data_bittiming; 506 u32 val = 0; 507 s8 tdco; 508 int err; 509 510 /* CAN Control Register 511 * 512 * - no transmit bandwidth sharing 513 * - config mode 514 * - disable transmit queue 515 * - store in transmit FIFO event 516 * - transition to restricted operation mode on system error 517 * - ESI is transmitted recessive when ESI of message is high or 518 * CAN controller error passive 519 * - restricted retransmission attempts, 520 * use TQXCON_TXAT and FIFOCON_TXAT 521 * - wake-up filter bits T11FILTER 522 * - use CAN bus line filter for wakeup 523 * - protocol exception is treated as a form error 524 * - Do not compare data bytes 525 */ 526 val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, 527 MCP251XFD_REG_CON_MODE_CONFIG) | 528 MCP251XFD_REG_CON_STEF | 529 MCP251XFD_REG_CON_ESIGM | 530 MCP251XFD_REG_CON_RTXAT | 531 FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK, 532 MCP251XFD_REG_CON_WFT_T11FILTER) | 533 MCP251XFD_REG_CON_WAKFIL | 534 MCP251XFD_REG_CON_PXEDIS; 535 536 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 537 val |= MCP251XFD_REG_CON_ISOCRCEN; 538 539 err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val); 540 if (err) 541 return err; 542 543 /* Nominal Bit Time */ 544 val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) | 545 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK, 546 bt->prop_seg + bt->phase_seg1 - 1) | 547 FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK, 548 bt->phase_seg2 - 1) | 549 FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1); 550 551 err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val); 552 if (err) 553 return err; 554 555 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD)) 556 return 0; 557 558 /* Data Bit Time */ 559 val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) | 560 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK, 561 dbt->prop_seg + dbt->phase_seg1 - 1) | 562 FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK, 563 dbt->phase_seg2 - 1) | 564 FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1); 565 566 err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val); 567 if (err) 568 return err; 569 570 /* Transmitter Delay Compensation */ 571 tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1), 572 -64, 63); 573 val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK, 574 MCP251XFD_REG_TDC_TDCMOD_AUTO) | 575 FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco); 576 577 return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val); 578 } 579 580 static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv) 581 { 582 u32 val; 583 584 if (!priv->rx_int) 585 return 0; 586 587 /* Configure GPIOs: 588 * - PIN0: GPIO Input 589 * - PIN1: GPIO Input/RX Interrupt 590 * 591 * PIN1 must be Input, otherwise there is a glitch on the 592 * rx-INT line. It happens between setting the PIN as output 593 * (in the first byte of the SPI transfer) and configuring the 594 * PIN as interrupt (in the last byte of the SPI transfer). 595 */ 596 val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 | 597 MCP251XFD_REG_IOCON_TRIS0; 598 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 599 } 600 601 static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv) 602 { 603 u32 val; 604 605 if (!priv->rx_int) 606 return 0; 607 608 /* Configure GPIOs: 609 * - PIN0: GPIO Input 610 * - PIN1: GPIO Input 611 */ 612 val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 | 613 MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0; 614 return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val); 615 } 616 617 static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv) 618 { 619 struct mcp251xfd_ecc *ecc = &priv->ecc; 620 void *ram; 621 u32 val = 0; 622 int err; 623 624 ecc->ecc_stat = 0; 625 626 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC) 627 val = MCP251XFD_REG_ECCCON_ECCEN; 628 629 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 630 MCP251XFD_REG_ECCCON_ECCEN, val); 631 if (err) 632 return err; 633 634 ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL); 635 if (!ram) 636 return -ENOMEM; 637 638 err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram, 639 MCP251XFD_RAM_SIZE); 640 kfree(ram); 641 642 return err; 643 } 644 645 static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv) 646 { 647 u8 mode; 648 649 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 650 mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK; 651 else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 652 mode = MCP251XFD_REG_CON_MODE_LISTENONLY; 653 else if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 654 mode = MCP251XFD_REG_CON_MODE_MIXED; 655 else 656 mode = MCP251XFD_REG_CON_MODE_CAN2_0; 657 658 return mode; 659 } 660 661 static int 662 __mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv, 663 bool nowait) 664 { 665 u8 mode; 666 667 mode = mcp251xfd_get_normal_mode(priv); 668 669 return __mcp251xfd_chip_set_mode(priv, mode, nowait); 670 } 671 672 static inline int 673 mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv) 674 { 675 return __mcp251xfd_chip_set_normal_mode(priv, false); 676 } 677 678 static inline int 679 mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv) 680 { 681 return __mcp251xfd_chip_set_normal_mode(priv, true); 682 } 683 684 static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv) 685 { 686 u32 val; 687 int err; 688 689 val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE; 690 err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val); 691 if (err) 692 return err; 693 694 val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 695 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val); 696 if (err) 697 return err; 698 699 val = MCP251XFD_REG_INT_CERRIE | 700 MCP251XFD_REG_INT_SERRIE | 701 MCP251XFD_REG_INT_RXOVIE | 702 MCP251XFD_REG_INT_TXATIE | 703 MCP251XFD_REG_INT_SPICRCIE | 704 MCP251XFD_REG_INT_ECCIE | 705 MCP251XFD_REG_INT_TEFIE | 706 MCP251XFD_REG_INT_MODIE | 707 MCP251XFD_REG_INT_RXIE; 708 709 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 710 val |= MCP251XFD_REG_INT_IVMIE; 711 712 return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val); 713 } 714 715 static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv) 716 { 717 int err; 718 u32 mask; 719 720 err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0); 721 if (err) 722 return err; 723 724 mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE; 725 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, 726 mask, 0x0); 727 if (err) 728 return err; 729 730 return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0); 731 } 732 733 static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv, 734 const enum can_state state) 735 { 736 priv->can.state = state; 737 738 mcp251xfd_chip_interrupts_disable(priv); 739 mcp251xfd_chip_rx_int_disable(priv); 740 mcp251xfd_chip_sleep(priv); 741 } 742 743 static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv) 744 { 745 int err; 746 747 err = mcp251xfd_chip_softreset(priv); 748 if (err) 749 goto out_chip_stop; 750 751 err = mcp251xfd_chip_clock_init(priv); 752 if (err) 753 goto out_chip_stop; 754 755 err = mcp251xfd_chip_timestamp_init(priv); 756 if (err) 757 goto out_chip_stop; 758 759 err = mcp251xfd_set_bittiming(priv); 760 if (err) 761 goto out_chip_stop; 762 763 err = mcp251xfd_chip_rx_int_enable(priv); 764 if (err) 765 goto out_chip_stop; 766 767 err = mcp251xfd_chip_ecc_init(priv); 768 if (err) 769 goto out_chip_stop; 770 771 err = mcp251xfd_ring_init(priv); 772 if (err) 773 goto out_chip_stop; 774 775 err = mcp251xfd_chip_fifo_init(priv); 776 if (err) 777 goto out_chip_stop; 778 779 priv->can.state = CAN_STATE_ERROR_ACTIVE; 780 781 err = mcp251xfd_chip_set_normal_mode(priv); 782 if (err) 783 goto out_chip_stop; 784 785 return 0; 786 787 out_chip_stop: 788 mcp251xfd_dump(priv); 789 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 790 791 return err; 792 } 793 794 static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode) 795 { 796 struct mcp251xfd_priv *priv = netdev_priv(ndev); 797 int err; 798 799 switch (mode) { 800 case CAN_MODE_START: 801 err = mcp251xfd_chip_start(priv); 802 if (err) 803 return err; 804 805 err = mcp251xfd_chip_interrupts_enable(priv); 806 if (err) { 807 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 808 return err; 809 } 810 811 netif_wake_queue(ndev); 812 break; 813 814 default: 815 return -EOPNOTSUPP; 816 } 817 818 return 0; 819 } 820 821 static int __mcp251xfd_get_berr_counter(const struct net_device *ndev, 822 struct can_berr_counter *bec) 823 { 824 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 825 u32 trec; 826 int err; 827 828 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 829 if (err) 830 return err; 831 832 if (trec & MCP251XFD_REG_TREC_TXBO) 833 bec->txerr = 256; 834 else 835 bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec); 836 bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec); 837 838 return 0; 839 } 840 841 static int mcp251xfd_get_berr_counter(const struct net_device *ndev, 842 struct can_berr_counter *bec) 843 { 844 const struct mcp251xfd_priv *priv = netdev_priv(ndev); 845 846 /* Avoid waking up the controller if the interface is down */ 847 if (!(ndev->flags & IFF_UP)) 848 return 0; 849 850 /* The controller is powered down during Bus Off, use saved 851 * bec values. 852 */ 853 if (priv->can.state == CAN_STATE_BUS_OFF) { 854 *bec = priv->bec; 855 return 0; 856 } 857 858 return __mcp251xfd_get_berr_counter(ndev, bec); 859 } 860 861 static struct sk_buff * 862 mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv, 863 struct can_frame **cf, u32 *timestamp) 864 { 865 struct sk_buff *skb; 866 int err; 867 868 err = mcp251xfd_get_timestamp(priv, timestamp); 869 if (err) 870 return NULL; 871 872 skb = alloc_can_err_skb(priv->ndev, cf); 873 if (skb) 874 mcp251xfd_skb_set_timestamp(priv, skb, *timestamp); 875 876 return skb; 877 } 878 879 static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv) 880 { 881 struct net_device_stats *stats = &priv->ndev->stats; 882 struct mcp251xfd_rx_ring *ring; 883 struct sk_buff *skb; 884 struct can_frame *cf; 885 u32 timestamp, rxovif; 886 int err, i; 887 888 stats->rx_over_errors++; 889 stats->rx_errors++; 890 891 err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif); 892 if (err) 893 return err; 894 895 mcp251xfd_for_each_rx_ring(priv, ring, i) { 896 if (!(rxovif & BIT(ring->fifo_nr))) 897 continue; 898 899 /* If SERRIF is active, there was a RX MAB overflow. */ 900 if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) { 901 if (net_ratelimit()) 902 netdev_dbg(priv->ndev, 903 "RX-%d: MAB overflow detected.\n", 904 ring->nr); 905 } else { 906 if (net_ratelimit()) 907 netdev_dbg(priv->ndev, 908 "RX-%d: FIFO overflow.\n", 909 ring->nr); 910 } 911 912 err = regmap_update_bits(priv->map_reg, 913 MCP251XFD_REG_FIFOSTA(ring->fifo_nr), 914 MCP251XFD_REG_FIFOSTA_RXOVIF, 915 0x0); 916 if (err) 917 return err; 918 } 919 920 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 921 if (!skb) 922 return 0; 923 924 cf->can_id |= CAN_ERR_CRTL; 925 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 926 927 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 928 if (err) 929 stats->rx_fifo_errors++; 930 931 return 0; 932 } 933 934 static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv) 935 { 936 netdev_info(priv->ndev, "%s\n", __func__); 937 938 return 0; 939 } 940 941 static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv) 942 { 943 struct net_device_stats *stats = &priv->ndev->stats; 944 u32 bdiag1, timestamp; 945 struct sk_buff *skb; 946 struct can_frame *cf = NULL; 947 int err; 948 949 err = mcp251xfd_get_timestamp(priv, ×tamp); 950 if (err) 951 return err; 952 953 err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1); 954 if (err) 955 return err; 956 957 /* Write 0s to clear error bits, don't write 1s to non active 958 * bits, as they will be set. 959 */ 960 err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0); 961 if (err) 962 return err; 963 964 priv->can.can_stats.bus_error++; 965 966 skb = alloc_can_err_skb(priv->ndev, &cf); 967 if (cf) 968 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 969 970 /* Controller misconfiguration */ 971 if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM)) 972 netdev_err(priv->ndev, 973 "recv'd DLC is larger than PLSIZE of FIFO element."); 974 975 /* RX errors */ 976 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR | 977 MCP251XFD_REG_BDIAG1_NCRCERR)) { 978 netdev_dbg(priv->ndev, "CRC error\n"); 979 980 stats->rx_errors++; 981 if (cf) 982 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; 983 } 984 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR | 985 MCP251XFD_REG_BDIAG1_NSTUFERR)) { 986 netdev_dbg(priv->ndev, "Stuff error\n"); 987 988 stats->rx_errors++; 989 if (cf) 990 cf->data[2] |= CAN_ERR_PROT_STUFF; 991 } 992 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR | 993 MCP251XFD_REG_BDIAG1_NFORMERR)) { 994 netdev_dbg(priv->ndev, "Format error\n"); 995 996 stats->rx_errors++; 997 if (cf) 998 cf->data[2] |= CAN_ERR_PROT_FORM; 999 } 1000 1001 /* TX errors */ 1002 if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) { 1003 netdev_dbg(priv->ndev, "NACK error\n"); 1004 1005 stats->tx_errors++; 1006 if (cf) { 1007 cf->can_id |= CAN_ERR_ACK; 1008 cf->data[2] |= CAN_ERR_PROT_TX; 1009 } 1010 } 1011 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR | 1012 MCP251XFD_REG_BDIAG1_NBIT1ERR)) { 1013 netdev_dbg(priv->ndev, "Bit1 error\n"); 1014 1015 stats->tx_errors++; 1016 if (cf) 1017 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1; 1018 } 1019 if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR | 1020 MCP251XFD_REG_BDIAG1_NBIT0ERR)) { 1021 netdev_dbg(priv->ndev, "Bit0 error\n"); 1022 1023 stats->tx_errors++; 1024 if (cf) 1025 cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0; 1026 } 1027 1028 if (!cf) 1029 return 0; 1030 1031 mcp251xfd_skb_set_timestamp(priv, skb, timestamp); 1032 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 1033 if (err) 1034 stats->rx_fifo_errors++; 1035 1036 return 0; 1037 } 1038 1039 static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv) 1040 { 1041 struct net_device_stats *stats = &priv->ndev->stats; 1042 struct sk_buff *skb; 1043 struct can_frame *cf = NULL; 1044 enum can_state new_state, rx_state, tx_state; 1045 u32 trec, timestamp; 1046 int err; 1047 1048 err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec); 1049 if (err) 1050 return err; 1051 1052 if (trec & MCP251XFD_REG_TREC_TXBO) 1053 tx_state = CAN_STATE_BUS_OFF; 1054 else if (trec & MCP251XFD_REG_TREC_TXBP) 1055 tx_state = CAN_STATE_ERROR_PASSIVE; 1056 else if (trec & MCP251XFD_REG_TREC_TXWARN) 1057 tx_state = CAN_STATE_ERROR_WARNING; 1058 else 1059 tx_state = CAN_STATE_ERROR_ACTIVE; 1060 1061 if (trec & MCP251XFD_REG_TREC_RXBP) 1062 rx_state = CAN_STATE_ERROR_PASSIVE; 1063 else if (trec & MCP251XFD_REG_TREC_RXWARN) 1064 rx_state = CAN_STATE_ERROR_WARNING; 1065 else 1066 rx_state = CAN_STATE_ERROR_ACTIVE; 1067 1068 new_state = max(tx_state, rx_state); 1069 if (new_state == priv->can.state) 1070 return 0; 1071 1072 /* The skb allocation might fail, but can_change_state() 1073 * handles cf == NULL. 1074 */ 1075 skb = mcp251xfd_alloc_can_err_skb(priv, &cf, ×tamp); 1076 can_change_state(priv->ndev, cf, tx_state, rx_state); 1077 1078 if (new_state == CAN_STATE_BUS_OFF) { 1079 /* As we're going to switch off the chip now, let's 1080 * save the error counters and return them to 1081 * userspace, if do_get_berr_counter() is called while 1082 * the chip is in Bus Off. 1083 */ 1084 err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec); 1085 if (err) 1086 return err; 1087 1088 mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF); 1089 can_bus_off(priv->ndev); 1090 } 1091 1092 if (!skb) 1093 return 0; 1094 1095 if (new_state != CAN_STATE_BUS_OFF) { 1096 struct can_berr_counter bec; 1097 1098 err = mcp251xfd_get_berr_counter(priv->ndev, &bec); 1099 if (err) 1100 return err; 1101 cf->data[6] = bec.txerr; 1102 cf->data[7] = bec.rxerr; 1103 } 1104 1105 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 1106 if (err) 1107 stats->rx_fifo_errors++; 1108 1109 return 0; 1110 } 1111 1112 static int 1113 mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode) 1114 { 1115 const u8 mode_reference = mcp251xfd_get_normal_mode(priv); 1116 u8 mode; 1117 int err; 1118 1119 err = mcp251xfd_chip_get_mode(priv, &mode); 1120 if (err) 1121 return err; 1122 1123 if (mode == mode_reference) { 1124 netdev_dbg(priv->ndev, 1125 "Controller changed into %s Mode (%u).\n", 1126 mcp251xfd_get_mode_str(mode), mode); 1127 return 0; 1128 } 1129 1130 /* According to MCP2517FD errata DS80000792B 1., during a TX 1131 * MAB underflow, the controller will transition to Restricted 1132 * Operation Mode or Listen Only Mode (depending on SERR2LOM). 1133 * 1134 * However this is not always the case. If SERR2LOM is 1135 * configured for Restricted Operation Mode (SERR2LOM not set) 1136 * the MCP2517FD will sometimes transition to Listen Only Mode 1137 * first. When polling this bit we see that it will transition 1138 * to Restricted Operation Mode shortly after. 1139 */ 1140 if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) && 1141 (mode == MCP251XFD_REG_CON_MODE_RESTRICTED || 1142 mode == MCP251XFD_REG_CON_MODE_LISTENONLY)) 1143 netdev_dbg(priv->ndev, 1144 "Controller changed into %s Mode (%u).\n", 1145 mcp251xfd_get_mode_str(mode), mode); 1146 else 1147 netdev_err(priv->ndev, 1148 "Controller changed into %s Mode (%u).\n", 1149 mcp251xfd_get_mode_str(mode), mode); 1150 1151 /* After the application requests Normal mode, the controller 1152 * will automatically attempt to retransmit the message that 1153 * caused the TX MAB underflow. 1154 * 1155 * However, if there is an ECC error in the TX-RAM, we first 1156 * have to reload the tx-object before requesting Normal 1157 * mode. This is done later in mcp251xfd_handle_eccif(). 1158 */ 1159 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) { 1160 *set_normal_mode = true; 1161 return 0; 1162 } 1163 1164 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1165 } 1166 1167 static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv) 1168 { 1169 struct mcp251xfd_ecc *ecc = &priv->ecc; 1170 struct net_device_stats *stats = &priv->ndev->stats; 1171 bool handled = false; 1172 1173 /* TX MAB underflow 1174 * 1175 * According to MCP2517FD Errata DS80000792B 1. a TX MAB 1176 * underflow is indicated by SERRIF and MODIF. 1177 * 1178 * In addition to the effects mentioned in the Errata, there 1179 * are Bus Errors due to the aborted CAN frame, so a IVMIF 1180 * will be seen as well. 1181 * 1182 * Sometimes there is an ECC error in the TX-RAM, which leads 1183 * to a TX MAB underflow. 1184 * 1185 * However, probably due to a race condition, there is no 1186 * associated MODIF pending. 1187 * 1188 * Further, there are situations, where the SERRIF is caused 1189 * by an ECC error in the TX-RAM, but not even the ECCIF is 1190 * set. This only seems to happen _after_ the first occurrence 1191 * of a ECCIF (which is tracked in ecc->cnt). 1192 * 1193 * Treat all as a known system errors.. 1194 */ 1195 if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF && 1196 priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) || 1197 priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1198 ecc->cnt) { 1199 const char *msg; 1200 1201 if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF || 1202 ecc->cnt) 1203 msg = "TX MAB underflow due to ECC error detected."; 1204 else 1205 msg = "TX MAB underflow detected."; 1206 1207 if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) 1208 netdev_dbg(priv->ndev, "%s\n", msg); 1209 else 1210 netdev_info(priv->ndev, "%s\n", msg); 1211 1212 stats->tx_aborted_errors++; 1213 stats->tx_errors++; 1214 handled = true; 1215 } 1216 1217 /* RX MAB overflow 1218 * 1219 * According to MCP2517FD Errata DS80000792B 1. a RX MAB 1220 * overflow is indicated by SERRIF. 1221 * 1222 * In addition to the effects mentioned in the Errata, (most 1223 * of the times) a RXOVIF is raised, if the FIFO that is being 1224 * received into has the RXOVIE activated (and we have enabled 1225 * RXOVIE on all FIFOs). 1226 * 1227 * Sometimes there is no RXOVIF just a RXIF is pending. 1228 * 1229 * Treat all as a known system errors.. 1230 */ 1231 if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF || 1232 priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) { 1233 stats->rx_dropped++; 1234 handled = true; 1235 } 1236 1237 if (!handled) 1238 netdev_err(priv->ndev, 1239 "Unhandled System Error Interrupt (intf=0x%08x)!\n", 1240 priv->regs_status.intf); 1241 1242 return 0; 1243 } 1244 1245 static int 1246 mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr) 1247 { 1248 struct mcp251xfd_tx_ring *tx_ring = priv->tx; 1249 struct mcp251xfd_ecc *ecc = &priv->ecc; 1250 struct mcp251xfd_tx_obj *tx_obj; 1251 u8 chip_tx_tail, tx_tail, offset; 1252 u16 addr; 1253 int err; 1254 1255 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat); 1256 1257 err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail); 1258 if (err) 1259 return err; 1260 1261 tx_tail = mcp251xfd_get_tx_tail(tx_ring); 1262 offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1); 1263 1264 /* Bail out if one of the following is met: 1265 * - tx_tail information is inconsistent 1266 * - for mcp2517fd: offset not 0 1267 * - for mcp2518fd: offset not 0 or 1 1268 */ 1269 if (chip_tx_tail != tx_tail || 1270 !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) || 1271 mcp251xfd_is_251863(priv))))) { 1272 netdev_err(priv->ndev, 1273 "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n", 1274 addr, nr, tx_ring->tail, tx_tail, chip_tx_tail, 1275 offset); 1276 return -EINVAL; 1277 } 1278 1279 netdev_info(priv->ndev, 1280 "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n", 1281 ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ? 1282 "Single" : "Double", 1283 addr, nr, tx_ring->tail, tx_tail, offset); 1284 1285 /* reload tx_obj into controller RAM ... */ 1286 tx_obj = &tx_ring->obj[nr]; 1287 err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1); 1288 if (err) 1289 return err; 1290 1291 /* ... and trigger retransmit */ 1292 return mcp251xfd_chip_set_normal_mode(priv); 1293 } 1294 1295 static int 1296 mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode) 1297 { 1298 struct mcp251xfd_ecc *ecc = &priv->ecc; 1299 const char *msg; 1300 bool in_tx_ram; 1301 u32 ecc_stat; 1302 u16 addr; 1303 u8 nr; 1304 int err; 1305 1306 err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat); 1307 if (err) 1308 return err; 1309 1310 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT, 1311 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat); 1312 if (err) 1313 return err; 1314 1315 /* Check if ECC error occurred in TX-RAM */ 1316 addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat); 1317 err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr); 1318 if (!err) 1319 in_tx_ram = true; 1320 else if (err == -ENOENT) 1321 in_tx_ram = false; 1322 else 1323 return err; 1324 1325 /* Errata Reference: 1326 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2. 1327 * 1328 * ECC single error correction does not work in all cases: 1329 * 1330 * Fix/Work Around: 1331 * Enable single error correction and double error detection 1332 * interrupts by setting SECIE and DEDIE. Handle SECIF as a 1333 * detection interrupt and do not rely on the error 1334 * correction. Instead, handle both interrupts as a 1335 * notification that the RAM word at ERRADDR was corrupted. 1336 */ 1337 if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF) 1338 msg = "Single ECC Error detected at address"; 1339 else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF) 1340 msg = "Double ECC Error detected at address"; 1341 else 1342 return -EINVAL; 1343 1344 if (!in_tx_ram) { 1345 ecc->ecc_stat = 0; 1346 1347 netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr); 1348 } else { 1349 /* Re-occurring error? */ 1350 if (ecc->ecc_stat == ecc_stat) { 1351 ecc->cnt++; 1352 } else { 1353 ecc->ecc_stat = ecc_stat; 1354 ecc->cnt = 1; 1355 } 1356 1357 netdev_info(priv->ndev, 1358 "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n", 1359 msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : ""); 1360 1361 if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX) 1362 return mcp251xfd_handle_eccif_recover(priv, nr); 1363 } 1364 1365 if (set_normal_mode) 1366 return mcp251xfd_chip_set_normal_mode_nowait(priv); 1367 1368 return 0; 1369 } 1370 1371 static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv) 1372 { 1373 int err; 1374 u32 crc; 1375 1376 err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc); 1377 if (err) 1378 return err; 1379 1380 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC, 1381 MCP251XFD_REG_CRC_IF_MASK, 1382 ~crc); 1383 if (err) 1384 return err; 1385 1386 if (crc & MCP251XFD_REG_CRC_FERRIF) 1387 netdev_notice(priv->ndev, "CRC write command format error.\n"); 1388 else if (crc & MCP251XFD_REG_CRC_CRCERRIF) 1389 netdev_notice(priv->ndev, 1390 "CRC write error detected. CRC=0x%04lx.\n", 1391 FIELD_GET(MCP251XFD_REG_CRC_MASK, crc)); 1392 1393 return 0; 1394 } 1395 1396 static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv) 1397 { 1398 const int val_bytes = regmap_get_val_bytes(priv->map_reg); 1399 size_t len; 1400 1401 if (priv->rx_ring_num == 1) 1402 len = sizeof(priv->regs_status.intf); 1403 else 1404 len = sizeof(priv->regs_status); 1405 1406 return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT, 1407 &priv->regs_status, len / val_bytes); 1408 } 1409 1410 #define mcp251xfd_handle(priv, irq, ...) \ 1411 ({ \ 1412 struct mcp251xfd_priv *_priv = (priv); \ 1413 int err; \ 1414 \ 1415 err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \ 1416 if (err) \ 1417 netdev_err(_priv->ndev, \ 1418 "IRQ handler mcp251xfd_handle_%s() returned %d.\n", \ 1419 __stringify(irq), err); \ 1420 err; \ 1421 }) 1422 1423 static irqreturn_t mcp251xfd_irq(int irq, void *dev_id) 1424 { 1425 struct mcp251xfd_priv *priv = dev_id; 1426 irqreturn_t handled = IRQ_NONE; 1427 int err; 1428 1429 if (priv->rx_int) 1430 do { 1431 int rx_pending; 1432 1433 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1434 if (!rx_pending) 1435 break; 1436 1437 /* Assume 1st RX-FIFO pending, if other FIFOs 1438 * are pending the main IRQ handler will take 1439 * care. 1440 */ 1441 priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr); 1442 err = mcp251xfd_handle(priv, rxif); 1443 if (err) 1444 goto out_fail; 1445 1446 handled = IRQ_HANDLED; 1447 1448 /* We don't know which RX-FIFO is pending, but only 1449 * handle the 1st RX-FIFO. Leave loop here if we have 1450 * more than 1 RX-FIFO to avoid starvation. 1451 */ 1452 } while (priv->rx_ring_num == 1); 1453 1454 do { 1455 u32 intf_pending, intf_pending_clearable; 1456 bool set_normal_mode = false; 1457 1458 err = mcp251xfd_read_regs_status(priv); 1459 if (err) 1460 goto out_fail; 1461 1462 intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK, 1463 priv->regs_status.intf) & 1464 FIELD_GET(MCP251XFD_REG_INT_IE_MASK, 1465 priv->regs_status.intf); 1466 1467 if (!(intf_pending)) { 1468 can_rx_offload_threaded_irq_finish(&priv->offload); 1469 return handled; 1470 } 1471 1472 /* Some interrupts must be ACKed in the 1473 * MCP251XFD_REG_INT register. 1474 * - First ACK then handle, to avoid lost-IRQ race 1475 * condition on fast re-occurring interrupts. 1476 * - Write "0" to clear active IRQs, "1" to all other, 1477 * to avoid r/m/w race condition on the 1478 * MCP251XFD_REG_INT register. 1479 */ 1480 intf_pending_clearable = intf_pending & 1481 MCP251XFD_REG_INT_IF_CLEARABLE_MASK; 1482 if (intf_pending_clearable) { 1483 err = regmap_update_bits(priv->map_reg, 1484 MCP251XFD_REG_INT, 1485 MCP251XFD_REG_INT_IF_MASK, 1486 ~intf_pending_clearable); 1487 if (err) 1488 goto out_fail; 1489 } 1490 1491 if (intf_pending & MCP251XFD_REG_INT_MODIF) { 1492 err = mcp251xfd_handle(priv, modif, &set_normal_mode); 1493 if (err) 1494 goto out_fail; 1495 } 1496 1497 if (intf_pending & MCP251XFD_REG_INT_RXIF) { 1498 err = mcp251xfd_handle(priv, rxif); 1499 if (err) 1500 goto out_fail; 1501 } 1502 1503 if (intf_pending & MCP251XFD_REG_INT_TEFIF) { 1504 err = mcp251xfd_handle(priv, tefif); 1505 if (err) 1506 goto out_fail; 1507 } 1508 1509 if (intf_pending & MCP251XFD_REG_INT_RXOVIF) { 1510 err = mcp251xfd_handle(priv, rxovif); 1511 if (err) 1512 goto out_fail; 1513 } 1514 1515 if (intf_pending & MCP251XFD_REG_INT_TXATIF) { 1516 err = mcp251xfd_handle(priv, txatif); 1517 if (err) 1518 goto out_fail; 1519 } 1520 1521 if (intf_pending & MCP251XFD_REG_INT_IVMIF) { 1522 err = mcp251xfd_handle(priv, ivmif); 1523 if (err) 1524 goto out_fail; 1525 } 1526 1527 if (intf_pending & MCP251XFD_REG_INT_SERRIF) { 1528 err = mcp251xfd_handle(priv, serrif); 1529 if (err) 1530 goto out_fail; 1531 } 1532 1533 if (intf_pending & MCP251XFD_REG_INT_ECCIF) { 1534 err = mcp251xfd_handle(priv, eccif, set_normal_mode); 1535 if (err) 1536 goto out_fail; 1537 } 1538 1539 if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) { 1540 err = mcp251xfd_handle(priv, spicrcif); 1541 if (err) 1542 goto out_fail; 1543 } 1544 1545 /* On the MCP2527FD and MCP2518FD, we don't get a 1546 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX 1547 * ERROR_ACTIVE. 1548 */ 1549 if (intf_pending & MCP251XFD_REG_INT_CERRIF || 1550 priv->can.state > CAN_STATE_ERROR_ACTIVE) { 1551 err = mcp251xfd_handle(priv, cerrif); 1552 if (err) 1553 goto out_fail; 1554 1555 /* In Bus Off we completely shut down the 1556 * controller. Every subsequent register read 1557 * will read bogus data, and if 1558 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC 1559 * check will fail, too. So leave IRQ handler 1560 * directly. 1561 */ 1562 if (priv->can.state == CAN_STATE_BUS_OFF) { 1563 can_rx_offload_threaded_irq_finish(&priv->offload); 1564 return IRQ_HANDLED; 1565 } 1566 } 1567 1568 handled = IRQ_HANDLED; 1569 } while (1); 1570 1571 out_fail: 1572 can_rx_offload_threaded_irq_finish(&priv->offload); 1573 1574 netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n", 1575 err, priv->regs_status.intf); 1576 mcp251xfd_dump(priv); 1577 mcp251xfd_chip_interrupts_disable(priv); 1578 mcp251xfd_timestamp_stop(priv); 1579 1580 return handled; 1581 } 1582 1583 static int mcp251xfd_open(struct net_device *ndev) 1584 { 1585 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1586 const struct spi_device *spi = priv->spi; 1587 int err; 1588 1589 err = open_candev(ndev); 1590 if (err) 1591 return err; 1592 1593 err = pm_runtime_resume_and_get(ndev->dev.parent); 1594 if (err) 1595 goto out_close_candev; 1596 1597 err = mcp251xfd_ring_alloc(priv); 1598 if (err) 1599 goto out_pm_runtime_put; 1600 1601 err = mcp251xfd_transceiver_enable(priv); 1602 if (err) 1603 goto out_mcp251xfd_ring_free; 1604 1605 err = mcp251xfd_chip_start(priv); 1606 if (err) 1607 goto out_transceiver_disable; 1608 1609 mcp251xfd_timestamp_init(priv); 1610 clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1611 can_rx_offload_enable(&priv->offload); 1612 1613 err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq, 1614 IRQF_SHARED | IRQF_ONESHOT, 1615 dev_name(&spi->dev), priv); 1616 if (err) 1617 goto out_can_rx_offload_disable; 1618 1619 err = mcp251xfd_chip_interrupts_enable(priv); 1620 if (err) 1621 goto out_free_irq; 1622 1623 netif_start_queue(ndev); 1624 1625 return 0; 1626 1627 out_free_irq: 1628 free_irq(spi->irq, priv); 1629 out_can_rx_offload_disable: 1630 can_rx_offload_disable(&priv->offload); 1631 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1632 mcp251xfd_timestamp_stop(priv); 1633 out_transceiver_disable: 1634 mcp251xfd_transceiver_disable(priv); 1635 out_mcp251xfd_ring_free: 1636 mcp251xfd_ring_free(priv); 1637 out_pm_runtime_put: 1638 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1639 pm_runtime_put(ndev->dev.parent); 1640 out_close_candev: 1641 close_candev(ndev); 1642 1643 return err; 1644 } 1645 1646 static int mcp251xfd_stop(struct net_device *ndev) 1647 { 1648 struct mcp251xfd_priv *priv = netdev_priv(ndev); 1649 1650 netif_stop_queue(ndev); 1651 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 1652 hrtimer_cancel(&priv->rx_irq_timer); 1653 mcp251xfd_chip_interrupts_disable(priv); 1654 free_irq(ndev->irq, priv); 1655 can_rx_offload_disable(&priv->offload); 1656 mcp251xfd_timestamp_stop(priv); 1657 mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED); 1658 mcp251xfd_transceiver_disable(priv); 1659 mcp251xfd_ring_free(priv); 1660 close_candev(ndev); 1661 1662 pm_runtime_put(ndev->dev.parent); 1663 1664 return 0; 1665 } 1666 1667 static const struct net_device_ops mcp251xfd_netdev_ops = { 1668 .ndo_open = mcp251xfd_open, 1669 .ndo_stop = mcp251xfd_stop, 1670 .ndo_start_xmit = mcp251xfd_start_xmit, 1671 .ndo_change_mtu = can_change_mtu, 1672 }; 1673 1674 static void 1675 mcp251xfd_register_quirks(struct mcp251xfd_priv *priv) 1676 { 1677 const struct spi_device *spi = priv->spi; 1678 const struct spi_controller *ctlr = spi->controller; 1679 1680 if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX) 1681 priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX; 1682 } 1683 1684 static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv) 1685 { 1686 const struct net_device *ndev = priv->ndev; 1687 const struct mcp251xfd_devtype_data *devtype_data; 1688 u32 osc; 1689 int err; 1690 1691 /* The OSC_LPMEN is only supported on MCP2518FD, so use it to 1692 * autodetect the model. 1693 */ 1694 err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC, 1695 MCP251XFD_REG_OSC_LPMEN, 1696 MCP251XFD_REG_OSC_LPMEN); 1697 if (err) 1698 return err; 1699 1700 err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc); 1701 if (err) 1702 return err; 1703 1704 if (osc & MCP251XFD_REG_OSC_LPMEN) 1705 devtype_data = &mcp251xfd_devtype_data_mcp2518fd; 1706 else 1707 devtype_data = &mcp251xfd_devtype_data_mcp2517fd; 1708 1709 if (!mcp251xfd_is_251XFD(priv) && 1710 priv->devtype_data.model != devtype_data->model) { 1711 netdev_info(ndev, 1712 "Detected %s, but firmware specifies a %s. Fixing up.\n", 1713 __mcp251xfd_get_model_str(devtype_data->model), 1714 mcp251xfd_get_model_str(priv)); 1715 } 1716 priv->devtype_data = *devtype_data; 1717 1718 /* We need to preserve the Half Duplex Quirk. */ 1719 mcp251xfd_register_quirks(priv); 1720 1721 /* Re-init regmap with quirks of detected model. */ 1722 return mcp251xfd_regmap_init(priv); 1723 } 1724 1725 static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv) 1726 { 1727 int err, rx_pending; 1728 1729 if (!priv->rx_int) 1730 return 0; 1731 1732 err = mcp251xfd_chip_rx_int_enable(priv); 1733 if (err) 1734 return err; 1735 1736 /* Check if RX_INT is properly working. The RX_INT should not 1737 * be active after a softreset. 1738 */ 1739 rx_pending = gpiod_get_value_cansleep(priv->rx_int); 1740 1741 err = mcp251xfd_chip_rx_int_disable(priv); 1742 if (err) 1743 return err; 1744 1745 if (!rx_pending) 1746 return 0; 1747 1748 netdev_info(priv->ndev, 1749 "RX_INT active after softreset, disabling RX_INT support.\n"); 1750 devm_gpiod_put(&priv->spi->dev, priv->rx_int); 1751 priv->rx_int = NULL; 1752 1753 return 0; 1754 } 1755 1756 static int 1757 mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id, 1758 u32 *effective_speed_hz_slow, 1759 u32 *effective_speed_hz_fast) 1760 { 1761 struct mcp251xfd_map_buf_nocrc *buf_rx; 1762 struct mcp251xfd_map_buf_nocrc *buf_tx; 1763 struct spi_transfer xfer[2] = { }; 1764 int err; 1765 1766 buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL); 1767 if (!buf_rx) 1768 return -ENOMEM; 1769 1770 buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL); 1771 if (!buf_tx) { 1772 err = -ENOMEM; 1773 goto out_kfree_buf_rx; 1774 } 1775 1776 xfer[0].tx_buf = buf_tx; 1777 xfer[0].len = sizeof(buf_tx->cmd); 1778 xfer[0].speed_hz = priv->spi_max_speed_hz_slow; 1779 xfer[1].rx_buf = buf_rx->data; 1780 xfer[1].len = sizeof(dev_id); 1781 xfer[1].speed_hz = priv->spi_max_speed_hz_fast; 1782 1783 mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID); 1784 1785 err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer)); 1786 if (err) 1787 goto out_kfree_buf_tx; 1788 1789 *dev_id = be32_to_cpup((__be32 *)buf_rx->data); 1790 *effective_speed_hz_slow = xfer[0].effective_speed_hz; 1791 *effective_speed_hz_fast = xfer[1].effective_speed_hz; 1792 1793 out_kfree_buf_tx: 1794 kfree(buf_tx); 1795 out_kfree_buf_rx: 1796 kfree(buf_rx); 1797 1798 return err; 1799 } 1800 1801 #define MCP251XFD_QUIRK_ACTIVE(quirk) \ 1802 (priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-') 1803 1804 static int 1805 mcp251xfd_register_done(const struct mcp251xfd_priv *priv) 1806 { 1807 u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast; 1808 unsigned long clk_rate; 1809 int err; 1810 1811 err = mcp251xfd_register_get_dev_id(priv, &dev_id, 1812 &effective_speed_hz_slow, 1813 &effective_speed_hz_fast); 1814 if (err) 1815 return err; 1816 1817 clk_rate = clk_get_rate(priv->clk); 1818 1819 netdev_info(priv->ndev, 1820 "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n", 1821 mcp251xfd_get_model_str(priv), 1822 FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id), 1823 FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id), 1824 priv->rx_int ? '+' : '-', 1825 priv->pll_enable ? '+' : '-', 1826 MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN), 1827 MCP251XFD_QUIRK_ACTIVE(CRC_REG), 1828 MCP251XFD_QUIRK_ACTIVE(CRC_RX), 1829 MCP251XFD_QUIRK_ACTIVE(CRC_TX), 1830 MCP251XFD_QUIRK_ACTIVE(ECC), 1831 MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX), 1832 clk_rate / 1000000, 1833 clk_rate % 1000000 / 1000 / 10, 1834 priv->can.clock.freq / 1000000, 1835 priv->can.clock.freq % 1000000 / 1000 / 10, 1836 priv->spi_max_speed_hz_orig / 1000000, 1837 priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10, 1838 priv->spi_max_speed_hz_slow / 1000000, 1839 priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10, 1840 effective_speed_hz_slow / 1000000, 1841 effective_speed_hz_slow % 1000000 / 1000 / 10, 1842 priv->spi_max_speed_hz_fast / 1000000, 1843 priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10, 1844 effective_speed_hz_fast / 1000000, 1845 effective_speed_hz_fast % 1000000 / 1000 / 10); 1846 1847 return 0; 1848 } 1849 1850 static int mcp251xfd_register(struct mcp251xfd_priv *priv) 1851 { 1852 struct net_device *ndev = priv->ndev; 1853 int err; 1854 1855 err = mcp251xfd_clks_and_vdd_enable(priv); 1856 if (err) 1857 return err; 1858 1859 pm_runtime_get_noresume(ndev->dev.parent); 1860 err = pm_runtime_set_active(ndev->dev.parent); 1861 if (err) 1862 goto out_runtime_put_noidle; 1863 pm_runtime_enable(ndev->dev.parent); 1864 1865 mcp251xfd_register_quirks(priv); 1866 1867 err = mcp251xfd_chip_softreset(priv); 1868 if (err == -ENODEV) 1869 goto out_runtime_disable; 1870 if (err) 1871 goto out_chip_sleep; 1872 1873 err = mcp251xfd_chip_clock_init(priv); 1874 if (err == -ENODEV) 1875 goto out_runtime_disable; 1876 if (err) 1877 goto out_chip_sleep; 1878 1879 err = mcp251xfd_register_chip_detect(priv); 1880 if (err) 1881 goto out_chip_sleep; 1882 1883 err = mcp251xfd_register_check_rx_int(priv); 1884 if (err) 1885 goto out_chip_sleep; 1886 1887 mcp251xfd_ethtool_init(priv); 1888 1889 err = register_candev(ndev); 1890 if (err) 1891 goto out_chip_sleep; 1892 1893 err = mcp251xfd_register_done(priv); 1894 if (err) 1895 goto out_unregister_candev; 1896 1897 /* Put controller into sleep mode and let pm_runtime_put() 1898 * disable the clocks and vdd. If CONFIG_PM is not enabled, 1899 * the clocks and vdd will stay powered. 1900 */ 1901 err = mcp251xfd_chip_sleep(priv); 1902 if (err) 1903 goto out_unregister_candev; 1904 1905 pm_runtime_put(ndev->dev.parent); 1906 1907 return 0; 1908 1909 out_unregister_candev: 1910 unregister_candev(ndev); 1911 out_chip_sleep: 1912 mcp251xfd_chip_sleep(priv); 1913 out_runtime_disable: 1914 pm_runtime_disable(ndev->dev.parent); 1915 out_runtime_put_noidle: 1916 pm_runtime_put_noidle(ndev->dev.parent); 1917 mcp251xfd_clks_and_vdd_disable(priv); 1918 1919 return err; 1920 } 1921 1922 static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv) 1923 { 1924 struct net_device *ndev = priv->ndev; 1925 1926 unregister_candev(ndev); 1927 1928 if (pm_runtime_enabled(ndev->dev.parent)) 1929 pm_runtime_disable(ndev->dev.parent); 1930 else 1931 mcp251xfd_clks_and_vdd_disable(priv); 1932 } 1933 1934 static const struct of_device_id mcp251xfd_of_match[] = { 1935 { 1936 .compatible = "microchip,mcp2517fd", 1937 .data = &mcp251xfd_devtype_data_mcp2517fd, 1938 }, { 1939 .compatible = "microchip,mcp2518fd", 1940 .data = &mcp251xfd_devtype_data_mcp2518fd, 1941 }, { 1942 .compatible = "microchip,mcp251863", 1943 .data = &mcp251xfd_devtype_data_mcp251863, 1944 }, { 1945 .compatible = "microchip,mcp251xfd", 1946 .data = &mcp251xfd_devtype_data_mcp251xfd, 1947 }, { 1948 /* sentinel */ 1949 }, 1950 }; 1951 MODULE_DEVICE_TABLE(of, mcp251xfd_of_match); 1952 1953 static const struct spi_device_id mcp251xfd_id_table[] = { 1954 { 1955 .name = "mcp2517fd", 1956 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd, 1957 }, { 1958 .name = "mcp2518fd", 1959 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd, 1960 }, { 1961 .name = "mcp251863", 1962 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863, 1963 }, { 1964 .name = "mcp251xfd", 1965 .driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd, 1966 }, { 1967 /* sentinel */ 1968 }, 1969 }; 1970 MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table); 1971 1972 static int mcp251xfd_probe(struct spi_device *spi) 1973 { 1974 const void *match; 1975 struct net_device *ndev; 1976 struct mcp251xfd_priv *priv; 1977 struct gpio_desc *rx_int; 1978 struct regulator *reg_vdd, *reg_xceiver; 1979 struct clk *clk; 1980 bool pll_enable = false; 1981 u32 freq = 0; 1982 int err; 1983 1984 if (!spi->irq) 1985 return dev_err_probe(&spi->dev, -ENXIO, 1986 "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n"); 1987 1988 rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int", 1989 GPIOD_IN); 1990 if (IS_ERR(rx_int)) 1991 return dev_err_probe(&spi->dev, PTR_ERR(rx_int), 1992 "Failed to get RX-INT!\n"); 1993 1994 reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd"); 1995 if (PTR_ERR(reg_vdd) == -ENODEV) 1996 reg_vdd = NULL; 1997 else if (IS_ERR(reg_vdd)) 1998 return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd), 1999 "Failed to get VDD regulator!\n"); 2000 2001 reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver"); 2002 if (PTR_ERR(reg_xceiver) == -ENODEV) 2003 reg_xceiver = NULL; 2004 else if (IS_ERR(reg_xceiver)) 2005 return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver), 2006 "Failed to get Transceiver regulator!\n"); 2007 2008 clk = devm_clk_get_optional(&spi->dev, NULL); 2009 if (IS_ERR(clk)) 2010 return dev_err_probe(&spi->dev, PTR_ERR(clk), 2011 "Failed to get Oscillator (clock)!\n"); 2012 if (clk) { 2013 freq = clk_get_rate(clk); 2014 } else { 2015 err = device_property_read_u32(&spi->dev, "clock-frequency", 2016 &freq); 2017 if (err) 2018 return dev_err_probe(&spi->dev, err, 2019 "Failed to get clock-frequency!\n"); 2020 } 2021 2022 /* Sanity check */ 2023 if (freq < MCP251XFD_SYSCLOCK_HZ_MIN || 2024 freq > MCP251XFD_SYSCLOCK_HZ_MAX) { 2025 dev_err(&spi->dev, 2026 "Oscillator frequency (%u Hz) is too low or high.\n", 2027 freq); 2028 return -ERANGE; 2029 } 2030 2031 if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER) 2032 pll_enable = true; 2033 2034 ndev = alloc_candev(sizeof(struct mcp251xfd_priv), 2035 MCP251XFD_TX_OBJ_NUM_MAX); 2036 if (!ndev) 2037 return -ENOMEM; 2038 2039 SET_NETDEV_DEV(ndev, &spi->dev); 2040 2041 ndev->netdev_ops = &mcp251xfd_netdev_ops; 2042 ndev->irq = spi->irq; 2043 ndev->flags |= IFF_ECHO; 2044 2045 priv = netdev_priv(ndev); 2046 spi_set_drvdata(spi, priv); 2047 priv->can.clock.freq = freq; 2048 if (pll_enable) 2049 priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER; 2050 priv->can.do_set_mode = mcp251xfd_set_mode; 2051 priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter; 2052 priv->can.bittiming_const = &mcp251xfd_bittiming_const; 2053 priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const; 2054 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 2055 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING | 2056 CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO | 2057 CAN_CTRLMODE_CC_LEN8_DLC; 2058 set_bit(MCP251XFD_FLAGS_DOWN, priv->flags); 2059 priv->ndev = ndev; 2060 priv->spi = spi; 2061 priv->rx_int = rx_int; 2062 priv->clk = clk; 2063 priv->pll_enable = pll_enable; 2064 priv->reg_vdd = reg_vdd; 2065 priv->reg_xceiver = reg_xceiver; 2066 2067 match = device_get_match_data(&spi->dev); 2068 if (match) 2069 priv->devtype_data = *(struct mcp251xfd_devtype_data *)match; 2070 else 2071 priv->devtype_data = *(struct mcp251xfd_devtype_data *) 2072 spi_get_device_id(spi)->driver_data; 2073 2074 /* Errata Reference: 2075 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4. 2076 * 2077 * The SPI can write corrupted data to the RAM at fast SPI 2078 * speeds: 2079 * 2080 * Simultaneous activity on the CAN bus while writing data to 2081 * RAM via the SPI interface, with high SCK frequency, can 2082 * lead to corrupted data being written to RAM. 2083 * 2084 * Fix/Work Around: 2085 * Ensure that FSCK is less than or equal to 0.85 * 2086 * (FSYSCLK/2). 2087 * 2088 * Known good combinations are: 2089 * 2090 * MCP ext-clk SoC SPI SPI-clk max-clk parent-clk config 2091 * 2092 * 2518 20 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 8333333 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 2093 * 2518 40 MHz allwinner,sun8i-h3 allwinner,sun8i-h3-spi 16666667 Hz 83.33% 600000000 Hz assigned-clocks = <&ccu CLK_SPIx> 2094 * 2517 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 2095 * 2518 40 MHz atmel,sama5d27 atmel,at91rm9200-spi 16400000 Hz 82.00% 82000000 Hz default 2096 * 2518 40 MHz fsl,imx6dl fsl,imx51-ecspi 15000000 Hz 75.00% 30000000 Hz default 2097 * 2517 20 MHz fsl,imx8mm fsl,imx51-ecspi 8333333 Hz 83.33% 16666667 Hz assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT> 2098 * 2099 */ 2100 priv->spi_max_speed_hz_orig = spi->max_speed_hz; 2101 priv->spi_max_speed_hz_slow = min(spi->max_speed_hz, 2102 freq / 2 / 1000 * 850); 2103 if (priv->pll_enable) 2104 priv->spi_max_speed_hz_fast = min(spi->max_speed_hz, 2105 freq * 2106 MCP251XFD_OSC_PLL_MULTIPLIER / 2107 2 / 1000 * 850); 2108 else 2109 priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow; 2110 spi->max_speed_hz = priv->spi_max_speed_hz_slow; 2111 spi->bits_per_word = 8; 2112 spi->rt = true; 2113 err = spi_setup(spi); 2114 if (err) 2115 goto out_free_candev; 2116 2117 err = mcp251xfd_regmap_init(priv); 2118 if (err) 2119 goto out_free_candev; 2120 2121 err = can_rx_offload_add_manual(ndev, &priv->offload, 2122 MCP251XFD_NAPI_WEIGHT); 2123 if (err) 2124 goto out_free_candev; 2125 2126 err = mcp251xfd_register(priv); 2127 if (err) { 2128 dev_err_probe(&spi->dev, err, "Failed to detect %s.\n", 2129 mcp251xfd_get_model_str(priv)); 2130 goto out_can_rx_offload_del; 2131 } 2132 2133 return 0; 2134 2135 out_can_rx_offload_del: 2136 can_rx_offload_del(&priv->offload); 2137 out_free_candev: 2138 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2139 2140 free_candev(ndev); 2141 2142 return err; 2143 } 2144 2145 static void mcp251xfd_remove(struct spi_device *spi) 2146 { 2147 struct mcp251xfd_priv *priv = spi_get_drvdata(spi); 2148 struct net_device *ndev = priv->ndev; 2149 2150 can_rx_offload_del(&priv->offload); 2151 mcp251xfd_unregister(priv); 2152 spi->max_speed_hz = priv->spi_max_speed_hz_orig; 2153 free_candev(ndev); 2154 } 2155 2156 static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device) 2157 { 2158 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2159 2160 return mcp251xfd_clks_and_vdd_disable(priv); 2161 } 2162 2163 static int __maybe_unused mcp251xfd_runtime_resume(struct device *device) 2164 { 2165 const struct mcp251xfd_priv *priv = dev_get_drvdata(device); 2166 2167 return mcp251xfd_clks_and_vdd_enable(priv); 2168 } 2169 2170 static const struct dev_pm_ops mcp251xfd_pm_ops = { 2171 SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend, 2172 mcp251xfd_runtime_resume, NULL) 2173 }; 2174 2175 static struct spi_driver mcp251xfd_driver = { 2176 .driver = { 2177 .name = DEVICE_NAME, 2178 .pm = &mcp251xfd_pm_ops, 2179 .of_match_table = mcp251xfd_of_match, 2180 }, 2181 .probe = mcp251xfd_probe, 2182 .remove = mcp251xfd_remove, 2183 .id_table = mcp251xfd_id_table, 2184 }; 2185 module_spi_driver(mcp251xfd_driver); 2186 2187 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 2188 MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver"); 2189 MODULE_LICENSE("GPL v2"); 2190