1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Secure Digital Host Controller 4 // 5 // Copyright (C) 2018 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/of_gpio.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/slab.h> 21 22 #include "sdhci-pltfm.h" 23 #include "mmc_hsq.h" 24 25 /* SDHCI_ARGUMENT2 register high 16bit */ 26 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 27 28 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 29 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 30 #define SDHCI_SPRD_DLL_EN BIT(21) 31 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 32 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 33 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 34 35 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 36 37 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 38 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 39 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 40 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 41 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 42 43 #define SDHCI_SPRD_REG_32_DLL_STS0 0x210 44 #define SDHCI_SPRD_DLL_LOCKED BIT(18) 45 46 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 47 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 48 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 49 50 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 51 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 52 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 53 54 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 55 56 /* SDHCI_HOST_CONTROL2 */ 57 #define SDHCI_SPRD_CTRL_HS200 0x0005 58 #define SDHCI_SPRD_CTRL_HS400 0x0006 59 #define SDHCI_SPRD_CTRL_HS400ES 0x0007 60 61 /* 62 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 63 * reserved, and only used on Spreadtrum's design, the hardware cannot work 64 * if this bit is cleared. 65 * 1 : normal work 66 * 0 : hardware reset 67 */ 68 #define SDHCI_HW_RESET_CARD BIT(3) 69 70 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 71 #define SDHCI_SPRD_CLK_MAX_DIV 1023 72 73 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 74 #define SDHCI_SPRD_PHY_DLL_CLK 52000000 75 76 struct sdhci_sprd_host { 77 u32 version; 78 struct clk *clk_sdio; 79 struct clk *clk_enable; 80 struct clk *clk_2x_enable; 81 struct pinctrl *pinctrl; 82 struct pinctrl_state *pins_uhs; 83 struct pinctrl_state *pins_default; 84 u32 base_rate; 85 int flags; /* backup of host attribute */ 86 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 87 }; 88 89 struct sdhci_sprd_phy_cfg { 90 const char *property; 91 u8 timing; 92 }; 93 94 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 95 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 96 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 97 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 98 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 99 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 100 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 101 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 102 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 103 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 104 }; 105 106 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 107 108 static void sdhci_sprd_init_config(struct sdhci_host *host) 109 { 110 u16 val; 111 112 /* set dll backup mode */ 113 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 114 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 115 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 116 } 117 118 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 119 { 120 if (unlikely(reg == SDHCI_MAX_CURRENT)) 121 return SDHCI_SPRD_MAX_CUR; 122 123 return readl_relaxed(host->ioaddr + reg); 124 } 125 126 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 127 { 128 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 129 if (unlikely(reg == SDHCI_MAX_CURRENT)) 130 return; 131 132 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 133 val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 134 135 writel_relaxed(val, host->ioaddr + reg); 136 } 137 138 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 139 { 140 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 141 if (unlikely(reg == SDHCI_BLOCK_COUNT)) 142 return; 143 144 writew_relaxed(val, host->ioaddr + reg); 145 } 146 147 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 148 { 149 /* 150 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 151 * standard specification, sdhci_reset() write this register directly 152 * without checking other reserved bits, that will clear BIT(3) which 153 * is defined as hardware reset on Spreadtrum's platform and clearing 154 * it by mistake will lead the card not work. So here we need to work 155 * around it. 156 */ 157 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 158 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 159 val |= SDHCI_HW_RESET_CARD; 160 } 161 162 writeb_relaxed(val, host->ioaddr + reg); 163 } 164 165 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 166 { 167 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 168 169 ctrl &= ~SDHCI_CLOCK_CARD_EN; 170 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 171 } 172 173 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 174 { 175 u16 ctrl; 176 177 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 178 ctrl |= SDHCI_CLOCK_CARD_EN; 179 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 180 } 181 182 static inline void 183 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 184 { 185 u32 dll_dly_offset; 186 187 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 188 if (en) 189 dll_dly_offset |= mask; 190 else 191 dll_dly_offset &= ~mask; 192 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 193 } 194 195 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 196 { 197 u32 div; 198 199 /* select 2x clock source */ 200 if (base_clk <= clk * 2) 201 return 0; 202 203 div = (u32) (base_clk / (clk * 2)); 204 205 if ((base_clk / div) > (clk * 2)) 206 div++; 207 208 if (div % 2) 209 div = (div + 1) / 2; 210 else 211 div = div / 2; 212 213 if (div > SDHCI_SPRD_CLK_MAX_DIV) 214 div = SDHCI_SPRD_CLK_MAX_DIV; 215 216 return div; 217 } 218 219 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 220 unsigned int clk) 221 { 222 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 223 u32 div, val, mask; 224 225 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 226 227 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 228 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 229 sdhci_enable_clk(host, div); 230 231 /* Enable CLK_AUTO when the clock is greater than 400K. */ 232 if (clk > 400000) { 233 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 234 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 235 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 236 if (mask != (val & mask)) { 237 val |= mask; 238 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 239 } 240 } 241 } 242 243 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 244 { 245 u32 tmp; 246 247 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 248 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 249 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 250 /* wait 1ms */ 251 usleep_range(1000, 1250); 252 253 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 254 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 255 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 256 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 257 /* wait 1ms */ 258 usleep_range(1000, 1250); 259 260 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 261 tmp |= SDHCI_SPRD_DLL_EN; 262 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 263 /* wait 1ms */ 264 usleep_range(1000, 1250); 265 266 if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), 267 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) { 268 pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc)); 269 pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n", 270 mmc_hostname(host->mmc), 271 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), 272 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); 273 } 274 } 275 276 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 277 { 278 bool en = false, clk_changed = false; 279 280 if (clock == 0) { 281 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 282 } else if (clock != host->clock) { 283 sdhci_sprd_sd_clk_off(host); 284 _sdhci_sprd_set_clock(host, clock); 285 286 if (clock <= 400000) 287 en = true; 288 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 289 SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 290 clk_changed = true; 291 } else { 292 _sdhci_sprd_set_clock(host, clock); 293 } 294 295 /* 296 * According to the Spreadtrum SD host specification, when we changed 297 * the clock to be more than 52M, we should enable the PHY DLL which 298 * is used to track the clock frequency to make the clock work more 299 * stable. Otherwise deviation may occur of the higher clock. 300 */ 301 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 302 sdhci_sprd_enable_phy_dll(host); 303 } 304 305 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 306 { 307 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 308 309 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 310 } 311 312 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 313 { 314 return 100000; 315 } 316 317 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 318 unsigned int timing) 319 { 320 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 321 struct mmc_host *mmc = host->mmc; 322 u32 *p = sprd_host->phy_delay; 323 u16 ctrl_2; 324 325 if (timing == host->timing) 326 return; 327 328 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 329 /* Select Bus Speed Mode for host */ 330 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 331 switch (timing) { 332 case MMC_TIMING_UHS_SDR12: 333 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 334 break; 335 case MMC_TIMING_MMC_HS: 336 case MMC_TIMING_SD_HS: 337 case MMC_TIMING_UHS_SDR25: 338 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 339 break; 340 case MMC_TIMING_UHS_SDR50: 341 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 342 break; 343 case MMC_TIMING_UHS_SDR104: 344 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 345 break; 346 case MMC_TIMING_UHS_DDR50: 347 case MMC_TIMING_MMC_DDR52: 348 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 349 break; 350 case MMC_TIMING_MMC_HS200: 351 ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 352 break; 353 case MMC_TIMING_MMC_HS400: 354 ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 355 break; 356 default: 357 break; 358 } 359 360 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 361 362 if (!mmc->ios.enhanced_strobe) 363 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 364 } 365 366 static void sdhci_sprd_hw_reset(struct sdhci_host *host) 367 { 368 int val; 369 370 /* 371 * Note: don't use sdhci_writeb() API here since it is redirected to 372 * sdhci_sprd_writeb() in which we have a workaround for 373 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 374 * not be cleared. 375 */ 376 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 377 val &= ~SDHCI_HW_RESET_CARD; 378 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 379 /* wait for 10 us */ 380 usleep_range(10, 20); 381 382 val |= SDHCI_HW_RESET_CARD; 383 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 384 usleep_range(300, 500); 385 } 386 387 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 388 { 389 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 390 return 1 << 31; 391 } 392 393 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 394 { 395 return 0; 396 } 397 398 static void sdhci_sprd_request_done(struct sdhci_host *host, 399 struct mmc_request *mrq) 400 { 401 /* Validate if the request was from software queue firstly. */ 402 if (mmc_hsq_finalize_request(host->mmc, mrq)) 403 return; 404 405 mmc_request_done(host->mmc, mrq); 406 } 407 408 static struct sdhci_ops sdhci_sprd_ops = { 409 .read_l = sdhci_sprd_readl, 410 .write_l = sdhci_sprd_writel, 411 .write_w = sdhci_sprd_writew, 412 .write_b = sdhci_sprd_writeb, 413 .set_clock = sdhci_sprd_set_clock, 414 .get_max_clock = sdhci_sprd_get_max_clock, 415 .get_min_clock = sdhci_sprd_get_min_clock, 416 .set_bus_width = sdhci_set_bus_width, 417 .reset = sdhci_reset, 418 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 419 .hw_reset = sdhci_sprd_hw_reset, 420 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 421 .get_ro = sdhci_sprd_get_ro, 422 .request_done = sdhci_sprd_request_done, 423 }; 424 425 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 426 struct mmc_request *mrq) 427 { 428 struct sdhci_host *host = mmc_priv(mmc); 429 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 430 431 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 432 433 /* 434 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 435 * block count register which doesn't support stuff bits of 436 * CMD23 argument on Spreadtrum's sd host controller. 437 */ 438 if (host->version >= SDHCI_SPEC_410 && 439 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 440 (host->flags & SDHCI_AUTO_CMD23)) 441 host->flags &= ~SDHCI_AUTO_CMD23; 442 } 443 444 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 445 { 446 sdhci_sprd_check_auto_cmd23(mmc, mrq); 447 448 sdhci_request(mmc, mrq); 449 } 450 451 static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 452 struct mmc_request *mrq) 453 { 454 sdhci_sprd_check_auto_cmd23(mmc, mrq); 455 456 return sdhci_request_atomic(mmc, mrq); 457 } 458 459 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 460 { 461 struct sdhci_host *host = mmc_priv(mmc); 462 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 463 int ret; 464 465 if (!IS_ERR(mmc->supply.vqmmc)) { 466 ret = mmc_regulator_set_vqmmc(mmc, ios); 467 if (ret < 0) { 468 pr_err("%s: Switching signalling voltage failed\n", 469 mmc_hostname(mmc)); 470 return ret; 471 } 472 } 473 474 if (IS_ERR(sprd_host->pinctrl)) 475 goto reset; 476 477 switch (ios->signal_voltage) { 478 case MMC_SIGNAL_VOLTAGE_180: 479 ret = pinctrl_select_state(sprd_host->pinctrl, 480 sprd_host->pins_uhs); 481 if (ret) { 482 pr_err("%s: failed to select uhs pin state\n", 483 mmc_hostname(mmc)); 484 return ret; 485 } 486 break; 487 488 default: 489 fallthrough; 490 case MMC_SIGNAL_VOLTAGE_330: 491 ret = pinctrl_select_state(sprd_host->pinctrl, 492 sprd_host->pins_default); 493 if (ret) { 494 pr_err("%s: failed to select default pin state\n", 495 mmc_hostname(mmc)); 496 return ret; 497 } 498 break; 499 } 500 501 /* Wait for 300 ~ 500 us for pin state stable */ 502 usleep_range(300, 500); 503 504 reset: 505 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 506 507 return 0; 508 } 509 510 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 511 struct mmc_ios *ios) 512 { 513 struct sdhci_host *host = mmc_priv(mmc); 514 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 515 u32 *p = sprd_host->phy_delay; 516 u16 ctrl_2; 517 518 if (!ios->enhanced_strobe) 519 return; 520 521 sdhci_sprd_sd_clk_off(host); 522 523 /* Set HS400 enhanced strobe mode */ 524 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 525 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 526 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 527 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 528 529 sdhci_sprd_sd_clk_on(host); 530 531 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 532 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 533 SDHCI_SPRD_REG_32_DLL_DLY); 534 } 535 536 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 537 struct device_node *np) 538 { 539 u32 *p = sprd_host->phy_delay; 540 int ret, i, index; 541 u32 val[4]; 542 543 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 544 ret = of_property_read_u32_array(np, 545 sdhci_sprd_phy_cfgs[i].property, val, 4); 546 if (ret) 547 continue; 548 549 index = sdhci_sprd_phy_cfgs[i].timing; 550 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 551 } 552 } 553 554 static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 555 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 556 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 557 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 558 SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 559 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 560 .ops = &sdhci_sprd_ops, 561 }; 562 563 static int sdhci_sprd_probe(struct platform_device *pdev) 564 { 565 struct sdhci_host *host; 566 struct sdhci_sprd_host *sprd_host; 567 struct mmc_hsq *hsq; 568 struct clk *clk; 569 int ret = 0; 570 571 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 572 if (IS_ERR(host)) 573 return PTR_ERR(host); 574 575 host->dma_mask = DMA_BIT_MASK(64); 576 pdev->dev.dma_mask = &host->dma_mask; 577 host->mmc_host_ops.request = sdhci_sprd_request; 578 host->mmc_host_ops.hs400_enhanced_strobe = 579 sdhci_sprd_hs400_enhanced_strobe; 580 /* 581 * We can not use the standard ops to change and detect the voltage 582 * signal for Spreadtrum SD host controller, since our voltage regulator 583 * for I/O is fixed in hardware, that means we do not need control 584 * the standard SD host controller to change the I/O voltage. 585 */ 586 host->mmc_host_ops.start_signal_voltage_switch = 587 sdhci_sprd_voltage_switch; 588 589 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 590 MMC_CAP_WAIT_WHILE_BUSY; 591 592 ret = mmc_of_parse(host->mmc); 593 if (ret) 594 goto pltfm_free; 595 596 if (!mmc_card_is_removable(host->mmc)) 597 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 598 else 599 host->always_defer_done = true; 600 601 sprd_host = TO_SPRD_HOST(host); 602 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 603 604 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 605 if (!IS_ERR(sprd_host->pinctrl)) { 606 sprd_host->pins_uhs = 607 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 608 if (IS_ERR(sprd_host->pins_uhs)) { 609 ret = PTR_ERR(sprd_host->pins_uhs); 610 goto pltfm_free; 611 } 612 613 sprd_host->pins_default = 614 pinctrl_lookup_state(sprd_host->pinctrl, "default"); 615 if (IS_ERR(sprd_host->pins_default)) { 616 ret = PTR_ERR(sprd_host->pins_default); 617 goto pltfm_free; 618 } 619 } 620 621 clk = devm_clk_get(&pdev->dev, "sdio"); 622 if (IS_ERR(clk)) { 623 ret = PTR_ERR(clk); 624 goto pltfm_free; 625 } 626 sprd_host->clk_sdio = clk; 627 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 628 if (!sprd_host->base_rate) 629 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 630 631 clk = devm_clk_get(&pdev->dev, "enable"); 632 if (IS_ERR(clk)) { 633 ret = PTR_ERR(clk); 634 goto pltfm_free; 635 } 636 sprd_host->clk_enable = clk; 637 638 clk = devm_clk_get(&pdev->dev, "2x_enable"); 639 if (!IS_ERR(clk)) 640 sprd_host->clk_2x_enable = clk; 641 642 ret = clk_prepare_enable(sprd_host->clk_sdio); 643 if (ret) 644 goto pltfm_free; 645 646 ret = clk_prepare_enable(sprd_host->clk_enable); 647 if (ret) 648 goto clk_disable; 649 650 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 651 if (ret) 652 goto clk_disable2; 653 654 sdhci_sprd_init_config(host); 655 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 656 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 657 SDHCI_VENDOR_VER_SHIFT); 658 659 pm_runtime_get_noresume(&pdev->dev); 660 pm_runtime_set_active(&pdev->dev); 661 pm_runtime_enable(&pdev->dev); 662 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 663 pm_runtime_use_autosuspend(&pdev->dev); 664 pm_suspend_ignore_children(&pdev->dev, 1); 665 666 sdhci_enable_v4_mode(host); 667 668 /* 669 * Supply the existing CAPS, but clear the UHS-I modes. This 670 * will allow these modes to be specified only by device 671 * tree properties through mmc_of_parse(). 672 */ 673 sdhci_read_caps(host); 674 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 675 SDHCI_SUPPORT_DDR50); 676 677 ret = sdhci_setup_host(host); 678 if (ret) 679 goto pm_runtime_disable; 680 681 sprd_host->flags = host->flags; 682 683 hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 684 if (!hsq) { 685 ret = -ENOMEM; 686 goto err_cleanup_host; 687 } 688 689 ret = mmc_hsq_init(hsq, host->mmc); 690 if (ret) 691 goto err_cleanup_host; 692 693 ret = __sdhci_add_host(host); 694 if (ret) 695 goto err_cleanup_host; 696 697 pm_runtime_mark_last_busy(&pdev->dev); 698 pm_runtime_put_autosuspend(&pdev->dev); 699 700 return 0; 701 702 err_cleanup_host: 703 sdhci_cleanup_host(host); 704 705 pm_runtime_disable: 706 pm_runtime_put_noidle(&pdev->dev); 707 pm_runtime_disable(&pdev->dev); 708 pm_runtime_set_suspended(&pdev->dev); 709 710 clk_disable_unprepare(sprd_host->clk_2x_enable); 711 712 clk_disable2: 713 clk_disable_unprepare(sprd_host->clk_enable); 714 715 clk_disable: 716 clk_disable_unprepare(sprd_host->clk_sdio); 717 718 pltfm_free: 719 sdhci_pltfm_free(pdev); 720 return ret; 721 } 722 723 static int sdhci_sprd_remove(struct platform_device *pdev) 724 { 725 struct sdhci_host *host = platform_get_drvdata(pdev); 726 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 727 728 sdhci_remove_host(host, 0); 729 730 clk_disable_unprepare(sprd_host->clk_sdio); 731 clk_disable_unprepare(sprd_host->clk_enable); 732 clk_disable_unprepare(sprd_host->clk_2x_enable); 733 734 sdhci_pltfm_free(pdev); 735 736 return 0; 737 } 738 739 static const struct of_device_id sdhci_sprd_of_match[] = { 740 { .compatible = "sprd,sdhci-r11", }, 741 { } 742 }; 743 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 744 745 #ifdef CONFIG_PM 746 static int sdhci_sprd_runtime_suspend(struct device *dev) 747 { 748 struct sdhci_host *host = dev_get_drvdata(dev); 749 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 750 751 mmc_hsq_suspend(host->mmc); 752 sdhci_runtime_suspend_host(host); 753 754 clk_disable_unprepare(sprd_host->clk_sdio); 755 clk_disable_unprepare(sprd_host->clk_enable); 756 clk_disable_unprepare(sprd_host->clk_2x_enable); 757 758 return 0; 759 } 760 761 static int sdhci_sprd_runtime_resume(struct device *dev) 762 { 763 struct sdhci_host *host = dev_get_drvdata(dev); 764 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 765 int ret; 766 767 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 768 if (ret) 769 return ret; 770 771 ret = clk_prepare_enable(sprd_host->clk_enable); 772 if (ret) 773 goto clk_2x_disable; 774 775 ret = clk_prepare_enable(sprd_host->clk_sdio); 776 if (ret) 777 goto clk_disable; 778 779 sdhci_runtime_resume_host(host, 1); 780 mmc_hsq_resume(host->mmc); 781 782 return 0; 783 784 clk_disable: 785 clk_disable_unprepare(sprd_host->clk_enable); 786 787 clk_2x_disable: 788 clk_disable_unprepare(sprd_host->clk_2x_enable); 789 790 return ret; 791 } 792 #endif 793 794 static const struct dev_pm_ops sdhci_sprd_pm_ops = { 795 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 796 pm_runtime_force_resume) 797 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 798 sdhci_sprd_runtime_resume, NULL) 799 }; 800 801 static struct platform_driver sdhci_sprd_driver = { 802 .probe = sdhci_sprd_probe, 803 .remove = sdhci_sprd_remove, 804 .driver = { 805 .name = "sdhci_sprd_r11", 806 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 807 .of_match_table = sdhci_sprd_of_match, 808 .pm = &sdhci_sprd_pm_ops, 809 }, 810 }; 811 module_platform_driver(sdhci_sprd_driver); 812 813 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 814 MODULE_LICENSE("GPL v2"); 815 MODULE_ALIAS("platform:sdhci-sprd-r11"); 816