1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Secure Digital Host Controller 4 // 5 // Copyright (C) 2018 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_gpio.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 20 #include "sdhci-pltfm.h" 21 22 /* SDHCI_ARGUMENT2 register high 16bit */ 23 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24 25 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 26 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 27 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 28 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 29 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 30 31 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 32 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 33 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 34 35 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 36 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 37 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 38 39 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 40 41 /* SDHCI_HOST_CONTROL2 */ 42 #define SDHCI_SPRD_CTRL_HS200 0x0005 43 #define SDHCI_SPRD_CTRL_HS400 0x0006 44 45 /* 46 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 47 * reserved, and only used on Spreadtrum's design, the hardware cannot work 48 * if this bit is cleared. 49 * 1 : normal work 50 * 0 : hardware reset 51 */ 52 #define SDHCI_HW_RESET_CARD BIT(3) 53 54 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 55 #define SDHCI_SPRD_CLK_MAX_DIV 1023 56 57 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 58 59 struct sdhci_sprd_host { 60 u32 version; 61 struct clk *clk_sdio; 62 struct clk *clk_enable; 63 struct clk *clk_2x_enable; 64 u32 base_rate; 65 int flags; /* backup of host attribute */ 66 }; 67 68 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 69 70 static void sdhci_sprd_init_config(struct sdhci_host *host) 71 { 72 u16 val; 73 74 /* set dll backup mode */ 75 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 76 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 77 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 78 } 79 80 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 81 { 82 if (unlikely(reg == SDHCI_MAX_CURRENT)) 83 return SDHCI_SPRD_MAX_CUR; 84 85 return readl_relaxed(host->ioaddr + reg); 86 } 87 88 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 89 { 90 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 91 if (unlikely(reg == SDHCI_MAX_CURRENT)) 92 return; 93 94 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 95 val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 96 97 writel_relaxed(val, host->ioaddr + reg); 98 } 99 100 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 101 { 102 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 103 if (unlikely(reg == SDHCI_BLOCK_COUNT)) 104 return; 105 106 writew_relaxed(val, host->ioaddr + reg); 107 } 108 109 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 110 { 111 /* 112 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 113 * standard specification, sdhci_reset() write this register directly 114 * without checking other reserved bits, that will clear BIT(3) which 115 * is defined as hardware reset on Spreadtrum's platform and clearing 116 * it by mistake will lead the card not work. So here we need to work 117 * around it. 118 */ 119 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 120 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 121 val |= SDHCI_HW_RESET_CARD; 122 } 123 124 writeb_relaxed(val, host->ioaddr + reg); 125 } 126 127 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 128 { 129 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 130 131 ctrl &= ~SDHCI_CLOCK_CARD_EN; 132 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 133 } 134 135 static inline void 136 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 137 { 138 u32 dll_dly_offset; 139 140 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 141 if (en) 142 dll_dly_offset |= mask; 143 else 144 dll_dly_offset &= ~mask; 145 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 146 } 147 148 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 149 { 150 u32 div; 151 152 /* select 2x clock source */ 153 if (base_clk <= clk * 2) 154 return 0; 155 156 div = (u32) (base_clk / (clk * 2)); 157 158 if ((base_clk / div) > (clk * 2)) 159 div++; 160 161 if (div > SDHCI_SPRD_CLK_MAX_DIV) 162 div = SDHCI_SPRD_CLK_MAX_DIV; 163 164 if (div % 2) 165 div = (div + 1) / 2; 166 else 167 div = div / 2; 168 169 return div; 170 } 171 172 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 173 unsigned int clk) 174 { 175 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 176 u32 div, val, mask; 177 178 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 179 180 clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 181 sdhci_enable_clk(host, clk); 182 183 /* enable auto gate sdhc_enable_auto_gate */ 184 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 185 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 186 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 187 if (mask != (val & mask)) { 188 val |= mask; 189 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 190 } 191 } 192 193 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 194 { 195 bool en = false; 196 197 if (clock == 0) { 198 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 199 } else if (clock != host->clock) { 200 sdhci_sprd_sd_clk_off(host); 201 _sdhci_sprd_set_clock(host, clock); 202 203 if (clock <= 400000) 204 en = true; 205 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 206 SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 207 } else { 208 _sdhci_sprd_set_clock(host, clock); 209 } 210 } 211 212 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 213 { 214 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 215 216 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 217 } 218 219 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 220 { 221 return 400000; 222 } 223 224 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 225 unsigned int timing) 226 { 227 u16 ctrl_2; 228 229 if (timing == host->timing) 230 return; 231 232 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 233 /* Select Bus Speed Mode for host */ 234 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 235 switch (timing) { 236 case MMC_TIMING_UHS_SDR12: 237 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 238 break; 239 case MMC_TIMING_MMC_HS: 240 case MMC_TIMING_SD_HS: 241 case MMC_TIMING_UHS_SDR25: 242 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 243 break; 244 case MMC_TIMING_UHS_SDR50: 245 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 246 break; 247 case MMC_TIMING_UHS_SDR104: 248 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 249 break; 250 case MMC_TIMING_UHS_DDR50: 251 case MMC_TIMING_MMC_DDR52: 252 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 253 break; 254 case MMC_TIMING_MMC_HS200: 255 ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 256 break; 257 case MMC_TIMING_MMC_HS400: 258 ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 259 break; 260 default: 261 break; 262 } 263 264 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 265 } 266 267 static void sdhci_sprd_hw_reset(struct sdhci_host *host) 268 { 269 int val; 270 271 /* 272 * Note: don't use sdhci_writeb() API here since it is redirected to 273 * sdhci_sprd_writeb() in which we have a workaround for 274 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 275 * not be cleared. 276 */ 277 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 278 val &= ~SDHCI_HW_RESET_CARD; 279 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 280 /* wait for 10 us */ 281 usleep_range(10, 20); 282 283 val |= SDHCI_HW_RESET_CARD; 284 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 285 usleep_range(300, 500); 286 } 287 288 static struct sdhci_ops sdhci_sprd_ops = { 289 .read_l = sdhci_sprd_readl, 290 .write_l = sdhci_sprd_writel, 291 .write_b = sdhci_sprd_writeb, 292 .set_clock = sdhci_sprd_set_clock, 293 .get_max_clock = sdhci_sprd_get_max_clock, 294 .get_min_clock = sdhci_sprd_get_min_clock, 295 .set_bus_width = sdhci_set_bus_width, 296 .reset = sdhci_reset, 297 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 298 .hw_reset = sdhci_sprd_hw_reset, 299 }; 300 301 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 302 { 303 struct sdhci_host *host = mmc_priv(mmc); 304 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 305 306 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 307 308 /* 309 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 310 * block count register which doesn't support stuff bits of 311 * CMD23 argument on Spreadtrum's sd host controller. 312 */ 313 if (host->version >= SDHCI_SPEC_410 && 314 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 315 (host->flags & SDHCI_AUTO_CMD23)) 316 host->flags &= ~SDHCI_AUTO_CMD23; 317 318 sdhci_request(mmc, mrq); 319 } 320 321 static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 322 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 323 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 324 SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 325 .ops = &sdhci_sprd_ops, 326 }; 327 328 static int sdhci_sprd_probe(struct platform_device *pdev) 329 { 330 struct sdhci_host *host; 331 struct sdhci_sprd_host *sprd_host; 332 struct clk *clk; 333 int ret = 0; 334 335 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 336 if (IS_ERR(host)) 337 return PTR_ERR(host); 338 339 host->dma_mask = DMA_BIT_MASK(64); 340 pdev->dev.dma_mask = &host->dma_mask; 341 host->mmc_host_ops.request = sdhci_sprd_request; 342 343 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 344 MMC_CAP_ERASE | MMC_CAP_CMD23; 345 ret = mmc_of_parse(host->mmc); 346 if (ret) 347 goto pltfm_free; 348 349 sprd_host = TO_SPRD_HOST(host); 350 351 clk = devm_clk_get(&pdev->dev, "sdio"); 352 if (IS_ERR(clk)) { 353 ret = PTR_ERR(clk); 354 goto pltfm_free; 355 } 356 sprd_host->clk_sdio = clk; 357 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 358 if (!sprd_host->base_rate) 359 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 360 361 clk = devm_clk_get(&pdev->dev, "enable"); 362 if (IS_ERR(clk)) { 363 ret = PTR_ERR(clk); 364 goto pltfm_free; 365 } 366 sprd_host->clk_enable = clk; 367 368 clk = devm_clk_get(&pdev->dev, "2x_enable"); 369 if (!IS_ERR(clk)) 370 sprd_host->clk_2x_enable = clk; 371 372 ret = clk_prepare_enable(sprd_host->clk_sdio); 373 if (ret) 374 goto pltfm_free; 375 376 ret = clk_prepare_enable(sprd_host->clk_enable); 377 if (ret) 378 goto clk_disable; 379 380 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 381 if (ret) 382 goto clk_disable2; 383 384 sdhci_sprd_init_config(host); 385 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 386 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 387 SDHCI_VENDOR_VER_SHIFT); 388 389 pm_runtime_get_noresume(&pdev->dev); 390 pm_runtime_set_active(&pdev->dev); 391 pm_runtime_enable(&pdev->dev); 392 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 393 pm_runtime_use_autosuspend(&pdev->dev); 394 pm_suspend_ignore_children(&pdev->dev, 1); 395 396 sdhci_enable_v4_mode(host); 397 398 ret = sdhci_setup_host(host); 399 if (ret) 400 goto pm_runtime_disable; 401 402 sprd_host->flags = host->flags; 403 404 ret = __sdhci_add_host(host); 405 if (ret) 406 goto err_cleanup_host; 407 408 pm_runtime_mark_last_busy(&pdev->dev); 409 pm_runtime_put_autosuspend(&pdev->dev); 410 411 return 0; 412 413 err_cleanup_host: 414 sdhci_cleanup_host(host); 415 416 pm_runtime_disable: 417 pm_runtime_disable(&pdev->dev); 418 pm_runtime_set_suspended(&pdev->dev); 419 420 clk_disable_unprepare(sprd_host->clk_2x_enable); 421 422 clk_disable2: 423 clk_disable_unprepare(sprd_host->clk_enable); 424 425 clk_disable: 426 clk_disable_unprepare(sprd_host->clk_sdio); 427 428 pltfm_free: 429 sdhci_pltfm_free(pdev); 430 return ret; 431 } 432 433 static int sdhci_sprd_remove(struct platform_device *pdev) 434 { 435 struct sdhci_host *host = platform_get_drvdata(pdev); 436 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 437 struct mmc_host *mmc = host->mmc; 438 439 mmc_remove_host(mmc); 440 clk_disable_unprepare(sprd_host->clk_sdio); 441 clk_disable_unprepare(sprd_host->clk_enable); 442 clk_disable_unprepare(sprd_host->clk_2x_enable); 443 444 mmc_free_host(mmc); 445 446 return 0; 447 } 448 449 static const struct of_device_id sdhci_sprd_of_match[] = { 450 { .compatible = "sprd,sdhci-r11", }, 451 { } 452 }; 453 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 454 455 #ifdef CONFIG_PM 456 static int sdhci_sprd_runtime_suspend(struct device *dev) 457 { 458 struct sdhci_host *host = dev_get_drvdata(dev); 459 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 460 461 sdhci_runtime_suspend_host(host); 462 463 clk_disable_unprepare(sprd_host->clk_sdio); 464 clk_disable_unprepare(sprd_host->clk_enable); 465 clk_disable_unprepare(sprd_host->clk_2x_enable); 466 467 return 0; 468 } 469 470 static int sdhci_sprd_runtime_resume(struct device *dev) 471 { 472 struct sdhci_host *host = dev_get_drvdata(dev); 473 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 474 int ret; 475 476 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 477 if (ret) 478 return ret; 479 480 ret = clk_prepare_enable(sprd_host->clk_enable); 481 if (ret) 482 goto clk_2x_disable; 483 484 ret = clk_prepare_enable(sprd_host->clk_sdio); 485 if (ret) 486 goto clk_disable; 487 488 sdhci_runtime_resume_host(host); 489 return 0; 490 491 clk_disable: 492 clk_disable_unprepare(sprd_host->clk_enable); 493 494 clk_2x_disable: 495 clk_disable_unprepare(sprd_host->clk_2x_enable); 496 497 return ret; 498 } 499 #endif 500 501 static const struct dev_pm_ops sdhci_sprd_pm_ops = { 502 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 503 pm_runtime_force_resume) 504 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 505 sdhci_sprd_runtime_resume, NULL) 506 }; 507 508 static struct platform_driver sdhci_sprd_driver = { 509 .probe = sdhci_sprd_probe, 510 .remove = sdhci_sprd_remove, 511 .driver = { 512 .name = "sdhci_sprd_r11", 513 .of_match_table = of_match_ptr(sdhci_sprd_of_match), 514 .pm = &sdhci_sprd_pm_ops, 515 }, 516 }; 517 module_platform_driver(sdhci_sprd_driver); 518 519 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 520 MODULE_LICENSE("GPL v2"); 521 MODULE_ALIAS("platform:sdhci-sprd-r11"); 522