1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Secure Digital Host Controller 4 // 5 // Copyright (C) 2018 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_gpio.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/slab.h> 20 21 #include "sdhci-pltfm.h" 22 #include "mmc_hsq.h" 23 24 /* SDHCI_ARGUMENT2 register high 16bit */ 25 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 26 27 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 28 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 29 #define SDHCI_SPRD_DLL_EN BIT(21) 30 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 31 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 32 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 33 34 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 35 36 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 37 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 38 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 39 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 40 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 41 42 #define SDHCI_SPRD_REG_32_DLL_STS0 0x210 43 #define SDHCI_SPRD_DLL_LOCKED BIT(18) 44 45 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 46 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 47 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 48 49 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 50 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 51 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 52 53 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 54 55 /* SDHCI_HOST_CONTROL2 */ 56 #define SDHCI_SPRD_CTRL_HS200 0x0005 57 #define SDHCI_SPRD_CTRL_HS400 0x0006 58 #define SDHCI_SPRD_CTRL_HS400ES 0x0007 59 60 /* 61 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 62 * reserved, and only used on Spreadtrum's design, the hardware cannot work 63 * if this bit is cleared. 64 * 1 : normal work 65 * 0 : hardware reset 66 */ 67 #define SDHCI_HW_RESET_CARD BIT(3) 68 69 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 70 #define SDHCI_SPRD_CLK_MAX_DIV 1023 71 72 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 73 #define SDHCI_SPRD_PHY_DLL_CLK 52000000 74 75 struct sdhci_sprd_host { 76 u32 version; 77 struct clk *clk_sdio; 78 struct clk *clk_enable; 79 struct clk *clk_2x_enable; 80 struct pinctrl *pinctrl; 81 struct pinctrl_state *pins_uhs; 82 struct pinctrl_state *pins_default; 83 u32 base_rate; 84 int flags; /* backup of host attribute */ 85 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 86 }; 87 88 struct sdhci_sprd_phy_cfg { 89 const char *property; 90 u8 timing; 91 }; 92 93 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 94 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 95 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 96 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 97 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 98 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 99 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 100 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 101 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 102 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 103 }; 104 105 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 106 107 static void sdhci_sprd_init_config(struct sdhci_host *host) 108 { 109 u16 val; 110 111 /* set dll backup mode */ 112 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 113 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 114 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 115 } 116 117 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 118 { 119 if (unlikely(reg == SDHCI_MAX_CURRENT)) 120 return SDHCI_SPRD_MAX_CUR; 121 122 return readl_relaxed(host->ioaddr + reg); 123 } 124 125 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 126 { 127 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 128 if (unlikely(reg == SDHCI_MAX_CURRENT)) 129 return; 130 131 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 132 val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 133 134 writel_relaxed(val, host->ioaddr + reg); 135 } 136 137 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 138 { 139 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 140 if (unlikely(reg == SDHCI_BLOCK_COUNT)) 141 return; 142 143 writew_relaxed(val, host->ioaddr + reg); 144 } 145 146 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 147 { 148 /* 149 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 150 * standard specification, sdhci_reset() write this register directly 151 * without checking other reserved bits, that will clear BIT(3) which 152 * is defined as hardware reset on Spreadtrum's platform and clearing 153 * it by mistake will lead the card not work. So here we need to work 154 * around it. 155 */ 156 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 157 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 158 val |= SDHCI_HW_RESET_CARD; 159 } 160 161 writeb_relaxed(val, host->ioaddr + reg); 162 } 163 164 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 165 { 166 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 167 168 ctrl &= ~SDHCI_CLOCK_CARD_EN; 169 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 170 } 171 172 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 173 { 174 u16 ctrl; 175 176 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 177 ctrl |= SDHCI_CLOCK_CARD_EN; 178 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 179 } 180 181 static inline void 182 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 183 { 184 u32 dll_dly_offset; 185 186 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 187 if (en) 188 dll_dly_offset |= mask; 189 else 190 dll_dly_offset &= ~mask; 191 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 192 } 193 194 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 195 { 196 u32 div; 197 198 /* select 2x clock source */ 199 if (base_clk <= clk * 2) 200 return 0; 201 202 div = (u32) (base_clk / (clk * 2)); 203 204 if ((base_clk / div) > (clk * 2)) 205 div++; 206 207 if (div % 2) 208 div = (div + 1) / 2; 209 else 210 div = div / 2; 211 212 if (div > SDHCI_SPRD_CLK_MAX_DIV) 213 div = SDHCI_SPRD_CLK_MAX_DIV; 214 215 return div; 216 } 217 218 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 219 unsigned int clk) 220 { 221 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 222 u32 div, val, mask; 223 224 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 225 226 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 227 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 228 sdhci_enable_clk(host, div); 229 230 /* Enable CLK_AUTO when the clock is greater than 400K. */ 231 if (clk > 400000) { 232 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 233 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 234 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 235 if (mask != (val & mask)) { 236 val |= mask; 237 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 238 } 239 } 240 } 241 242 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 243 { 244 u32 tmp; 245 246 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 247 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 248 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 249 /* wait 1ms */ 250 usleep_range(1000, 1250); 251 252 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 253 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 254 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 255 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 256 /* wait 1ms */ 257 usleep_range(1000, 1250); 258 259 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 260 tmp |= SDHCI_SPRD_DLL_EN; 261 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 262 /* wait 1ms */ 263 usleep_range(1000, 1250); 264 265 if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), 266 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) { 267 pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc)); 268 pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n", 269 mmc_hostname(host->mmc), 270 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), 271 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); 272 } 273 } 274 275 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 276 { 277 bool en = false, clk_changed = false; 278 279 if (clock == 0) { 280 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 281 } else if (clock != host->clock) { 282 sdhci_sprd_sd_clk_off(host); 283 _sdhci_sprd_set_clock(host, clock); 284 285 if (clock <= 400000) 286 en = true; 287 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 288 SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 289 clk_changed = true; 290 } else { 291 _sdhci_sprd_set_clock(host, clock); 292 } 293 294 /* 295 * According to the Spreadtrum SD host specification, when we changed 296 * the clock to be more than 52M, we should enable the PHY DLL which 297 * is used to track the clock frequency to make the clock work more 298 * stable. Otherwise deviation may occur of the higher clock. 299 */ 300 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 301 sdhci_sprd_enable_phy_dll(host); 302 } 303 304 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 305 { 306 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 307 308 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 309 } 310 311 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 312 { 313 return 100000; 314 } 315 316 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 317 unsigned int timing) 318 { 319 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 320 struct mmc_host *mmc = host->mmc; 321 u32 *p = sprd_host->phy_delay; 322 u16 ctrl_2; 323 324 if (timing == host->timing) 325 return; 326 327 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 328 /* Select Bus Speed Mode for host */ 329 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 330 switch (timing) { 331 case MMC_TIMING_UHS_SDR12: 332 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 333 break; 334 case MMC_TIMING_MMC_HS: 335 case MMC_TIMING_SD_HS: 336 case MMC_TIMING_UHS_SDR25: 337 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 338 break; 339 case MMC_TIMING_UHS_SDR50: 340 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 341 break; 342 case MMC_TIMING_UHS_SDR104: 343 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 344 break; 345 case MMC_TIMING_UHS_DDR50: 346 case MMC_TIMING_MMC_DDR52: 347 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 348 break; 349 case MMC_TIMING_MMC_HS200: 350 ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 351 break; 352 case MMC_TIMING_MMC_HS400: 353 ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 354 break; 355 default: 356 break; 357 } 358 359 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 360 361 if (!mmc->ios.enhanced_strobe) 362 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 363 } 364 365 static void sdhci_sprd_hw_reset(struct sdhci_host *host) 366 { 367 int val; 368 369 /* 370 * Note: don't use sdhci_writeb() API here since it is redirected to 371 * sdhci_sprd_writeb() in which we have a workaround for 372 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 373 * not be cleared. 374 */ 375 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 376 val &= ~SDHCI_HW_RESET_CARD; 377 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 378 /* wait for 10 us */ 379 usleep_range(10, 20); 380 381 val |= SDHCI_HW_RESET_CARD; 382 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 383 usleep_range(300, 500); 384 } 385 386 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 387 { 388 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 389 return 1 << 31; 390 } 391 392 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 393 { 394 return 0; 395 } 396 397 static void sdhci_sprd_request_done(struct sdhci_host *host, 398 struct mmc_request *mrq) 399 { 400 /* Validate if the request was from software queue firstly. */ 401 if (mmc_hsq_finalize_request(host->mmc, mrq)) 402 return; 403 404 mmc_request_done(host->mmc, mrq); 405 } 406 407 static struct sdhci_ops sdhci_sprd_ops = { 408 .read_l = sdhci_sprd_readl, 409 .write_l = sdhci_sprd_writel, 410 .write_w = sdhci_sprd_writew, 411 .write_b = sdhci_sprd_writeb, 412 .set_clock = sdhci_sprd_set_clock, 413 .get_max_clock = sdhci_sprd_get_max_clock, 414 .get_min_clock = sdhci_sprd_get_min_clock, 415 .set_bus_width = sdhci_set_bus_width, 416 .reset = sdhci_reset, 417 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 418 .hw_reset = sdhci_sprd_hw_reset, 419 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 420 .get_ro = sdhci_sprd_get_ro, 421 .request_done = sdhci_sprd_request_done, 422 }; 423 424 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 425 struct mmc_request *mrq) 426 { 427 struct sdhci_host *host = mmc_priv(mmc); 428 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 429 430 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 431 432 /* 433 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 434 * block count register which doesn't support stuff bits of 435 * CMD23 argument on Spreadtrum's sd host controller. 436 */ 437 if (host->version >= SDHCI_SPEC_410 && 438 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 439 (host->flags & SDHCI_AUTO_CMD23)) 440 host->flags &= ~SDHCI_AUTO_CMD23; 441 } 442 443 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 444 { 445 sdhci_sprd_check_auto_cmd23(mmc, mrq); 446 447 sdhci_request(mmc, mrq); 448 } 449 450 static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 451 struct mmc_request *mrq) 452 { 453 sdhci_sprd_check_auto_cmd23(mmc, mrq); 454 455 return sdhci_request_atomic(mmc, mrq); 456 } 457 458 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 459 { 460 struct sdhci_host *host = mmc_priv(mmc); 461 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 462 int ret; 463 464 if (!IS_ERR(mmc->supply.vqmmc)) { 465 ret = mmc_regulator_set_vqmmc(mmc, ios); 466 if (ret < 0) { 467 pr_err("%s: Switching signalling voltage failed\n", 468 mmc_hostname(mmc)); 469 return ret; 470 } 471 } 472 473 if (IS_ERR(sprd_host->pinctrl)) 474 goto reset; 475 476 switch (ios->signal_voltage) { 477 case MMC_SIGNAL_VOLTAGE_180: 478 ret = pinctrl_select_state(sprd_host->pinctrl, 479 sprd_host->pins_uhs); 480 if (ret) { 481 pr_err("%s: failed to select uhs pin state\n", 482 mmc_hostname(mmc)); 483 return ret; 484 } 485 break; 486 487 default: 488 fallthrough; 489 case MMC_SIGNAL_VOLTAGE_330: 490 ret = pinctrl_select_state(sprd_host->pinctrl, 491 sprd_host->pins_default); 492 if (ret) { 493 pr_err("%s: failed to select default pin state\n", 494 mmc_hostname(mmc)); 495 return ret; 496 } 497 break; 498 } 499 500 /* Wait for 300 ~ 500 us for pin state stable */ 501 usleep_range(300, 500); 502 503 reset: 504 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 505 506 return 0; 507 } 508 509 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 510 struct mmc_ios *ios) 511 { 512 struct sdhci_host *host = mmc_priv(mmc); 513 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 514 u32 *p = sprd_host->phy_delay; 515 u16 ctrl_2; 516 517 if (!ios->enhanced_strobe) 518 return; 519 520 sdhci_sprd_sd_clk_off(host); 521 522 /* Set HS400 enhanced strobe mode */ 523 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 524 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 525 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 526 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 527 528 sdhci_sprd_sd_clk_on(host); 529 530 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 531 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 532 SDHCI_SPRD_REG_32_DLL_DLY); 533 } 534 535 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 536 struct device_node *np) 537 { 538 u32 *p = sprd_host->phy_delay; 539 int ret, i, index; 540 u32 val[4]; 541 542 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 543 ret = of_property_read_u32_array(np, 544 sdhci_sprd_phy_cfgs[i].property, val, 4); 545 if (ret) 546 continue; 547 548 index = sdhci_sprd_phy_cfgs[i].timing; 549 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 550 } 551 } 552 553 static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 554 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 555 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 556 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 557 SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 558 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 559 .ops = &sdhci_sprd_ops, 560 }; 561 562 static int sdhci_sprd_probe(struct platform_device *pdev) 563 { 564 struct sdhci_host *host; 565 struct sdhci_sprd_host *sprd_host; 566 struct mmc_hsq *hsq; 567 struct clk *clk; 568 int ret = 0; 569 570 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 571 if (IS_ERR(host)) 572 return PTR_ERR(host); 573 574 host->dma_mask = DMA_BIT_MASK(64); 575 pdev->dev.dma_mask = &host->dma_mask; 576 host->mmc_host_ops.request = sdhci_sprd_request; 577 host->mmc_host_ops.hs400_enhanced_strobe = 578 sdhci_sprd_hs400_enhanced_strobe; 579 /* 580 * We can not use the standard ops to change and detect the voltage 581 * signal for Spreadtrum SD host controller, since our voltage regulator 582 * for I/O is fixed in hardware, that means we do not need control 583 * the standard SD host controller to change the I/O voltage. 584 */ 585 host->mmc_host_ops.start_signal_voltage_switch = 586 sdhci_sprd_voltage_switch; 587 588 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 589 MMC_CAP_WAIT_WHILE_BUSY; 590 591 ret = mmc_of_parse(host->mmc); 592 if (ret) 593 goto pltfm_free; 594 595 if (!mmc_card_is_removable(host->mmc)) 596 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 597 else 598 host->always_defer_done = true; 599 600 sprd_host = TO_SPRD_HOST(host); 601 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 602 603 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 604 if (!IS_ERR(sprd_host->pinctrl)) { 605 sprd_host->pins_uhs = 606 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 607 if (IS_ERR(sprd_host->pins_uhs)) { 608 ret = PTR_ERR(sprd_host->pins_uhs); 609 goto pltfm_free; 610 } 611 612 sprd_host->pins_default = 613 pinctrl_lookup_state(sprd_host->pinctrl, "default"); 614 if (IS_ERR(sprd_host->pins_default)) { 615 ret = PTR_ERR(sprd_host->pins_default); 616 goto pltfm_free; 617 } 618 } 619 620 clk = devm_clk_get(&pdev->dev, "sdio"); 621 if (IS_ERR(clk)) { 622 ret = PTR_ERR(clk); 623 goto pltfm_free; 624 } 625 sprd_host->clk_sdio = clk; 626 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 627 if (!sprd_host->base_rate) 628 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 629 630 clk = devm_clk_get(&pdev->dev, "enable"); 631 if (IS_ERR(clk)) { 632 ret = PTR_ERR(clk); 633 goto pltfm_free; 634 } 635 sprd_host->clk_enable = clk; 636 637 clk = devm_clk_get(&pdev->dev, "2x_enable"); 638 if (!IS_ERR(clk)) 639 sprd_host->clk_2x_enable = clk; 640 641 ret = clk_prepare_enable(sprd_host->clk_sdio); 642 if (ret) 643 goto pltfm_free; 644 645 ret = clk_prepare_enable(sprd_host->clk_enable); 646 if (ret) 647 goto clk_disable; 648 649 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 650 if (ret) 651 goto clk_disable2; 652 653 sdhci_sprd_init_config(host); 654 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 655 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 656 SDHCI_VENDOR_VER_SHIFT); 657 658 pm_runtime_get_noresume(&pdev->dev); 659 pm_runtime_set_active(&pdev->dev); 660 pm_runtime_enable(&pdev->dev); 661 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 662 pm_runtime_use_autosuspend(&pdev->dev); 663 pm_suspend_ignore_children(&pdev->dev, 1); 664 665 sdhci_enable_v4_mode(host); 666 667 /* 668 * Supply the existing CAPS, but clear the UHS-I modes. This 669 * will allow these modes to be specified only by device 670 * tree properties through mmc_of_parse(). 671 */ 672 sdhci_read_caps(host); 673 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 674 SDHCI_SUPPORT_DDR50); 675 676 ret = sdhci_setup_host(host); 677 if (ret) 678 goto pm_runtime_disable; 679 680 sprd_host->flags = host->flags; 681 682 hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 683 if (!hsq) { 684 ret = -ENOMEM; 685 goto err_cleanup_host; 686 } 687 688 ret = mmc_hsq_init(hsq, host->mmc); 689 if (ret) 690 goto err_cleanup_host; 691 692 ret = __sdhci_add_host(host); 693 if (ret) 694 goto err_cleanup_host; 695 696 pm_runtime_mark_last_busy(&pdev->dev); 697 pm_runtime_put_autosuspend(&pdev->dev); 698 699 return 0; 700 701 err_cleanup_host: 702 sdhci_cleanup_host(host); 703 704 pm_runtime_disable: 705 pm_runtime_put_noidle(&pdev->dev); 706 pm_runtime_disable(&pdev->dev); 707 pm_runtime_set_suspended(&pdev->dev); 708 709 clk_disable_unprepare(sprd_host->clk_2x_enable); 710 711 clk_disable2: 712 clk_disable_unprepare(sprd_host->clk_enable); 713 714 clk_disable: 715 clk_disable_unprepare(sprd_host->clk_sdio); 716 717 pltfm_free: 718 sdhci_pltfm_free(pdev); 719 return ret; 720 } 721 722 static void sdhci_sprd_remove(struct platform_device *pdev) 723 { 724 struct sdhci_host *host = platform_get_drvdata(pdev); 725 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 726 727 sdhci_remove_host(host, 0); 728 729 clk_disable_unprepare(sprd_host->clk_sdio); 730 clk_disable_unprepare(sprd_host->clk_enable); 731 clk_disable_unprepare(sprd_host->clk_2x_enable); 732 733 sdhci_pltfm_free(pdev); 734 } 735 736 static const struct of_device_id sdhci_sprd_of_match[] = { 737 { .compatible = "sprd,sdhci-r11", }, 738 { } 739 }; 740 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 741 742 #ifdef CONFIG_PM 743 static int sdhci_sprd_runtime_suspend(struct device *dev) 744 { 745 struct sdhci_host *host = dev_get_drvdata(dev); 746 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 747 748 mmc_hsq_suspend(host->mmc); 749 sdhci_runtime_suspend_host(host); 750 751 clk_disable_unprepare(sprd_host->clk_sdio); 752 clk_disable_unprepare(sprd_host->clk_enable); 753 clk_disable_unprepare(sprd_host->clk_2x_enable); 754 755 return 0; 756 } 757 758 static int sdhci_sprd_runtime_resume(struct device *dev) 759 { 760 struct sdhci_host *host = dev_get_drvdata(dev); 761 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 762 int ret; 763 764 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 765 if (ret) 766 return ret; 767 768 ret = clk_prepare_enable(sprd_host->clk_enable); 769 if (ret) 770 goto clk_2x_disable; 771 772 ret = clk_prepare_enable(sprd_host->clk_sdio); 773 if (ret) 774 goto clk_disable; 775 776 sdhci_runtime_resume_host(host, 1); 777 mmc_hsq_resume(host->mmc); 778 779 return 0; 780 781 clk_disable: 782 clk_disable_unprepare(sprd_host->clk_enable); 783 784 clk_2x_disable: 785 clk_disable_unprepare(sprd_host->clk_2x_enable); 786 787 return ret; 788 } 789 #endif 790 791 static const struct dev_pm_ops sdhci_sprd_pm_ops = { 792 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 793 pm_runtime_force_resume) 794 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 795 sdhci_sprd_runtime_resume, NULL) 796 }; 797 798 static struct platform_driver sdhci_sprd_driver = { 799 .probe = sdhci_sprd_probe, 800 .remove_new = sdhci_sprd_remove, 801 .driver = { 802 .name = "sdhci_sprd_r11", 803 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 804 .of_match_table = sdhci_sprd_of_match, 805 .pm = &sdhci_sprd_pm_ops, 806 }, 807 }; 808 module_platform_driver(sdhci_sprd_driver); 809 810 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 811 MODULE_LICENSE("GPL v2"); 812 MODULE_ALIAS("platform:sdhci-sprd-r11"); 813