1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Secure Digital Host Controller 4 // 5 // Copyright (C) 2018 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/iopoll.h> 12 #include <linux/mmc/host.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regulator/consumer.h> 21 #include <linux/slab.h> 22 23 #include "sdhci-pltfm.h" 24 #include "mmc_hsq.h" 25 26 /* SDHCI_ARGUMENT2 register high 16bit */ 27 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 28 29 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 30 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 31 #define SDHCI_SPRD_DLL_EN BIT(21) 32 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 33 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 34 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 35 36 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 37 38 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 39 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 40 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 41 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 42 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 43 44 #define SDHCI_SPRD_REG_32_DLL_STS0 0x210 45 #define SDHCI_SPRD_DLL_LOCKED BIT(18) 46 47 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 48 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 49 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 50 51 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 52 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 53 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 54 55 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 56 57 /* SDHCI_HOST_CONTROL2 */ 58 #define SDHCI_SPRD_CTRL_HS200 0x0005 59 #define SDHCI_SPRD_CTRL_HS400 0x0006 60 #define SDHCI_SPRD_CTRL_HS400ES 0x0007 61 62 /* 63 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 64 * reserved, and only used on Spreadtrum's design, the hardware cannot work 65 * if this bit is cleared. 66 * 1 : normal work 67 * 0 : hardware reset 68 */ 69 #define SDHCI_HW_RESET_CARD BIT(3) 70 71 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 72 #define SDHCI_SPRD_CLK_MAX_DIV 1023 73 74 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 75 #define SDHCI_SPRD_PHY_DLL_CLK 52000000 76 77 #define SDHCI_SPRD_MAX_RANGE 0xff 78 #define SDHCI_SPRD_CMD_DLY_MASK GENMASK(15, 8) 79 #define SDHCI_SPRD_POSRD_DLY_MASK GENMASK(23, 16) 80 #define SDHCI_SPRD_CPST_EN GENMASK(27, 24) 81 82 struct sdhci_sprd_host { 83 u32 version; 84 struct clk *clk_sdio; 85 struct clk *clk_enable; 86 struct clk *clk_2x_enable; 87 struct pinctrl *pinctrl; 88 struct pinctrl_state *pins_uhs; 89 struct pinctrl_state *pins_default; 90 u32 base_rate; 91 int flags; /* backup of host attribute */ 92 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 93 }; 94 95 enum sdhci_sprd_tuning_type { 96 SDHCI_SPRD_TUNING_SD_HS_CMD, 97 SDHCI_SPRD_TUNING_SD_HS_DATA, 98 }; 99 100 struct sdhci_sprd_phy_cfg { 101 const char *property; 102 u8 timing; 103 }; 104 105 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 106 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 107 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 108 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 109 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 110 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 111 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 112 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 113 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 114 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 115 }; 116 117 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 118 119 static void sdhci_sprd_init_config(struct sdhci_host *host) 120 { 121 u16 val; 122 123 /* set dll backup mode */ 124 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 125 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 126 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 127 } 128 129 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 130 { 131 if (unlikely(reg == SDHCI_MAX_CURRENT)) 132 return SDHCI_SPRD_MAX_CUR; 133 134 return readl_relaxed(host->ioaddr + reg); 135 } 136 137 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 138 { 139 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 140 if (unlikely(reg == SDHCI_MAX_CURRENT)) 141 return; 142 143 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 144 val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 145 146 writel_relaxed(val, host->ioaddr + reg); 147 } 148 149 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 150 { 151 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 152 if (unlikely(reg == SDHCI_BLOCK_COUNT)) 153 return; 154 155 writew_relaxed(val, host->ioaddr + reg); 156 } 157 158 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 159 { 160 /* 161 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 162 * standard specification, sdhci_reset() write this register directly 163 * without checking other reserved bits, that will clear BIT(3) which 164 * is defined as hardware reset on Spreadtrum's platform and clearing 165 * it by mistake will lead the card not work. So here we need to work 166 * around it. 167 */ 168 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 169 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 170 val |= SDHCI_HW_RESET_CARD; 171 } 172 173 writeb_relaxed(val, host->ioaddr + reg); 174 } 175 176 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 177 { 178 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 179 180 ctrl &= ~SDHCI_CLOCK_CARD_EN; 181 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 182 } 183 184 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 185 { 186 u16 ctrl; 187 188 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 189 ctrl |= SDHCI_CLOCK_CARD_EN; 190 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 191 } 192 193 static inline void 194 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 195 { 196 u32 dll_dly_offset; 197 198 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 199 if (en) 200 dll_dly_offset |= mask; 201 else 202 dll_dly_offset &= ~mask; 203 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 204 } 205 206 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 207 { 208 u32 div; 209 210 /* select 2x clock source */ 211 if (base_clk <= clk * 2) 212 return 0; 213 214 div = (u32) (base_clk / (clk * 2)); 215 216 if ((base_clk / div) > (clk * 2)) 217 div++; 218 219 if (div % 2) 220 div = (div + 1) / 2; 221 else 222 div = div / 2; 223 224 if (div > SDHCI_SPRD_CLK_MAX_DIV) 225 div = SDHCI_SPRD_CLK_MAX_DIV; 226 227 return div; 228 } 229 230 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 231 unsigned int clk) 232 { 233 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 234 u32 div, val, mask; 235 236 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 237 238 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 239 div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 240 sdhci_enable_clk(host, div); 241 242 /* Enable CLK_AUTO when the clock is greater than 400K. */ 243 if (clk > 400000) { 244 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 245 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 246 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 247 if (mask != (val & mask)) { 248 val |= mask; 249 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 250 } 251 } 252 } 253 254 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 255 { 256 u32 tmp; 257 258 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 259 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 260 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 261 /* wait 1ms */ 262 usleep_range(1000, 1250); 263 264 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 265 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 266 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 267 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 268 /* wait 1ms */ 269 usleep_range(1000, 1250); 270 271 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 272 tmp |= SDHCI_SPRD_DLL_EN; 273 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 274 /* wait 1ms */ 275 usleep_range(1000, 1250); 276 277 if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), 278 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) { 279 pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc)); 280 pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n", 281 mmc_hostname(host->mmc), 282 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), 283 sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); 284 } 285 } 286 287 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 288 { 289 bool en = false, clk_changed = false; 290 291 if (clock == 0) { 292 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 293 } else if (clock != host->clock) { 294 sdhci_sprd_sd_clk_off(host); 295 _sdhci_sprd_set_clock(host, clock); 296 297 if (clock <= 400000) 298 en = true; 299 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 300 SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 301 clk_changed = true; 302 } else { 303 _sdhci_sprd_set_clock(host, clock); 304 } 305 306 /* 307 * According to the Spreadtrum SD host specification, when we changed 308 * the clock to be more than 52M, we should enable the PHY DLL which 309 * is used to track the clock frequency to make the clock work more 310 * stable. Otherwise deviation may occur of the higher clock. 311 */ 312 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 313 sdhci_sprd_enable_phy_dll(host); 314 } 315 316 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 317 { 318 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 319 320 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 321 } 322 323 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 324 { 325 return 100000; 326 } 327 328 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 329 unsigned int timing) 330 { 331 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 332 struct mmc_host *mmc = host->mmc; 333 u32 *p = sprd_host->phy_delay; 334 u16 ctrl_2; 335 336 if (timing == host->timing) 337 return; 338 339 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 340 /* Select Bus Speed Mode for host */ 341 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 342 switch (timing) { 343 case MMC_TIMING_UHS_SDR12: 344 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 345 break; 346 case MMC_TIMING_MMC_HS: 347 case MMC_TIMING_SD_HS: 348 case MMC_TIMING_UHS_SDR25: 349 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 350 break; 351 case MMC_TIMING_UHS_SDR50: 352 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 353 break; 354 case MMC_TIMING_UHS_SDR104: 355 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 356 break; 357 case MMC_TIMING_UHS_DDR50: 358 case MMC_TIMING_MMC_DDR52: 359 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 360 break; 361 case MMC_TIMING_MMC_HS200: 362 ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 363 break; 364 case MMC_TIMING_MMC_HS400: 365 ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 366 break; 367 default: 368 break; 369 } 370 371 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 372 373 if (!mmc->ios.enhanced_strobe) 374 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 375 } 376 377 static void sdhci_sprd_hw_reset(struct sdhci_host *host) 378 { 379 int val; 380 381 /* 382 * Note: don't use sdhci_writeb() API here since it is redirected to 383 * sdhci_sprd_writeb() in which we have a workaround for 384 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 385 * not be cleared. 386 */ 387 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 388 val &= ~SDHCI_HW_RESET_CARD; 389 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 390 /* wait for 10 us */ 391 usleep_range(10, 20); 392 393 val |= SDHCI_HW_RESET_CARD; 394 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 395 usleep_range(300, 500); 396 } 397 398 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 399 { 400 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 401 return 1 << 31; 402 } 403 404 static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 405 { 406 return 0; 407 } 408 409 static void sdhci_sprd_request_done(struct sdhci_host *host, 410 struct mmc_request *mrq) 411 { 412 /* Validate if the request was from software queue firstly. */ 413 if (mmc_hsq_finalize_request(host->mmc, mrq)) 414 return; 415 416 mmc_request_done(host->mmc, mrq); 417 } 418 419 static struct sdhci_ops sdhci_sprd_ops = { 420 .read_l = sdhci_sprd_readl, 421 .write_l = sdhci_sprd_writel, 422 .write_w = sdhci_sprd_writew, 423 .write_b = sdhci_sprd_writeb, 424 .set_clock = sdhci_sprd_set_clock, 425 .get_max_clock = sdhci_sprd_get_max_clock, 426 .get_min_clock = sdhci_sprd_get_min_clock, 427 .set_bus_width = sdhci_set_bus_width, 428 .reset = sdhci_reset, 429 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 430 .hw_reset = sdhci_sprd_hw_reset, 431 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 432 .get_ro = sdhci_sprd_get_ro, 433 .request_done = sdhci_sprd_request_done, 434 }; 435 436 static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 437 struct mmc_request *mrq) 438 { 439 struct sdhci_host *host = mmc_priv(mmc); 440 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 441 442 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 443 444 /* 445 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 446 * block count register which doesn't support stuff bits of 447 * CMD23 argument on Spreadtrum's sd host controller. 448 */ 449 if (host->version >= SDHCI_SPEC_410 && 450 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 451 (host->flags & SDHCI_AUTO_CMD23)) 452 host->flags &= ~SDHCI_AUTO_CMD23; 453 } 454 455 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 456 { 457 sdhci_sprd_check_auto_cmd23(mmc, mrq); 458 459 sdhci_request(mmc, mrq); 460 } 461 462 static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 463 struct mmc_request *mrq) 464 { 465 sdhci_sprd_check_auto_cmd23(mmc, mrq); 466 467 return sdhci_request_atomic(mmc, mrq); 468 } 469 470 static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 471 { 472 struct sdhci_host *host = mmc_priv(mmc); 473 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 474 int ret; 475 476 if (!IS_ERR(mmc->supply.vqmmc)) { 477 ret = mmc_regulator_set_vqmmc(mmc, ios); 478 if (ret < 0) { 479 pr_err("%s: Switching signalling voltage failed\n", 480 mmc_hostname(mmc)); 481 return ret; 482 } 483 } 484 485 if (IS_ERR(sprd_host->pinctrl)) 486 goto reset; 487 488 switch (ios->signal_voltage) { 489 case MMC_SIGNAL_VOLTAGE_180: 490 ret = pinctrl_select_state(sprd_host->pinctrl, 491 sprd_host->pins_uhs); 492 if (ret) { 493 pr_err("%s: failed to select uhs pin state\n", 494 mmc_hostname(mmc)); 495 return ret; 496 } 497 break; 498 499 default: 500 fallthrough; 501 case MMC_SIGNAL_VOLTAGE_330: 502 ret = pinctrl_select_state(sprd_host->pinctrl, 503 sprd_host->pins_default); 504 if (ret) { 505 pr_err("%s: failed to select default pin state\n", 506 mmc_hostname(mmc)); 507 return ret; 508 } 509 break; 510 } 511 512 /* Wait for 300 ~ 500 us for pin state stable */ 513 usleep_range(300, 500); 514 515 reset: 516 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 517 518 return 0; 519 } 520 521 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 522 struct mmc_ios *ios) 523 { 524 struct sdhci_host *host = mmc_priv(mmc); 525 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 526 u32 *p = sprd_host->phy_delay; 527 u16 ctrl_2; 528 529 if (!ios->enhanced_strobe) 530 return; 531 532 sdhci_sprd_sd_clk_off(host); 533 534 /* Set HS400 enhanced strobe mode */ 535 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 536 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 537 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 538 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 539 540 sdhci_sprd_sd_clk_on(host); 541 542 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 543 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 544 SDHCI_SPRD_REG_32_DLL_DLY); 545 } 546 547 static int mmc_send_tuning_cmd(struct mmc_card *card) 548 { 549 return mmc_send_status(card, NULL); 550 } 551 552 static int mmc_send_tuning_data(struct mmc_card *card) 553 { 554 u8 *status; 555 int ret; 556 557 status = kmalloc(64, GFP_KERNEL); 558 if (!status) 559 return -ENOMEM; 560 561 ret = mmc_sd_switch(card, 0, 0, 0, status); 562 563 kfree(status); 564 565 return ret; 566 } 567 568 static int sdhci_sprd_get_best_clk_sample(struct mmc_host *mmc, u8 *value) 569 { 570 int range_end = SDHCI_SPRD_MAX_RANGE; 571 int range_length = 0; 572 int middle_range = 0; 573 int count = 0; 574 int i; 575 576 for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) { 577 if (value[i]) { 578 pr_debug("%s: tuning ok: %d\n", mmc_hostname(mmc), i); 579 count++; 580 } else { 581 pr_debug("%s: tuning fail: %d\n", mmc_hostname(mmc), i); 582 if (range_length < count) { 583 range_length = count; 584 range_end = i - 1; 585 count = 0; 586 } 587 } 588 } 589 590 if (!count) 591 return -EIO; 592 593 if (count > range_length) { 594 range_length = count; 595 range_end = i - 1; 596 } 597 598 middle_range = range_end - (range_length - 1) / 2; 599 600 return middle_range; 601 } 602 603 static int sdhci_sprd_tuning(struct mmc_host *mmc, struct mmc_card *card, 604 enum sdhci_sprd_tuning_type type) 605 { 606 struct sdhci_host *host = mmc_priv(mmc); 607 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 608 u32 *p = sprd_host->phy_delay; 609 u32 dll_cfg, dll_dly; 610 int best_clk_sample; 611 int err = 0; 612 u8 *value; 613 int i; 614 615 value = kmalloc(SDHCI_SPRD_MAX_RANGE + 1, GFP_KERNEL); 616 if (!value) 617 return -ENOMEM; 618 619 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 620 621 dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 622 dll_cfg &= ~SDHCI_SPRD_CPST_EN; 623 sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG); 624 625 dll_dly = p[mmc->ios.timing]; 626 627 for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) { 628 if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) { 629 dll_dly &= ~SDHCI_SPRD_CMD_DLY_MASK; 630 dll_dly |= ((i << 8) & SDHCI_SPRD_CMD_DLY_MASK); 631 } else { 632 dll_dly &= ~SDHCI_SPRD_POSRD_DLY_MASK; 633 dll_dly |= ((i << 16) & SDHCI_SPRD_POSRD_DLY_MASK); 634 } 635 636 sdhci_writel(host, dll_dly, SDHCI_SPRD_REG_32_DLL_DLY); 637 638 if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) 639 value[i] = !mmc_send_tuning_cmd(card); 640 else 641 value[i] = !mmc_send_tuning_data(card); 642 } 643 644 best_clk_sample = sdhci_sprd_get_best_clk_sample(mmc, value); 645 if (best_clk_sample < 0) { 646 dev_err(mmc_dev(host->mmc), "all tuning phase fail!\n"); 647 goto out; 648 } 649 650 if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) { 651 p[mmc->ios.timing] &= ~SDHCI_SPRD_CMD_DLY_MASK; 652 p[mmc->ios.timing] |= ((best_clk_sample << 8) & SDHCI_SPRD_CMD_DLY_MASK); 653 } else { 654 p[mmc->ios.timing] &= ~(SDHCI_SPRD_POSRD_DLY_MASK); 655 p[mmc->ios.timing] |= ((best_clk_sample << 16) & SDHCI_SPRD_POSRD_DLY_MASK); 656 } 657 658 pr_debug("%s: the best clk sample %d, delay value 0x%08x\n", 659 mmc_hostname(host->mmc), best_clk_sample, p[mmc->ios.timing]); 660 661 out: 662 sdhci_writel(host, p[mmc->ios.timing], SDHCI_SPRD_REG_32_DLL_DLY); 663 664 kfree(value); 665 666 return err; 667 } 668 669 static int sdhci_sprd_prepare_sd_hs_cmd_tuning(struct mmc_host *mmc, struct mmc_card *card) 670 { 671 return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_CMD); 672 } 673 674 static int sdhci_sprd_execute_sd_hs_data_tuning(struct mmc_host *mmc, struct mmc_card *card) 675 { 676 return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_DATA); 677 } 678 679 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 680 struct device_node *np) 681 { 682 u32 *p = sprd_host->phy_delay; 683 int ret, i, index; 684 u32 val[4]; 685 686 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 687 ret = of_property_read_u32_array(np, 688 sdhci_sprd_phy_cfgs[i].property, val, 4); 689 if (ret) 690 continue; 691 692 index = sdhci_sprd_phy_cfgs[i].timing; 693 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 694 } 695 } 696 697 static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 698 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 699 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 700 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 701 SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 702 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 703 .ops = &sdhci_sprd_ops, 704 }; 705 706 static int sdhci_sprd_probe(struct platform_device *pdev) 707 { 708 struct sdhci_host *host; 709 struct sdhci_sprd_host *sprd_host; 710 struct mmc_hsq *hsq; 711 struct clk *clk; 712 int ret = 0; 713 714 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 715 if (IS_ERR(host)) 716 return PTR_ERR(host); 717 718 host->dma_mask = DMA_BIT_MASK(64); 719 pdev->dev.dma_mask = &host->dma_mask; 720 host->mmc_host_ops.request = sdhci_sprd_request; 721 host->mmc_host_ops.hs400_enhanced_strobe = 722 sdhci_sprd_hs400_enhanced_strobe; 723 host->mmc_host_ops.prepare_sd_hs_tuning = 724 sdhci_sprd_prepare_sd_hs_cmd_tuning; 725 host->mmc_host_ops.execute_sd_hs_tuning = 726 sdhci_sprd_execute_sd_hs_data_tuning; 727 728 /* 729 * We can not use the standard ops to change and detect the voltage 730 * signal for Spreadtrum SD host controller, since our voltage regulator 731 * for I/O is fixed in hardware, that means we do not need control 732 * the standard SD host controller to change the I/O voltage. 733 */ 734 host->mmc_host_ops.start_signal_voltage_switch = 735 sdhci_sprd_voltage_switch; 736 737 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 738 MMC_CAP_WAIT_WHILE_BUSY; 739 740 ret = mmc_of_parse(host->mmc); 741 if (ret) 742 goto pltfm_free; 743 744 if (!mmc_card_is_removable(host->mmc)) 745 host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 746 else 747 host->always_defer_done = true; 748 749 sprd_host = TO_SPRD_HOST(host); 750 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 751 752 sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 753 if (!IS_ERR(sprd_host->pinctrl)) { 754 sprd_host->pins_uhs = 755 pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 756 if (IS_ERR(sprd_host->pins_uhs)) { 757 ret = PTR_ERR(sprd_host->pins_uhs); 758 goto pltfm_free; 759 } 760 761 sprd_host->pins_default = 762 pinctrl_lookup_state(sprd_host->pinctrl, "default"); 763 if (IS_ERR(sprd_host->pins_default)) { 764 ret = PTR_ERR(sprd_host->pins_default); 765 goto pltfm_free; 766 } 767 } 768 769 clk = devm_clk_get(&pdev->dev, "sdio"); 770 if (IS_ERR(clk)) { 771 ret = PTR_ERR(clk); 772 goto pltfm_free; 773 } 774 sprd_host->clk_sdio = clk; 775 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 776 if (!sprd_host->base_rate) 777 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 778 779 clk = devm_clk_get(&pdev->dev, "enable"); 780 if (IS_ERR(clk)) { 781 ret = PTR_ERR(clk); 782 goto pltfm_free; 783 } 784 sprd_host->clk_enable = clk; 785 786 clk = devm_clk_get(&pdev->dev, "2x_enable"); 787 if (!IS_ERR(clk)) 788 sprd_host->clk_2x_enable = clk; 789 790 ret = clk_prepare_enable(sprd_host->clk_sdio); 791 if (ret) 792 goto pltfm_free; 793 794 ret = clk_prepare_enable(sprd_host->clk_enable); 795 if (ret) 796 goto clk_disable; 797 798 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 799 if (ret) 800 goto clk_disable2; 801 802 sdhci_sprd_init_config(host); 803 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 804 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 805 SDHCI_VENDOR_VER_SHIFT); 806 807 pm_runtime_get_noresume(&pdev->dev); 808 pm_runtime_set_active(&pdev->dev); 809 pm_runtime_enable(&pdev->dev); 810 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 811 pm_runtime_use_autosuspend(&pdev->dev); 812 pm_suspend_ignore_children(&pdev->dev, 1); 813 814 sdhci_enable_v4_mode(host); 815 816 /* 817 * Supply the existing CAPS, but clear the UHS-I modes. This 818 * will allow these modes to be specified only by device 819 * tree properties through mmc_of_parse(). 820 */ 821 sdhci_read_caps(host); 822 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 823 SDHCI_SUPPORT_DDR50); 824 825 ret = sdhci_setup_host(host); 826 if (ret) 827 goto pm_runtime_disable; 828 829 sprd_host->flags = host->flags; 830 831 hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 832 if (!hsq) { 833 ret = -ENOMEM; 834 goto err_cleanup_host; 835 } 836 837 ret = mmc_hsq_init(hsq, host->mmc); 838 if (ret) 839 goto err_cleanup_host; 840 841 ret = __sdhci_add_host(host); 842 if (ret) 843 goto err_cleanup_host; 844 845 pm_runtime_mark_last_busy(&pdev->dev); 846 pm_runtime_put_autosuspend(&pdev->dev); 847 848 return 0; 849 850 err_cleanup_host: 851 sdhci_cleanup_host(host); 852 853 pm_runtime_disable: 854 pm_runtime_put_noidle(&pdev->dev); 855 pm_runtime_disable(&pdev->dev); 856 pm_runtime_set_suspended(&pdev->dev); 857 858 clk_disable_unprepare(sprd_host->clk_2x_enable); 859 860 clk_disable2: 861 clk_disable_unprepare(sprd_host->clk_enable); 862 863 clk_disable: 864 clk_disable_unprepare(sprd_host->clk_sdio); 865 866 pltfm_free: 867 sdhci_pltfm_free(pdev); 868 return ret; 869 } 870 871 static void sdhci_sprd_remove(struct platform_device *pdev) 872 { 873 struct sdhci_host *host = platform_get_drvdata(pdev); 874 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 875 876 sdhci_remove_host(host, 0); 877 878 clk_disable_unprepare(sprd_host->clk_sdio); 879 clk_disable_unprepare(sprd_host->clk_enable); 880 clk_disable_unprepare(sprd_host->clk_2x_enable); 881 882 sdhci_pltfm_free(pdev); 883 } 884 885 static const struct of_device_id sdhci_sprd_of_match[] = { 886 { .compatible = "sprd,sdhci-r11", }, 887 { } 888 }; 889 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 890 891 #ifdef CONFIG_PM 892 static int sdhci_sprd_runtime_suspend(struct device *dev) 893 { 894 struct sdhci_host *host = dev_get_drvdata(dev); 895 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 896 897 mmc_hsq_suspend(host->mmc); 898 sdhci_runtime_suspend_host(host); 899 900 clk_disable_unprepare(sprd_host->clk_sdio); 901 clk_disable_unprepare(sprd_host->clk_enable); 902 clk_disable_unprepare(sprd_host->clk_2x_enable); 903 904 return 0; 905 } 906 907 static int sdhci_sprd_runtime_resume(struct device *dev) 908 { 909 struct sdhci_host *host = dev_get_drvdata(dev); 910 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 911 int ret; 912 913 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 914 if (ret) 915 return ret; 916 917 ret = clk_prepare_enable(sprd_host->clk_enable); 918 if (ret) 919 goto clk_2x_disable; 920 921 ret = clk_prepare_enable(sprd_host->clk_sdio); 922 if (ret) 923 goto clk_disable; 924 925 sdhci_runtime_resume_host(host, 1); 926 mmc_hsq_resume(host->mmc); 927 928 return 0; 929 930 clk_disable: 931 clk_disable_unprepare(sprd_host->clk_enable); 932 933 clk_2x_disable: 934 clk_disable_unprepare(sprd_host->clk_2x_enable); 935 936 return ret; 937 } 938 #endif 939 940 static const struct dev_pm_ops sdhci_sprd_pm_ops = { 941 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 942 pm_runtime_force_resume) 943 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 944 sdhci_sprd_runtime_resume, NULL) 945 }; 946 947 static struct platform_driver sdhci_sprd_driver = { 948 .probe = sdhci_sprd_probe, 949 .remove_new = sdhci_sprd_remove, 950 .driver = { 951 .name = "sdhci_sprd_r11", 952 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 953 .of_match_table = sdhci_sprd_of_match, 954 .pm = &sdhci_sprd_pm_ops, 955 }, 956 }; 957 module_platform_driver(sdhci_sprd_driver); 958 959 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 960 MODULE_LICENSE("GPL v2"); 961 MODULE_ALIAS("platform:sdhci-sprd-r11"); 962