1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Secure Digital Host Controller 4 // 5 // Copyright (C) 2018 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_gpio.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 20 #include "sdhci-pltfm.h" 21 22 /* SDHCI_ARGUMENT2 register high 16bit */ 23 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24 25 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 26 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 27 #define SDHCI_SPRD_DLL_EN BIT(21) 28 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 29 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 30 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 31 32 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 33 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 34 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 35 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 36 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 37 38 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 39 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 40 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 41 42 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 43 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 44 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 45 46 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 47 48 /* SDHCI_HOST_CONTROL2 */ 49 #define SDHCI_SPRD_CTRL_HS200 0x0005 50 #define SDHCI_SPRD_CTRL_HS400 0x0006 51 #define SDHCI_SPRD_CTRL_HS400ES 0x0007 52 53 /* 54 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 55 * reserved, and only used on Spreadtrum's design, the hardware cannot work 56 * if this bit is cleared. 57 * 1 : normal work 58 * 0 : hardware reset 59 */ 60 #define SDHCI_HW_RESET_CARD BIT(3) 61 62 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 63 #define SDHCI_SPRD_CLK_MAX_DIV 1023 64 65 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 66 #define SDHCI_SPRD_PHY_DLL_CLK 52000000 67 68 struct sdhci_sprd_host { 69 u32 version; 70 struct clk *clk_sdio; 71 struct clk *clk_enable; 72 struct clk *clk_2x_enable; 73 u32 base_rate; 74 int flags; /* backup of host attribute */ 75 }; 76 77 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 78 79 static void sdhci_sprd_init_config(struct sdhci_host *host) 80 { 81 u16 val; 82 83 /* set dll backup mode */ 84 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 85 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 86 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 87 } 88 89 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 90 { 91 if (unlikely(reg == SDHCI_MAX_CURRENT)) 92 return SDHCI_SPRD_MAX_CUR; 93 94 return readl_relaxed(host->ioaddr + reg); 95 } 96 97 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 98 { 99 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 100 if (unlikely(reg == SDHCI_MAX_CURRENT)) 101 return; 102 103 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 104 val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 105 106 writel_relaxed(val, host->ioaddr + reg); 107 } 108 109 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 110 { 111 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 112 if (unlikely(reg == SDHCI_BLOCK_COUNT)) 113 return; 114 115 writew_relaxed(val, host->ioaddr + reg); 116 } 117 118 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 119 { 120 /* 121 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 122 * standard specification, sdhci_reset() write this register directly 123 * without checking other reserved bits, that will clear BIT(3) which 124 * is defined as hardware reset on Spreadtrum's platform and clearing 125 * it by mistake will lead the card not work. So here we need to work 126 * around it. 127 */ 128 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 129 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 130 val |= SDHCI_HW_RESET_CARD; 131 } 132 133 writeb_relaxed(val, host->ioaddr + reg); 134 } 135 136 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 137 { 138 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 139 140 ctrl &= ~SDHCI_CLOCK_CARD_EN; 141 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 142 } 143 144 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 145 { 146 u16 ctrl; 147 148 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 149 ctrl |= SDHCI_CLOCK_CARD_EN; 150 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 151 } 152 153 static inline void 154 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 155 { 156 u32 dll_dly_offset; 157 158 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 159 if (en) 160 dll_dly_offset |= mask; 161 else 162 dll_dly_offset &= ~mask; 163 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 164 } 165 166 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 167 { 168 u32 div; 169 170 /* select 2x clock source */ 171 if (base_clk <= clk * 2) 172 return 0; 173 174 div = (u32) (base_clk / (clk * 2)); 175 176 if ((base_clk / div) > (clk * 2)) 177 div++; 178 179 if (div > SDHCI_SPRD_CLK_MAX_DIV) 180 div = SDHCI_SPRD_CLK_MAX_DIV; 181 182 if (div % 2) 183 div = (div + 1) / 2; 184 else 185 div = div / 2; 186 187 return div; 188 } 189 190 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 191 unsigned int clk) 192 { 193 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 194 u32 div, val, mask; 195 196 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 197 198 clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 199 sdhci_enable_clk(host, clk); 200 201 /* enable auto gate sdhc_enable_auto_gate */ 202 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 203 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 204 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 205 if (mask != (val & mask)) { 206 val |= mask; 207 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 208 } 209 } 210 211 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 212 { 213 u32 tmp; 214 215 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 216 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 217 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 218 /* wait 1ms */ 219 usleep_range(1000, 1250); 220 221 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 222 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 223 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 224 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 225 /* wait 1ms */ 226 usleep_range(1000, 1250); 227 228 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 229 tmp |= SDHCI_SPRD_DLL_EN; 230 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 231 /* wait 1ms */ 232 usleep_range(1000, 1250); 233 } 234 235 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 236 { 237 bool en = false, clk_changed = false; 238 239 if (clock == 0) { 240 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 241 } else if (clock != host->clock) { 242 sdhci_sprd_sd_clk_off(host); 243 _sdhci_sprd_set_clock(host, clock); 244 245 if (clock <= 400000) 246 en = true; 247 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 248 SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 249 clk_changed = true; 250 } else { 251 _sdhci_sprd_set_clock(host, clock); 252 } 253 254 /* 255 * According to the Spreadtrum SD host specification, when we changed 256 * the clock to be more than 52M, we should enable the PHY DLL which 257 * is used to track the clock frequency to make the clock work more 258 * stable. Otherwise deviation may occur of the higher clock. 259 */ 260 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 261 sdhci_sprd_enable_phy_dll(host); 262 } 263 264 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 265 { 266 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 267 268 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 269 } 270 271 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 272 { 273 return 400000; 274 } 275 276 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 277 unsigned int timing) 278 { 279 u16 ctrl_2; 280 281 if (timing == host->timing) 282 return; 283 284 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 285 /* Select Bus Speed Mode for host */ 286 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 287 switch (timing) { 288 case MMC_TIMING_UHS_SDR12: 289 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 290 break; 291 case MMC_TIMING_MMC_HS: 292 case MMC_TIMING_SD_HS: 293 case MMC_TIMING_UHS_SDR25: 294 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 295 break; 296 case MMC_TIMING_UHS_SDR50: 297 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 298 break; 299 case MMC_TIMING_UHS_SDR104: 300 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 301 break; 302 case MMC_TIMING_UHS_DDR50: 303 case MMC_TIMING_MMC_DDR52: 304 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 305 break; 306 case MMC_TIMING_MMC_HS200: 307 ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 308 break; 309 case MMC_TIMING_MMC_HS400: 310 ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 311 break; 312 default: 313 break; 314 } 315 316 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 317 } 318 319 static void sdhci_sprd_hw_reset(struct sdhci_host *host) 320 { 321 int val; 322 323 /* 324 * Note: don't use sdhci_writeb() API here since it is redirected to 325 * sdhci_sprd_writeb() in which we have a workaround for 326 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 327 * not be cleared. 328 */ 329 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 330 val &= ~SDHCI_HW_RESET_CARD; 331 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 332 /* wait for 10 us */ 333 usleep_range(10, 20); 334 335 val |= SDHCI_HW_RESET_CARD; 336 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 337 usleep_range(300, 500); 338 } 339 340 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 341 { 342 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 343 return 1 << 31; 344 } 345 346 static struct sdhci_ops sdhci_sprd_ops = { 347 .read_l = sdhci_sprd_readl, 348 .write_l = sdhci_sprd_writel, 349 .write_b = sdhci_sprd_writeb, 350 .set_clock = sdhci_sprd_set_clock, 351 .get_max_clock = sdhci_sprd_get_max_clock, 352 .get_min_clock = sdhci_sprd_get_min_clock, 353 .set_bus_width = sdhci_set_bus_width, 354 .reset = sdhci_reset, 355 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 356 .hw_reset = sdhci_sprd_hw_reset, 357 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 358 }; 359 360 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 361 { 362 struct sdhci_host *host = mmc_priv(mmc); 363 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 364 365 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 366 367 /* 368 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 369 * block count register which doesn't support stuff bits of 370 * CMD23 argument on Spreadtrum's sd host controller. 371 */ 372 if (host->version >= SDHCI_SPEC_410 && 373 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 374 (host->flags & SDHCI_AUTO_CMD23)) 375 host->flags &= ~SDHCI_AUTO_CMD23; 376 377 sdhci_request(mmc, mrq); 378 } 379 380 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 381 struct mmc_ios *ios) 382 { 383 struct sdhci_host *host = mmc_priv(mmc); 384 u16 ctrl_2; 385 386 if (!ios->enhanced_strobe) 387 return; 388 389 sdhci_sprd_sd_clk_off(host); 390 391 /* Set HS400 enhanced strobe mode */ 392 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 393 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 394 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 395 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 396 397 sdhci_sprd_sd_clk_on(host); 398 } 399 400 static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 401 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 402 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 403 SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 404 .ops = &sdhci_sprd_ops, 405 }; 406 407 static int sdhci_sprd_probe(struct platform_device *pdev) 408 { 409 struct sdhci_host *host; 410 struct sdhci_sprd_host *sprd_host; 411 struct clk *clk; 412 int ret = 0; 413 414 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 415 if (IS_ERR(host)) 416 return PTR_ERR(host); 417 418 host->dma_mask = DMA_BIT_MASK(64); 419 pdev->dev.dma_mask = &host->dma_mask; 420 host->mmc_host_ops.request = sdhci_sprd_request; 421 host->mmc_host_ops.hs400_enhanced_strobe = 422 sdhci_sprd_hs400_enhanced_strobe; 423 424 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 425 MMC_CAP_ERASE | MMC_CAP_CMD23; 426 ret = mmc_of_parse(host->mmc); 427 if (ret) 428 goto pltfm_free; 429 430 sprd_host = TO_SPRD_HOST(host); 431 432 clk = devm_clk_get(&pdev->dev, "sdio"); 433 if (IS_ERR(clk)) { 434 ret = PTR_ERR(clk); 435 goto pltfm_free; 436 } 437 sprd_host->clk_sdio = clk; 438 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 439 if (!sprd_host->base_rate) 440 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 441 442 clk = devm_clk_get(&pdev->dev, "enable"); 443 if (IS_ERR(clk)) { 444 ret = PTR_ERR(clk); 445 goto pltfm_free; 446 } 447 sprd_host->clk_enable = clk; 448 449 clk = devm_clk_get(&pdev->dev, "2x_enable"); 450 if (!IS_ERR(clk)) 451 sprd_host->clk_2x_enable = clk; 452 453 ret = clk_prepare_enable(sprd_host->clk_sdio); 454 if (ret) 455 goto pltfm_free; 456 457 ret = clk_prepare_enable(sprd_host->clk_enable); 458 if (ret) 459 goto clk_disable; 460 461 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 462 if (ret) 463 goto clk_disable2; 464 465 sdhci_sprd_init_config(host); 466 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 467 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 468 SDHCI_VENDOR_VER_SHIFT); 469 470 pm_runtime_get_noresume(&pdev->dev); 471 pm_runtime_set_active(&pdev->dev); 472 pm_runtime_enable(&pdev->dev); 473 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 474 pm_runtime_use_autosuspend(&pdev->dev); 475 pm_suspend_ignore_children(&pdev->dev, 1); 476 477 sdhci_enable_v4_mode(host); 478 479 ret = sdhci_setup_host(host); 480 if (ret) 481 goto pm_runtime_disable; 482 483 sprd_host->flags = host->flags; 484 485 ret = __sdhci_add_host(host); 486 if (ret) 487 goto err_cleanup_host; 488 489 pm_runtime_mark_last_busy(&pdev->dev); 490 pm_runtime_put_autosuspend(&pdev->dev); 491 492 return 0; 493 494 err_cleanup_host: 495 sdhci_cleanup_host(host); 496 497 pm_runtime_disable: 498 pm_runtime_disable(&pdev->dev); 499 pm_runtime_set_suspended(&pdev->dev); 500 501 clk_disable_unprepare(sprd_host->clk_2x_enable); 502 503 clk_disable2: 504 clk_disable_unprepare(sprd_host->clk_enable); 505 506 clk_disable: 507 clk_disable_unprepare(sprd_host->clk_sdio); 508 509 pltfm_free: 510 sdhci_pltfm_free(pdev); 511 return ret; 512 } 513 514 static int sdhci_sprd_remove(struct platform_device *pdev) 515 { 516 struct sdhci_host *host = platform_get_drvdata(pdev); 517 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 518 struct mmc_host *mmc = host->mmc; 519 520 mmc_remove_host(mmc); 521 clk_disable_unprepare(sprd_host->clk_sdio); 522 clk_disable_unprepare(sprd_host->clk_enable); 523 clk_disable_unprepare(sprd_host->clk_2x_enable); 524 525 mmc_free_host(mmc); 526 527 return 0; 528 } 529 530 static const struct of_device_id sdhci_sprd_of_match[] = { 531 { .compatible = "sprd,sdhci-r11", }, 532 { } 533 }; 534 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 535 536 #ifdef CONFIG_PM 537 static int sdhci_sprd_runtime_suspend(struct device *dev) 538 { 539 struct sdhci_host *host = dev_get_drvdata(dev); 540 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 541 542 sdhci_runtime_suspend_host(host); 543 544 clk_disable_unprepare(sprd_host->clk_sdio); 545 clk_disable_unprepare(sprd_host->clk_enable); 546 clk_disable_unprepare(sprd_host->clk_2x_enable); 547 548 return 0; 549 } 550 551 static int sdhci_sprd_runtime_resume(struct device *dev) 552 { 553 struct sdhci_host *host = dev_get_drvdata(dev); 554 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 555 int ret; 556 557 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 558 if (ret) 559 return ret; 560 561 ret = clk_prepare_enable(sprd_host->clk_enable); 562 if (ret) 563 goto clk_2x_disable; 564 565 ret = clk_prepare_enable(sprd_host->clk_sdio); 566 if (ret) 567 goto clk_disable; 568 569 sdhci_runtime_resume_host(host); 570 return 0; 571 572 clk_disable: 573 clk_disable_unprepare(sprd_host->clk_enable); 574 575 clk_2x_disable: 576 clk_disable_unprepare(sprd_host->clk_2x_enable); 577 578 return ret; 579 } 580 #endif 581 582 static const struct dev_pm_ops sdhci_sprd_pm_ops = { 583 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 584 pm_runtime_force_resume) 585 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 586 sdhci_sprd_runtime_resume, NULL) 587 }; 588 589 static struct platform_driver sdhci_sprd_driver = { 590 .probe = sdhci_sprd_probe, 591 .remove = sdhci_sprd_remove, 592 .driver = { 593 .name = "sdhci_sprd_r11", 594 .of_match_table = of_match_ptr(sdhci_sprd_of_match), 595 .pm = &sdhci_sprd_pm_ops, 596 }, 597 }; 598 module_platform_driver(sdhci_sprd_driver); 599 600 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 601 MODULE_LICENSE("GPL v2"); 602 MODULE_ALIAS("platform:sdhci-sprd-r11"); 603