1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Secure Digital Host Controller 4 // 5 // Copyright (C) 2018 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_gpio.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 20 #include "sdhci-pltfm.h" 21 22 /* SDHCI_ARGUMENT2 register high 16bit */ 23 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24 25 #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 26 #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 27 #define SDHCI_SPRD_DLL_EN BIT(21) 28 #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 29 #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 30 #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 31 32 #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 33 34 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 35 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 36 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 37 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 38 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 39 40 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 41 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 42 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 43 44 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 45 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 46 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 47 48 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 49 50 /* SDHCI_HOST_CONTROL2 */ 51 #define SDHCI_SPRD_CTRL_HS200 0x0005 52 #define SDHCI_SPRD_CTRL_HS400 0x0006 53 #define SDHCI_SPRD_CTRL_HS400ES 0x0007 54 55 /* 56 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 57 * reserved, and only used on Spreadtrum's design, the hardware cannot work 58 * if this bit is cleared. 59 * 1 : normal work 60 * 0 : hardware reset 61 */ 62 #define SDHCI_HW_RESET_CARD BIT(3) 63 64 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 65 #define SDHCI_SPRD_CLK_MAX_DIV 1023 66 67 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 68 #define SDHCI_SPRD_PHY_DLL_CLK 52000000 69 70 struct sdhci_sprd_host { 71 u32 version; 72 struct clk *clk_sdio; 73 struct clk *clk_enable; 74 struct clk *clk_2x_enable; 75 u32 base_rate; 76 int flags; /* backup of host attribute */ 77 u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 78 }; 79 80 struct sdhci_sprd_phy_cfg { 81 const char *property; 82 u8 timing; 83 }; 84 85 static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 86 { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 87 { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 88 { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 89 { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 90 { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 91 { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 92 { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 93 { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 94 { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 95 }; 96 97 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 98 99 static void sdhci_sprd_init_config(struct sdhci_host *host) 100 { 101 u16 val; 102 103 /* set dll backup mode */ 104 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 105 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 106 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 107 } 108 109 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 110 { 111 if (unlikely(reg == SDHCI_MAX_CURRENT)) 112 return SDHCI_SPRD_MAX_CUR; 113 114 return readl_relaxed(host->ioaddr + reg); 115 } 116 117 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 118 { 119 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 120 if (unlikely(reg == SDHCI_MAX_CURRENT)) 121 return; 122 123 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 124 val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 125 126 writel_relaxed(val, host->ioaddr + reg); 127 } 128 129 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 130 { 131 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 132 if (unlikely(reg == SDHCI_BLOCK_COUNT)) 133 return; 134 135 writew_relaxed(val, host->ioaddr + reg); 136 } 137 138 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 139 { 140 /* 141 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 142 * standard specification, sdhci_reset() write this register directly 143 * without checking other reserved bits, that will clear BIT(3) which 144 * is defined as hardware reset on Spreadtrum's platform and clearing 145 * it by mistake will lead the card not work. So here we need to work 146 * around it. 147 */ 148 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 149 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 150 val |= SDHCI_HW_RESET_CARD; 151 } 152 153 writeb_relaxed(val, host->ioaddr + reg); 154 } 155 156 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 157 { 158 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 159 160 ctrl &= ~SDHCI_CLOCK_CARD_EN; 161 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 162 } 163 164 static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 165 { 166 u16 ctrl; 167 168 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 169 ctrl |= SDHCI_CLOCK_CARD_EN; 170 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 171 } 172 173 static inline void 174 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 175 { 176 u32 dll_dly_offset; 177 178 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 179 if (en) 180 dll_dly_offset |= mask; 181 else 182 dll_dly_offset &= ~mask; 183 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 184 } 185 186 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 187 { 188 u32 div; 189 190 /* select 2x clock source */ 191 if (base_clk <= clk * 2) 192 return 0; 193 194 div = (u32) (base_clk / (clk * 2)); 195 196 if ((base_clk / div) > (clk * 2)) 197 div++; 198 199 if (div > SDHCI_SPRD_CLK_MAX_DIV) 200 div = SDHCI_SPRD_CLK_MAX_DIV; 201 202 if (div % 2) 203 div = (div + 1) / 2; 204 else 205 div = div / 2; 206 207 return div; 208 } 209 210 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 211 unsigned int clk) 212 { 213 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 214 u32 div, val, mask; 215 216 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 217 218 clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 219 sdhci_enable_clk(host, clk); 220 221 /* enable auto gate sdhc_enable_auto_gate */ 222 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 223 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 224 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 225 if (mask != (val & mask)) { 226 val |= mask; 227 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 228 } 229 } 230 231 static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 232 { 233 u32 tmp; 234 235 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 236 tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 237 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 238 /* wait 1ms */ 239 usleep_range(1000, 1250); 240 241 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 242 tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 243 SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 244 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 245 /* wait 1ms */ 246 usleep_range(1000, 1250); 247 248 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 249 tmp |= SDHCI_SPRD_DLL_EN; 250 sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 251 /* wait 1ms */ 252 usleep_range(1000, 1250); 253 } 254 255 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 256 { 257 bool en = false, clk_changed = false; 258 259 if (clock == 0) { 260 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 261 } else if (clock != host->clock) { 262 sdhci_sprd_sd_clk_off(host); 263 _sdhci_sprd_set_clock(host, clock); 264 265 if (clock <= 400000) 266 en = true; 267 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 268 SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 269 clk_changed = true; 270 } else { 271 _sdhci_sprd_set_clock(host, clock); 272 } 273 274 /* 275 * According to the Spreadtrum SD host specification, when we changed 276 * the clock to be more than 52M, we should enable the PHY DLL which 277 * is used to track the clock frequency to make the clock work more 278 * stable. Otherwise deviation may occur of the higher clock. 279 */ 280 if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 281 sdhci_sprd_enable_phy_dll(host); 282 } 283 284 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 285 { 286 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 287 288 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 289 } 290 291 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 292 { 293 return 400000; 294 } 295 296 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 297 unsigned int timing) 298 { 299 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 300 struct mmc_host *mmc = host->mmc; 301 u32 *p = sprd_host->phy_delay; 302 u16 ctrl_2; 303 304 if (timing == host->timing) 305 return; 306 307 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 308 /* Select Bus Speed Mode for host */ 309 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 310 switch (timing) { 311 case MMC_TIMING_UHS_SDR12: 312 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 313 break; 314 case MMC_TIMING_MMC_HS: 315 case MMC_TIMING_SD_HS: 316 case MMC_TIMING_UHS_SDR25: 317 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 318 break; 319 case MMC_TIMING_UHS_SDR50: 320 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 321 break; 322 case MMC_TIMING_UHS_SDR104: 323 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 324 break; 325 case MMC_TIMING_UHS_DDR50: 326 case MMC_TIMING_MMC_DDR52: 327 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 328 break; 329 case MMC_TIMING_MMC_HS200: 330 ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 331 break; 332 case MMC_TIMING_MMC_HS400: 333 ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 334 break; 335 default: 336 break; 337 } 338 339 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 340 341 if (!mmc->ios.enhanced_strobe) 342 sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 343 } 344 345 static void sdhci_sprd_hw_reset(struct sdhci_host *host) 346 { 347 int val; 348 349 /* 350 * Note: don't use sdhci_writeb() API here since it is redirected to 351 * sdhci_sprd_writeb() in which we have a workaround for 352 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 353 * not be cleared. 354 */ 355 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 356 val &= ~SDHCI_HW_RESET_CARD; 357 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 358 /* wait for 10 us */ 359 usleep_range(10, 20); 360 361 val |= SDHCI_HW_RESET_CARD; 362 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 363 usleep_range(300, 500); 364 } 365 366 static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 367 { 368 /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 369 return 1 << 31; 370 } 371 372 static struct sdhci_ops sdhci_sprd_ops = { 373 .read_l = sdhci_sprd_readl, 374 .write_l = sdhci_sprd_writel, 375 .write_b = sdhci_sprd_writeb, 376 .set_clock = sdhci_sprd_set_clock, 377 .get_max_clock = sdhci_sprd_get_max_clock, 378 .get_min_clock = sdhci_sprd_get_min_clock, 379 .set_bus_width = sdhci_set_bus_width, 380 .reset = sdhci_reset, 381 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 382 .hw_reset = sdhci_sprd_hw_reset, 383 .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 384 }; 385 386 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 387 { 388 struct sdhci_host *host = mmc_priv(mmc); 389 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 390 391 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 392 393 /* 394 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 395 * block count register which doesn't support stuff bits of 396 * CMD23 argument on Spreadtrum's sd host controller. 397 */ 398 if (host->version >= SDHCI_SPEC_410 && 399 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 400 (host->flags & SDHCI_AUTO_CMD23)) 401 host->flags &= ~SDHCI_AUTO_CMD23; 402 403 sdhci_request(mmc, mrq); 404 } 405 406 static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 407 struct mmc_ios *ios) 408 { 409 struct sdhci_host *host = mmc_priv(mmc); 410 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 411 u32 *p = sprd_host->phy_delay; 412 u16 ctrl_2; 413 414 if (!ios->enhanced_strobe) 415 return; 416 417 sdhci_sprd_sd_clk_off(host); 418 419 /* Set HS400 enhanced strobe mode */ 420 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 421 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 422 ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 423 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 424 425 sdhci_sprd_sd_clk_on(host); 426 427 /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 428 sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 429 SDHCI_SPRD_REG_32_DLL_DLY); 430 } 431 432 static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 433 struct device_node *np) 434 { 435 u32 *p = sprd_host->phy_delay; 436 int ret, i, index; 437 u32 val[4]; 438 439 for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 440 ret = of_property_read_u32_array(np, 441 sdhci_sprd_phy_cfgs[i].property, val, 4); 442 if (ret) 443 continue; 444 445 index = sdhci_sprd_phy_cfgs[i].timing; 446 p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 447 } 448 } 449 450 static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 451 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 452 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 453 SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 454 .ops = &sdhci_sprd_ops, 455 }; 456 457 static int sdhci_sprd_probe(struct platform_device *pdev) 458 { 459 struct sdhci_host *host; 460 struct sdhci_sprd_host *sprd_host; 461 struct clk *clk; 462 int ret = 0; 463 464 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 465 if (IS_ERR(host)) 466 return PTR_ERR(host); 467 468 host->dma_mask = DMA_BIT_MASK(64); 469 pdev->dev.dma_mask = &host->dma_mask; 470 host->mmc_host_ops.request = sdhci_sprd_request; 471 host->mmc_host_ops.hs400_enhanced_strobe = 472 sdhci_sprd_hs400_enhanced_strobe; 473 474 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 475 MMC_CAP_ERASE | MMC_CAP_CMD23; 476 ret = mmc_of_parse(host->mmc); 477 if (ret) 478 goto pltfm_free; 479 480 sprd_host = TO_SPRD_HOST(host); 481 sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 482 483 clk = devm_clk_get(&pdev->dev, "sdio"); 484 if (IS_ERR(clk)) { 485 ret = PTR_ERR(clk); 486 goto pltfm_free; 487 } 488 sprd_host->clk_sdio = clk; 489 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 490 if (!sprd_host->base_rate) 491 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 492 493 clk = devm_clk_get(&pdev->dev, "enable"); 494 if (IS_ERR(clk)) { 495 ret = PTR_ERR(clk); 496 goto pltfm_free; 497 } 498 sprd_host->clk_enable = clk; 499 500 clk = devm_clk_get(&pdev->dev, "2x_enable"); 501 if (!IS_ERR(clk)) 502 sprd_host->clk_2x_enable = clk; 503 504 ret = clk_prepare_enable(sprd_host->clk_sdio); 505 if (ret) 506 goto pltfm_free; 507 508 ret = clk_prepare_enable(sprd_host->clk_enable); 509 if (ret) 510 goto clk_disable; 511 512 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 513 if (ret) 514 goto clk_disable2; 515 516 sdhci_sprd_init_config(host); 517 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 518 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 519 SDHCI_VENDOR_VER_SHIFT); 520 521 pm_runtime_get_noresume(&pdev->dev); 522 pm_runtime_set_active(&pdev->dev); 523 pm_runtime_enable(&pdev->dev); 524 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 525 pm_runtime_use_autosuspend(&pdev->dev); 526 pm_suspend_ignore_children(&pdev->dev, 1); 527 528 sdhci_enable_v4_mode(host); 529 530 ret = sdhci_setup_host(host); 531 if (ret) 532 goto pm_runtime_disable; 533 534 sprd_host->flags = host->flags; 535 536 ret = __sdhci_add_host(host); 537 if (ret) 538 goto err_cleanup_host; 539 540 pm_runtime_mark_last_busy(&pdev->dev); 541 pm_runtime_put_autosuspend(&pdev->dev); 542 543 return 0; 544 545 err_cleanup_host: 546 sdhci_cleanup_host(host); 547 548 pm_runtime_disable: 549 pm_runtime_disable(&pdev->dev); 550 pm_runtime_set_suspended(&pdev->dev); 551 552 clk_disable_unprepare(sprd_host->clk_2x_enable); 553 554 clk_disable2: 555 clk_disable_unprepare(sprd_host->clk_enable); 556 557 clk_disable: 558 clk_disable_unprepare(sprd_host->clk_sdio); 559 560 pltfm_free: 561 sdhci_pltfm_free(pdev); 562 return ret; 563 } 564 565 static int sdhci_sprd_remove(struct platform_device *pdev) 566 { 567 struct sdhci_host *host = platform_get_drvdata(pdev); 568 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 569 struct mmc_host *mmc = host->mmc; 570 571 mmc_remove_host(mmc); 572 clk_disable_unprepare(sprd_host->clk_sdio); 573 clk_disable_unprepare(sprd_host->clk_enable); 574 clk_disable_unprepare(sprd_host->clk_2x_enable); 575 576 mmc_free_host(mmc); 577 578 return 0; 579 } 580 581 static const struct of_device_id sdhci_sprd_of_match[] = { 582 { .compatible = "sprd,sdhci-r11", }, 583 { } 584 }; 585 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 586 587 #ifdef CONFIG_PM 588 static int sdhci_sprd_runtime_suspend(struct device *dev) 589 { 590 struct sdhci_host *host = dev_get_drvdata(dev); 591 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 592 593 sdhci_runtime_suspend_host(host); 594 595 clk_disable_unprepare(sprd_host->clk_sdio); 596 clk_disable_unprepare(sprd_host->clk_enable); 597 clk_disable_unprepare(sprd_host->clk_2x_enable); 598 599 return 0; 600 } 601 602 static int sdhci_sprd_runtime_resume(struct device *dev) 603 { 604 struct sdhci_host *host = dev_get_drvdata(dev); 605 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 606 int ret; 607 608 ret = clk_prepare_enable(sprd_host->clk_2x_enable); 609 if (ret) 610 return ret; 611 612 ret = clk_prepare_enable(sprd_host->clk_enable); 613 if (ret) 614 goto clk_2x_disable; 615 616 ret = clk_prepare_enable(sprd_host->clk_sdio); 617 if (ret) 618 goto clk_disable; 619 620 sdhci_runtime_resume_host(host); 621 return 0; 622 623 clk_disable: 624 clk_disable_unprepare(sprd_host->clk_enable); 625 626 clk_2x_disable: 627 clk_disable_unprepare(sprd_host->clk_2x_enable); 628 629 return ret; 630 } 631 #endif 632 633 static const struct dev_pm_ops sdhci_sprd_pm_ops = { 634 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 635 pm_runtime_force_resume) 636 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 637 sdhci_sprd_runtime_resume, NULL) 638 }; 639 640 static struct platform_driver sdhci_sprd_driver = { 641 .probe = sdhci_sprd_probe, 642 .remove = sdhci_sprd_remove, 643 .driver = { 644 .name = "sdhci_sprd_r11", 645 .of_match_table = of_match_ptr(sdhci_sprd_of_match), 646 .pm = &sdhci_sprd_pm_ops, 647 }, 648 }; 649 module_platform_driver(sdhci_sprd_driver); 650 651 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 652 MODULE_LICENSE("GPL v2"); 653 MODULE_ALIAS("platform:sdhci-sprd-r11"); 654