1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Secure Digital Host Controller 4 // 5 // Copyright (C) 2018 Spreadtrum, Inc. 6 // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/highmem.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_gpio.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 20 #include "sdhci-pltfm.h" 21 22 /* SDHCI_ARGUMENT2 register high 16bit */ 23 #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24 25 #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 26 #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 27 #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 28 #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 29 #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 30 31 #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 32 #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 33 #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 34 35 #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 36 #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 37 #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 38 39 #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 40 41 /* SDHCI_HOST_CONTROL2 */ 42 #define SDHCI_SPRD_CTRL_HS200 0x0005 43 #define SDHCI_SPRD_CTRL_HS400 0x0006 44 45 /* 46 * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 47 * reserved, and only used on Spreadtrum's design, the hardware cannot work 48 * if this bit is cleared. 49 * 1 : normal work 50 * 0 : hardware reset 51 */ 52 #define SDHCI_HW_RESET_CARD BIT(3) 53 54 #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 55 #define SDHCI_SPRD_CLK_MAX_DIV 1023 56 57 #define SDHCI_SPRD_CLK_DEF_RATE 26000000 58 59 struct sdhci_sprd_host { 60 u32 version; 61 struct clk *clk_sdio; 62 struct clk *clk_enable; 63 u32 base_rate; 64 int flags; /* backup of host attribute */ 65 }; 66 67 #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 68 69 static void sdhci_sprd_init_config(struct sdhci_host *host) 70 { 71 u16 val; 72 73 /* set dll backup mode */ 74 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 75 val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 76 sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 77 } 78 79 static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 80 { 81 if (unlikely(reg == SDHCI_MAX_CURRENT)) 82 return SDHCI_SPRD_MAX_CUR; 83 84 return readl_relaxed(host->ioaddr + reg); 85 } 86 87 static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 88 { 89 /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 90 if (unlikely(reg == SDHCI_MAX_CURRENT)) 91 return; 92 93 if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 94 val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 95 96 writel_relaxed(val, host->ioaddr + reg); 97 } 98 99 static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 100 { 101 /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 102 if (unlikely(reg == SDHCI_BLOCK_COUNT)) 103 return; 104 105 writew_relaxed(val, host->ioaddr + reg); 106 } 107 108 static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 109 { 110 /* 111 * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 112 * standard specification, sdhci_reset() write this register directly 113 * without checking other reserved bits, that will clear BIT(3) which 114 * is defined as hardware reset on Spreadtrum's platform and clearing 115 * it by mistake will lead the card not work. So here we need to work 116 * around it. 117 */ 118 if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 119 if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 120 val |= SDHCI_HW_RESET_CARD; 121 } 122 123 writeb_relaxed(val, host->ioaddr + reg); 124 } 125 126 static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 127 { 128 u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 129 130 ctrl &= ~SDHCI_CLOCK_CARD_EN; 131 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 132 } 133 134 static inline void 135 sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 136 { 137 u32 dll_dly_offset; 138 139 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 140 if (en) 141 dll_dly_offset |= mask; 142 else 143 dll_dly_offset &= ~mask; 144 sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 145 } 146 147 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 148 { 149 u32 div; 150 151 /* select 2x clock source */ 152 if (base_clk <= clk * 2) 153 return 0; 154 155 div = (u32) (base_clk / (clk * 2)); 156 157 if ((base_clk / div) > (clk * 2)) 158 div++; 159 160 if (div > SDHCI_SPRD_CLK_MAX_DIV) 161 div = SDHCI_SPRD_CLK_MAX_DIV; 162 163 if (div % 2) 164 div = (div + 1) / 2; 165 else 166 div = div / 2; 167 168 return div; 169 } 170 171 static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 172 unsigned int clk) 173 { 174 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 175 u32 div, val, mask; 176 177 div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 178 179 clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 180 sdhci_enable_clk(host, clk); 181 182 /* enable auto gate sdhc_enable_auto_gate */ 183 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 184 mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 185 SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 186 if (mask != (val & mask)) { 187 val |= mask; 188 sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 189 } 190 } 191 192 static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 193 { 194 bool en = false; 195 196 if (clock == 0) { 197 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 198 } else if (clock != host->clock) { 199 sdhci_sprd_sd_clk_off(host); 200 _sdhci_sprd_set_clock(host, clock); 201 202 if (clock <= 400000) 203 en = true; 204 sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 205 SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 206 } else { 207 _sdhci_sprd_set_clock(host, clock); 208 } 209 } 210 211 static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 212 { 213 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 214 215 return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 216 } 217 218 static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 219 { 220 return 400000; 221 } 222 223 static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 224 unsigned int timing) 225 { 226 u16 ctrl_2; 227 228 if (timing == host->timing) 229 return; 230 231 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 232 /* Select Bus Speed Mode for host */ 233 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 234 switch (timing) { 235 case MMC_TIMING_UHS_SDR12: 236 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 237 break; 238 case MMC_TIMING_MMC_HS: 239 case MMC_TIMING_SD_HS: 240 case MMC_TIMING_UHS_SDR25: 241 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 242 break; 243 case MMC_TIMING_UHS_SDR50: 244 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 245 break; 246 case MMC_TIMING_UHS_SDR104: 247 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 248 break; 249 case MMC_TIMING_UHS_DDR50: 250 case MMC_TIMING_MMC_DDR52: 251 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 252 break; 253 case MMC_TIMING_MMC_HS200: 254 ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 255 break; 256 case MMC_TIMING_MMC_HS400: 257 ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 258 break; 259 default: 260 break; 261 } 262 263 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 264 } 265 266 static void sdhci_sprd_hw_reset(struct sdhci_host *host) 267 { 268 int val; 269 270 /* 271 * Note: don't use sdhci_writeb() API here since it is redirected to 272 * sdhci_sprd_writeb() in which we have a workaround for 273 * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 274 * not be cleared. 275 */ 276 val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 277 val &= ~SDHCI_HW_RESET_CARD; 278 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 279 /* wait for 10 us */ 280 usleep_range(10, 20); 281 282 val |= SDHCI_HW_RESET_CARD; 283 writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 284 usleep_range(300, 500); 285 } 286 287 static struct sdhci_ops sdhci_sprd_ops = { 288 .read_l = sdhci_sprd_readl, 289 .write_l = sdhci_sprd_writel, 290 .write_b = sdhci_sprd_writeb, 291 .set_clock = sdhci_sprd_set_clock, 292 .get_max_clock = sdhci_sprd_get_max_clock, 293 .get_min_clock = sdhci_sprd_get_min_clock, 294 .set_bus_width = sdhci_set_bus_width, 295 .reset = sdhci_reset, 296 .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 297 .hw_reset = sdhci_sprd_hw_reset, 298 }; 299 300 static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 301 { 302 struct sdhci_host *host = mmc_priv(mmc); 303 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 304 305 host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 306 307 /* 308 * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 309 * block count register which doesn't support stuff bits of 310 * CMD23 argument on Spreadtrum's sd host controller. 311 */ 312 if (host->version >= SDHCI_SPEC_410 && 313 mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 314 (host->flags & SDHCI_AUTO_CMD23)) 315 host->flags &= ~SDHCI_AUTO_CMD23; 316 317 sdhci_request(mmc, mrq); 318 } 319 320 static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 321 .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 322 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 323 SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 324 .ops = &sdhci_sprd_ops, 325 }; 326 327 static int sdhci_sprd_probe(struct platform_device *pdev) 328 { 329 struct sdhci_host *host; 330 struct sdhci_sprd_host *sprd_host; 331 struct clk *clk; 332 int ret = 0; 333 334 host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 335 if (IS_ERR(host)) 336 return PTR_ERR(host); 337 338 host->dma_mask = DMA_BIT_MASK(64); 339 pdev->dev.dma_mask = &host->dma_mask; 340 host->mmc_host_ops.request = sdhci_sprd_request; 341 342 host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 343 MMC_CAP_ERASE | MMC_CAP_CMD23; 344 ret = mmc_of_parse(host->mmc); 345 if (ret) 346 goto pltfm_free; 347 348 sprd_host = TO_SPRD_HOST(host); 349 350 clk = devm_clk_get(&pdev->dev, "sdio"); 351 if (IS_ERR(clk)) { 352 ret = PTR_ERR(clk); 353 goto pltfm_free; 354 } 355 sprd_host->clk_sdio = clk; 356 sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 357 if (!sprd_host->base_rate) 358 sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 359 360 clk = devm_clk_get(&pdev->dev, "enable"); 361 if (IS_ERR(clk)) { 362 ret = PTR_ERR(clk); 363 goto pltfm_free; 364 } 365 sprd_host->clk_enable = clk; 366 367 ret = clk_prepare_enable(sprd_host->clk_sdio); 368 if (ret) 369 goto pltfm_free; 370 371 clk_prepare_enable(sprd_host->clk_enable); 372 if (ret) 373 goto clk_disable; 374 375 sdhci_sprd_init_config(host); 376 host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 377 sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 378 SDHCI_VENDOR_VER_SHIFT); 379 380 pm_runtime_get_noresume(&pdev->dev); 381 pm_runtime_set_active(&pdev->dev); 382 pm_runtime_enable(&pdev->dev); 383 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 384 pm_runtime_use_autosuspend(&pdev->dev); 385 pm_suspend_ignore_children(&pdev->dev, 1); 386 387 sdhci_enable_v4_mode(host); 388 389 ret = sdhci_setup_host(host); 390 if (ret) 391 goto pm_runtime_disable; 392 393 sprd_host->flags = host->flags; 394 395 ret = __sdhci_add_host(host); 396 if (ret) 397 goto err_cleanup_host; 398 399 pm_runtime_mark_last_busy(&pdev->dev); 400 pm_runtime_put_autosuspend(&pdev->dev); 401 402 return 0; 403 404 err_cleanup_host: 405 sdhci_cleanup_host(host); 406 407 pm_runtime_disable: 408 pm_runtime_disable(&pdev->dev); 409 pm_runtime_set_suspended(&pdev->dev); 410 411 clk_disable_unprepare(sprd_host->clk_enable); 412 413 clk_disable: 414 clk_disable_unprepare(sprd_host->clk_sdio); 415 416 pltfm_free: 417 sdhci_pltfm_free(pdev); 418 return ret; 419 } 420 421 static int sdhci_sprd_remove(struct platform_device *pdev) 422 { 423 struct sdhci_host *host = platform_get_drvdata(pdev); 424 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 425 struct mmc_host *mmc = host->mmc; 426 427 mmc_remove_host(mmc); 428 clk_disable_unprepare(sprd_host->clk_sdio); 429 clk_disable_unprepare(sprd_host->clk_enable); 430 431 mmc_free_host(mmc); 432 433 return 0; 434 } 435 436 static const struct of_device_id sdhci_sprd_of_match[] = { 437 { .compatible = "sprd,sdhci-r11", }, 438 { } 439 }; 440 MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 441 442 #ifdef CONFIG_PM 443 static int sdhci_sprd_runtime_suspend(struct device *dev) 444 { 445 struct sdhci_host *host = dev_get_drvdata(dev); 446 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 447 448 sdhci_runtime_suspend_host(host); 449 450 clk_disable_unprepare(sprd_host->clk_sdio); 451 clk_disable_unprepare(sprd_host->clk_enable); 452 453 return 0; 454 } 455 456 static int sdhci_sprd_runtime_resume(struct device *dev) 457 { 458 struct sdhci_host *host = dev_get_drvdata(dev); 459 struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 460 int ret; 461 462 ret = clk_prepare_enable(sprd_host->clk_enable); 463 if (ret) 464 return ret; 465 466 ret = clk_prepare_enable(sprd_host->clk_sdio); 467 if (ret) { 468 clk_disable_unprepare(sprd_host->clk_enable); 469 return ret; 470 } 471 472 sdhci_runtime_resume_host(host); 473 474 return 0; 475 } 476 #endif 477 478 static const struct dev_pm_ops sdhci_sprd_pm_ops = { 479 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 480 pm_runtime_force_resume) 481 SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 482 sdhci_sprd_runtime_resume, NULL) 483 }; 484 485 static struct platform_driver sdhci_sprd_driver = { 486 .probe = sdhci_sprd_probe, 487 .remove = sdhci_sprd_remove, 488 .driver = { 489 .name = "sdhci_sprd_r11", 490 .of_match_table = of_match_ptr(sdhci_sprd_of_match), 491 .pm = &sdhci_sprd_pm_ops, 492 }, 493 }; 494 module_platform_driver(sdhci_sprd_driver); 495 496 MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 497 MODULE_LICENSE("GPL v2"); 498 MODULE_ALIAS("platform:sdhci-sprd-r11"); 499