1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 11fb8bd90fSChunyan Zhang #include <linux/module.h> 12fb8bd90fSChunyan Zhang #include <linux/of.h> 13fb8bd90fSChunyan Zhang #include <linux/of_device.h> 14fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 15fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 16fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 17fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 18fb8bd90fSChunyan Zhang #include <linux/slab.h> 19fb8bd90fSChunyan Zhang 20fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 21fb8bd90fSChunyan Zhang 22fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 23fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24fb8bd90fSChunyan Zhang 25fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 26fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 27fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 28fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 29fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 30fb8bd90fSChunyan Zhang 31fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 32fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 33fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 34fb8bd90fSChunyan Zhang 35fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 36fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 37fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 38fb8bd90fSChunyan Zhang 39fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 40fb8bd90fSChunyan Zhang 41fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 43fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 44fb8bd90fSChunyan Zhang 45fb8bd90fSChunyan Zhang /* 46fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 47fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 48fb8bd90fSChunyan Zhang * if this bit is cleared. 49fb8bd90fSChunyan Zhang * 1 : normal work 50fb8bd90fSChunyan Zhang * 0 : hardware reset 51fb8bd90fSChunyan Zhang */ 52fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 53fb8bd90fSChunyan Zhang 54fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 55fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 56fb8bd90fSChunyan Zhang 57fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 58fb8bd90fSChunyan Zhang 59fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 60fb8bd90fSChunyan Zhang u32 version; 61fb8bd90fSChunyan Zhang struct clk *clk_sdio; 62fb8bd90fSChunyan Zhang struct clk *clk_enable; 63fb8bd90fSChunyan Zhang u32 base_rate; 64fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 65fb8bd90fSChunyan Zhang }; 66fb8bd90fSChunyan Zhang 67fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 68fb8bd90fSChunyan Zhang 69fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 70fb8bd90fSChunyan Zhang { 71fb8bd90fSChunyan Zhang u16 val; 72fb8bd90fSChunyan Zhang 73fb8bd90fSChunyan Zhang /* set dll backup mode */ 74fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 75fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 76fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 77fb8bd90fSChunyan Zhang } 78fb8bd90fSChunyan Zhang 79fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 80fb8bd90fSChunyan Zhang { 81fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 82fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 83fb8bd90fSChunyan Zhang 84fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 85fb8bd90fSChunyan Zhang } 86fb8bd90fSChunyan Zhang 87fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 88fb8bd90fSChunyan Zhang { 89fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 90fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 91fb8bd90fSChunyan Zhang return; 92fb8bd90fSChunyan Zhang 93fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 94fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 95fb8bd90fSChunyan Zhang 96fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 97fb8bd90fSChunyan Zhang } 98fb8bd90fSChunyan Zhang 99fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 100fb8bd90fSChunyan Zhang { 101fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 102fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 103fb8bd90fSChunyan Zhang return; 104fb8bd90fSChunyan Zhang 105fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 106fb8bd90fSChunyan Zhang } 107fb8bd90fSChunyan Zhang 108fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 109fb8bd90fSChunyan Zhang { 110fb8bd90fSChunyan Zhang /* 111fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 112fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 113fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 114fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 115fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 116fb8bd90fSChunyan Zhang * around it. 117fb8bd90fSChunyan Zhang */ 118fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 119fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 120fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 121fb8bd90fSChunyan Zhang } 122fb8bd90fSChunyan Zhang 123fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 124fb8bd90fSChunyan Zhang } 125fb8bd90fSChunyan Zhang 126fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 127fb8bd90fSChunyan Zhang { 128fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 129fb8bd90fSChunyan Zhang 130fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 131fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 132fb8bd90fSChunyan Zhang } 133fb8bd90fSChunyan Zhang 134fb8bd90fSChunyan Zhang static inline void 135fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 136fb8bd90fSChunyan Zhang { 137fb8bd90fSChunyan Zhang u32 dll_dly_offset; 138fb8bd90fSChunyan Zhang 139fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 140fb8bd90fSChunyan Zhang if (en) 141fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 142fb8bd90fSChunyan Zhang else 143fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 144fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 145fb8bd90fSChunyan Zhang } 146fb8bd90fSChunyan Zhang 147fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 148fb8bd90fSChunyan Zhang { 149fb8bd90fSChunyan Zhang u32 div; 150fb8bd90fSChunyan Zhang 151fb8bd90fSChunyan Zhang /* select 2x clock source */ 152fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 153fb8bd90fSChunyan Zhang return 0; 154fb8bd90fSChunyan Zhang 155fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 156fb8bd90fSChunyan Zhang 157fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 158fb8bd90fSChunyan Zhang div++; 159fb8bd90fSChunyan Zhang 160fb8bd90fSChunyan Zhang if (div > SDHCI_SPRD_CLK_MAX_DIV) 161fb8bd90fSChunyan Zhang div = SDHCI_SPRD_CLK_MAX_DIV; 162fb8bd90fSChunyan Zhang 163fb8bd90fSChunyan Zhang if (div % 2) 164fb8bd90fSChunyan Zhang div = (div + 1) / 2; 165fb8bd90fSChunyan Zhang else 166fb8bd90fSChunyan Zhang div = div / 2; 167fb8bd90fSChunyan Zhang 168fb8bd90fSChunyan Zhang return div; 169fb8bd90fSChunyan Zhang } 170fb8bd90fSChunyan Zhang 171fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 172fb8bd90fSChunyan Zhang unsigned int clk) 173fb8bd90fSChunyan Zhang { 174fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 175fb8bd90fSChunyan Zhang u32 div, val, mask; 176fb8bd90fSChunyan Zhang 177fb8bd90fSChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 178fb8bd90fSChunyan Zhang 179fb8bd90fSChunyan Zhang clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 180fb8bd90fSChunyan Zhang sdhci_enable_clk(host, clk); 181fb8bd90fSChunyan Zhang 182fb8bd90fSChunyan Zhang /* enable auto gate sdhc_enable_auto_gate */ 183fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 184fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 185fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 186fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 187fb8bd90fSChunyan Zhang val |= mask; 188fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 189fb8bd90fSChunyan Zhang } 190fb8bd90fSChunyan Zhang } 191fb8bd90fSChunyan Zhang 192fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 193fb8bd90fSChunyan Zhang { 194fb8bd90fSChunyan Zhang bool en = false; 195fb8bd90fSChunyan Zhang 196fb8bd90fSChunyan Zhang if (clock == 0) { 197fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 198fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 199fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 200fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 201fb8bd90fSChunyan Zhang 202fb8bd90fSChunyan Zhang if (clock <= 400000) 203fb8bd90fSChunyan Zhang en = true; 204fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 205fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 206fb8bd90fSChunyan Zhang } else { 207fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 208fb8bd90fSChunyan Zhang } 209fb8bd90fSChunyan Zhang } 210fb8bd90fSChunyan Zhang 211fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 212fb8bd90fSChunyan Zhang { 213fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 214fb8bd90fSChunyan Zhang 215fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 216fb8bd90fSChunyan Zhang } 217fb8bd90fSChunyan Zhang 218fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 219fb8bd90fSChunyan Zhang { 220fb8bd90fSChunyan Zhang return 400000; 221fb8bd90fSChunyan Zhang } 222fb8bd90fSChunyan Zhang 223fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 224fb8bd90fSChunyan Zhang unsigned int timing) 225fb8bd90fSChunyan Zhang { 226fb8bd90fSChunyan Zhang u16 ctrl_2; 227fb8bd90fSChunyan Zhang 228fb8bd90fSChunyan Zhang if (timing == host->timing) 229fb8bd90fSChunyan Zhang return; 230fb8bd90fSChunyan Zhang 231fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 232fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 233fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 234fb8bd90fSChunyan Zhang switch (timing) { 235fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 236fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 237fb8bd90fSChunyan Zhang break; 238fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 239fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 240fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 241fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 242fb8bd90fSChunyan Zhang break; 243fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 244fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 245fb8bd90fSChunyan Zhang break; 246fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 247fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 248fb8bd90fSChunyan Zhang break; 249fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 250fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 251fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 252fb8bd90fSChunyan Zhang break; 253fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 254fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 255fb8bd90fSChunyan Zhang break; 256fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 257fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 258fb8bd90fSChunyan Zhang break; 259fb8bd90fSChunyan Zhang default: 260fb8bd90fSChunyan Zhang break; 261fb8bd90fSChunyan Zhang } 262fb8bd90fSChunyan Zhang 263fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 264fb8bd90fSChunyan Zhang } 265fb8bd90fSChunyan Zhang 266fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 267fb8bd90fSChunyan Zhang { 268fb8bd90fSChunyan Zhang int val; 269fb8bd90fSChunyan Zhang 270fb8bd90fSChunyan Zhang /* 271fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 272fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 273fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 274fb8bd90fSChunyan Zhang * not be cleared. 275fb8bd90fSChunyan Zhang */ 276fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 277fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 278fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 279fb8bd90fSChunyan Zhang /* wait for 10 us */ 280fb8bd90fSChunyan Zhang usleep_range(10, 20); 281fb8bd90fSChunyan Zhang 282fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 283fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 284fb8bd90fSChunyan Zhang usleep_range(300, 500); 285fb8bd90fSChunyan Zhang } 286fb8bd90fSChunyan Zhang 287fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 288fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 289fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 290fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 291fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 292fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 293fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 294fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 295fb8bd90fSChunyan Zhang .reset = sdhci_reset, 296fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 297fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 298fb8bd90fSChunyan Zhang }; 299fb8bd90fSChunyan Zhang 300fb8bd90fSChunyan Zhang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 301fb8bd90fSChunyan Zhang { 302fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 303fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 304fb8bd90fSChunyan Zhang 305fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 306fb8bd90fSChunyan Zhang 307fb8bd90fSChunyan Zhang /* 308fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 309fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 310fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 311fb8bd90fSChunyan Zhang */ 312fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 313fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 314fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 315fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 316fb8bd90fSChunyan Zhang 317fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 318fb8bd90fSChunyan Zhang } 319fb8bd90fSChunyan Zhang 320fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 321fb8bd90fSChunyan Zhang .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 322fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 323fb8bd90fSChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 324fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 325fb8bd90fSChunyan Zhang }; 326fb8bd90fSChunyan Zhang 327fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 328fb8bd90fSChunyan Zhang { 329fb8bd90fSChunyan Zhang struct sdhci_host *host; 330fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 331fb8bd90fSChunyan Zhang struct clk *clk; 332fb8bd90fSChunyan Zhang int ret = 0; 333fb8bd90fSChunyan Zhang 334fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 335fb8bd90fSChunyan Zhang if (IS_ERR(host)) 336fb8bd90fSChunyan Zhang return PTR_ERR(host); 337fb8bd90fSChunyan Zhang 338fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 339fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 340fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 341fb8bd90fSChunyan Zhang 342fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 343fb8bd90fSChunyan Zhang MMC_CAP_ERASE | MMC_CAP_CMD23; 344fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 345fb8bd90fSChunyan Zhang if (ret) 346fb8bd90fSChunyan Zhang goto pltfm_free; 347fb8bd90fSChunyan Zhang 348fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 349fb8bd90fSChunyan Zhang 350fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 351fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 352fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 353fb8bd90fSChunyan Zhang goto pltfm_free; 354fb8bd90fSChunyan Zhang } 355fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 356fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 357fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 358fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 359fb8bd90fSChunyan Zhang 360fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 361fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 362fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 363fb8bd90fSChunyan Zhang goto pltfm_free; 364fb8bd90fSChunyan Zhang } 365fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 366fb8bd90fSChunyan Zhang 367fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 368fb8bd90fSChunyan Zhang if (ret) 369fb8bd90fSChunyan Zhang goto pltfm_free; 370fb8bd90fSChunyan Zhang 371fb8bd90fSChunyan Zhang clk_prepare_enable(sprd_host->clk_enable); 372fb8bd90fSChunyan Zhang if (ret) 373fb8bd90fSChunyan Zhang goto clk_disable; 374fb8bd90fSChunyan Zhang 375fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 376fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 377fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 378fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 379fb8bd90fSChunyan Zhang 380fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 381fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 382fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 383fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 384fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 385fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 386fb8bd90fSChunyan Zhang 387fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 388fb8bd90fSChunyan Zhang 389fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 390fb8bd90fSChunyan Zhang if (ret) 391fb8bd90fSChunyan Zhang goto pm_runtime_disable; 392fb8bd90fSChunyan Zhang 393fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 394fb8bd90fSChunyan Zhang 395fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 396fb8bd90fSChunyan Zhang if (ret) 397fb8bd90fSChunyan Zhang goto err_cleanup_host; 398fb8bd90fSChunyan Zhang 399fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 400fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 401fb8bd90fSChunyan Zhang 402fb8bd90fSChunyan Zhang return 0; 403fb8bd90fSChunyan Zhang 404fb8bd90fSChunyan Zhang err_cleanup_host: 405fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 406fb8bd90fSChunyan Zhang 407fb8bd90fSChunyan Zhang pm_runtime_disable: 408fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 409fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 410fb8bd90fSChunyan Zhang 411fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 412fb8bd90fSChunyan Zhang 413fb8bd90fSChunyan Zhang clk_disable: 414fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 415fb8bd90fSChunyan Zhang 416fb8bd90fSChunyan Zhang pltfm_free: 417fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 418fb8bd90fSChunyan Zhang return ret; 419fb8bd90fSChunyan Zhang } 420fb8bd90fSChunyan Zhang 421fb8bd90fSChunyan Zhang static int sdhci_sprd_remove(struct platform_device *pdev) 422fb8bd90fSChunyan Zhang { 423fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 424fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 425fb8bd90fSChunyan Zhang struct mmc_host *mmc = host->mmc; 426fb8bd90fSChunyan Zhang 427fb8bd90fSChunyan Zhang mmc_remove_host(mmc); 428fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 429fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 430fb8bd90fSChunyan Zhang 431fb8bd90fSChunyan Zhang mmc_free_host(mmc); 432fb8bd90fSChunyan Zhang 433fb8bd90fSChunyan Zhang return 0; 434fb8bd90fSChunyan Zhang } 435fb8bd90fSChunyan Zhang 436fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 437fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 438fb8bd90fSChunyan Zhang { } 439fb8bd90fSChunyan Zhang }; 440fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 441fb8bd90fSChunyan Zhang 442fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 443fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 444fb8bd90fSChunyan Zhang { 445fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 446fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 447fb8bd90fSChunyan Zhang 448fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 449fb8bd90fSChunyan Zhang 450fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 451fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 452fb8bd90fSChunyan Zhang 453fb8bd90fSChunyan Zhang return 0; 454fb8bd90fSChunyan Zhang } 455fb8bd90fSChunyan Zhang 456fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 457fb8bd90fSChunyan Zhang { 458fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 459fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 460fb8bd90fSChunyan Zhang int ret; 461fb8bd90fSChunyan Zhang 462fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_enable); 463fb8bd90fSChunyan Zhang if (ret) 464fb8bd90fSChunyan Zhang return ret; 465fb8bd90fSChunyan Zhang 466fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 467fb8bd90fSChunyan Zhang if (ret) { 468fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 469fb8bd90fSChunyan Zhang return ret; 470fb8bd90fSChunyan Zhang } 471fb8bd90fSChunyan Zhang 472fb8bd90fSChunyan Zhang sdhci_runtime_resume_host(host); 473fb8bd90fSChunyan Zhang 474fb8bd90fSChunyan Zhang return 0; 475fb8bd90fSChunyan Zhang } 476fb8bd90fSChunyan Zhang #endif 477fb8bd90fSChunyan Zhang 478fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 479fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 480fb8bd90fSChunyan Zhang pm_runtime_force_resume) 481fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 482fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 483fb8bd90fSChunyan Zhang }; 484fb8bd90fSChunyan Zhang 485fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 486fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 487fb8bd90fSChunyan Zhang .remove = sdhci_sprd_remove, 488fb8bd90fSChunyan Zhang .driver = { 489fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 490fb8bd90fSChunyan Zhang .of_match_table = of_match_ptr(sdhci_sprd_of_match), 491fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 492fb8bd90fSChunyan Zhang }, 493fb8bd90fSChunyan Zhang }; 494fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 495fb8bd90fSChunyan Zhang 496fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 497fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 498fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 499