1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 11fb8bd90fSChunyan Zhang #include <linux/module.h> 12fb8bd90fSChunyan Zhang #include <linux/of.h> 13fb8bd90fSChunyan Zhang #include <linux/of_device.h> 14fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 1529ca763fSBaolin Wang #include <linux/pinctrl/consumer.h> 16fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 17fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 18fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 19fb8bd90fSChunyan Zhang #include <linux/slab.h> 20fb8bd90fSChunyan Zhang 21fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 22fb8bd90fSChunyan Zhang 23fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 24fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 25fb8bd90fSChunyan Zhang 2687a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 2787a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 2887a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 2987a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3187a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3287a395c2SBaolin Wang 335f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 345f2f4e0dSBaolin Wang 35fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 36fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 37fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 39fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 40fb8bd90fSChunyan Zhang 41fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 43fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 44fb8bd90fSChunyan Zhang 45fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 46fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 47fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 48fb8bd90fSChunyan Zhang 49fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 50fb8bd90fSChunyan Zhang 51fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 52fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 53fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 54494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 55fb8bd90fSChunyan Zhang 56fb8bd90fSChunyan Zhang /* 57fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 58fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 59fb8bd90fSChunyan Zhang * if this bit is cleared. 60fb8bd90fSChunyan Zhang * 1 : normal work 61fb8bd90fSChunyan Zhang * 0 : hardware reset 62fb8bd90fSChunyan Zhang */ 63fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 64fb8bd90fSChunyan Zhang 65fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 66fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 67fb8bd90fSChunyan Zhang 68fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 6987a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 70fb8bd90fSChunyan Zhang 71fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 72fb8bd90fSChunyan Zhang u32 version; 73fb8bd90fSChunyan Zhang struct clk *clk_sdio; 74fb8bd90fSChunyan Zhang struct clk *clk_enable; 75ebd88a38SBaolin Wang struct clk *clk_2x_enable; 7629ca763fSBaolin Wang struct pinctrl *pinctrl; 7729ca763fSBaolin Wang struct pinctrl_state *pins_uhs; 7829ca763fSBaolin Wang struct pinctrl_state *pins_default; 79fb8bd90fSChunyan Zhang u32 base_rate; 80fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 815f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 825f2f4e0dSBaolin Wang }; 835f2f4e0dSBaolin Wang 845f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg { 855f2f4e0dSBaolin Wang const char *property; 865f2f4e0dSBaolin Wang u8 timing; 875f2f4e0dSBaolin Wang }; 885f2f4e0dSBaolin Wang 895f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 905f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 915f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 925f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 935f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 945f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 955f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 965f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 975f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 985f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 99fb8bd90fSChunyan Zhang }; 100fb8bd90fSChunyan Zhang 101fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 102fb8bd90fSChunyan Zhang 103fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 104fb8bd90fSChunyan Zhang { 105fb8bd90fSChunyan Zhang u16 val; 106fb8bd90fSChunyan Zhang 107fb8bd90fSChunyan Zhang /* set dll backup mode */ 108fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 109fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 110fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 111fb8bd90fSChunyan Zhang } 112fb8bd90fSChunyan Zhang 113fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 114fb8bd90fSChunyan Zhang { 115fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 116fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 117fb8bd90fSChunyan Zhang 118fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 119fb8bd90fSChunyan Zhang } 120fb8bd90fSChunyan Zhang 121fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 122fb8bd90fSChunyan Zhang { 123fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 124fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 125fb8bd90fSChunyan Zhang return; 126fb8bd90fSChunyan Zhang 127fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 128fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 129fb8bd90fSChunyan Zhang 130fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 131fb8bd90fSChunyan Zhang } 132fb8bd90fSChunyan Zhang 133fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 134fb8bd90fSChunyan Zhang { 135fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 136fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 137fb8bd90fSChunyan Zhang return; 138fb8bd90fSChunyan Zhang 139fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 140fb8bd90fSChunyan Zhang } 141fb8bd90fSChunyan Zhang 142fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 143fb8bd90fSChunyan Zhang { 144fb8bd90fSChunyan Zhang /* 145fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 146fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 147fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 148fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 149fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 150fb8bd90fSChunyan Zhang * around it. 151fb8bd90fSChunyan Zhang */ 152fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 153fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 154fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 155fb8bd90fSChunyan Zhang } 156fb8bd90fSChunyan Zhang 157fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 158fb8bd90fSChunyan Zhang } 159fb8bd90fSChunyan Zhang 160fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 161fb8bd90fSChunyan Zhang { 162fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 163fb8bd90fSChunyan Zhang 164fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 165fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 166fb8bd90fSChunyan Zhang } 167fb8bd90fSChunyan Zhang 168494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 169494c11e1SBaolin Wang { 170494c11e1SBaolin Wang u16 ctrl; 171494c11e1SBaolin Wang 172494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 173494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 174494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 175494c11e1SBaolin Wang } 176494c11e1SBaolin Wang 177fb8bd90fSChunyan Zhang static inline void 178fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 179fb8bd90fSChunyan Zhang { 180fb8bd90fSChunyan Zhang u32 dll_dly_offset; 181fb8bd90fSChunyan Zhang 182fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 183fb8bd90fSChunyan Zhang if (en) 184fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 185fb8bd90fSChunyan Zhang else 186fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 187fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 188fb8bd90fSChunyan Zhang } 189fb8bd90fSChunyan Zhang 190fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 191fb8bd90fSChunyan Zhang { 192fb8bd90fSChunyan Zhang u32 div; 193fb8bd90fSChunyan Zhang 194fb8bd90fSChunyan Zhang /* select 2x clock source */ 195fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 196fb8bd90fSChunyan Zhang return 0; 197fb8bd90fSChunyan Zhang 198fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 199fb8bd90fSChunyan Zhang 200fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 201fb8bd90fSChunyan Zhang div++; 202fb8bd90fSChunyan Zhang 203fb8bd90fSChunyan Zhang if (div > SDHCI_SPRD_CLK_MAX_DIV) 204fb8bd90fSChunyan Zhang div = SDHCI_SPRD_CLK_MAX_DIV; 205fb8bd90fSChunyan Zhang 206fb8bd90fSChunyan Zhang if (div % 2) 207fb8bd90fSChunyan Zhang div = (div + 1) / 2; 208fb8bd90fSChunyan Zhang else 209fb8bd90fSChunyan Zhang div = div / 2; 210fb8bd90fSChunyan Zhang 211fb8bd90fSChunyan Zhang return div; 212fb8bd90fSChunyan Zhang } 213fb8bd90fSChunyan Zhang 214fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 215fb8bd90fSChunyan Zhang unsigned int clk) 216fb8bd90fSChunyan Zhang { 217fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 218fb8bd90fSChunyan Zhang u32 div, val, mask; 219fb8bd90fSChunyan Zhang 220efdaf275SChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 221fb8bd90fSChunyan Zhang 222efdaf275SChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 223efdaf275SChunyan Zhang div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 224efdaf275SChunyan Zhang sdhci_enable_clk(host, div); 225fb8bd90fSChunyan Zhang 226fb8bd90fSChunyan Zhang /* enable auto gate sdhc_enable_auto_gate */ 227fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 228fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 229fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 230fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 231fb8bd90fSChunyan Zhang val |= mask; 232fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 233fb8bd90fSChunyan Zhang } 234fb8bd90fSChunyan Zhang } 235fb8bd90fSChunyan Zhang 23687a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 23787a395c2SBaolin Wang { 23887a395c2SBaolin Wang u32 tmp; 23987a395c2SBaolin Wang 24087a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24187a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 24287a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 24387a395c2SBaolin Wang /* wait 1ms */ 24487a395c2SBaolin Wang usleep_range(1000, 1250); 24587a395c2SBaolin Wang 24687a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24787a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 24887a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 24987a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 25087a395c2SBaolin Wang /* wait 1ms */ 25187a395c2SBaolin Wang usleep_range(1000, 1250); 25287a395c2SBaolin Wang 25387a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 25487a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 25587a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 25687a395c2SBaolin Wang /* wait 1ms */ 25787a395c2SBaolin Wang usleep_range(1000, 1250); 25887a395c2SBaolin Wang } 25987a395c2SBaolin Wang 260fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 261fb8bd90fSChunyan Zhang { 26287a395c2SBaolin Wang bool en = false, clk_changed = false; 263fb8bd90fSChunyan Zhang 264fb8bd90fSChunyan Zhang if (clock == 0) { 265fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 266fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 267fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 268fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 269fb8bd90fSChunyan Zhang 270fb8bd90fSChunyan Zhang if (clock <= 400000) 271fb8bd90fSChunyan Zhang en = true; 272fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 273fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 27487a395c2SBaolin Wang clk_changed = true; 275fb8bd90fSChunyan Zhang } else { 276fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 277fb8bd90fSChunyan Zhang } 27887a395c2SBaolin Wang 27987a395c2SBaolin Wang /* 28087a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 28187a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 28287a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 28387a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 28487a395c2SBaolin Wang */ 28587a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 28687a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 287fb8bd90fSChunyan Zhang } 288fb8bd90fSChunyan Zhang 289fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 290fb8bd90fSChunyan Zhang { 291fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 292fb8bd90fSChunyan Zhang 293fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 294fb8bd90fSChunyan Zhang } 295fb8bd90fSChunyan Zhang 296fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 297fb8bd90fSChunyan Zhang { 298fb8bd90fSChunyan Zhang return 400000; 299fb8bd90fSChunyan Zhang } 300fb8bd90fSChunyan Zhang 301fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 302fb8bd90fSChunyan Zhang unsigned int timing) 303fb8bd90fSChunyan Zhang { 3045f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 3055f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc; 3065f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 307fb8bd90fSChunyan Zhang u16 ctrl_2; 308fb8bd90fSChunyan Zhang 309fb8bd90fSChunyan Zhang if (timing == host->timing) 310fb8bd90fSChunyan Zhang return; 311fb8bd90fSChunyan Zhang 312fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 313fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 314fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 315fb8bd90fSChunyan Zhang switch (timing) { 316fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 317fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 318fb8bd90fSChunyan Zhang break; 319fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 320fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 321fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 322fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 323fb8bd90fSChunyan Zhang break; 324fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 325fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 326fb8bd90fSChunyan Zhang break; 327fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 328fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 329fb8bd90fSChunyan Zhang break; 330fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 331fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 332fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 333fb8bd90fSChunyan Zhang break; 334fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 335fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 336fb8bd90fSChunyan Zhang break; 337fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 338fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 339fb8bd90fSChunyan Zhang break; 340fb8bd90fSChunyan Zhang default: 341fb8bd90fSChunyan Zhang break; 342fb8bd90fSChunyan Zhang } 343fb8bd90fSChunyan Zhang 344fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 3455f2f4e0dSBaolin Wang 3465f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe) 3475f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 348fb8bd90fSChunyan Zhang } 349fb8bd90fSChunyan Zhang 350fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 351fb8bd90fSChunyan Zhang { 352fb8bd90fSChunyan Zhang int val; 353fb8bd90fSChunyan Zhang 354fb8bd90fSChunyan Zhang /* 355fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 356fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 357fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 358fb8bd90fSChunyan Zhang * not be cleared. 359fb8bd90fSChunyan Zhang */ 360fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 361fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 362fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 363fb8bd90fSChunyan Zhang /* wait for 10 us */ 364fb8bd90fSChunyan Zhang usleep_range(10, 20); 365fb8bd90fSChunyan Zhang 366fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 367fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 368fb8bd90fSChunyan Zhang usleep_range(300, 500); 369fb8bd90fSChunyan Zhang } 370fb8bd90fSChunyan Zhang 3717486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3727486831dSBaolin Wang { 3737486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 3747486831dSBaolin Wang return 1 << 31; 3757486831dSBaolin Wang } 3767486831dSBaolin Wang 377fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 378fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 379fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 380fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 381fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 382fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 383fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 384fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 385fb8bd90fSChunyan Zhang .reset = sdhci_reset, 386fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 387fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 3887486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 389fb8bd90fSChunyan Zhang }; 390fb8bd90fSChunyan Zhang 391fb8bd90fSChunyan Zhang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 392fb8bd90fSChunyan Zhang { 393fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 394fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 395fb8bd90fSChunyan Zhang 396fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 397fb8bd90fSChunyan Zhang 398fb8bd90fSChunyan Zhang /* 399fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 400fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 401fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 402fb8bd90fSChunyan Zhang */ 403fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 404fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 405fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 406fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 407fb8bd90fSChunyan Zhang 408fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 409fb8bd90fSChunyan Zhang } 410fb8bd90fSChunyan Zhang 411eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 412eef9e0a6SBaolin Wang { 41329ca763fSBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 41429ca763fSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 415eef9e0a6SBaolin Wang int ret; 416eef9e0a6SBaolin Wang 417eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) { 418eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios); 419eef9e0a6SBaolin Wang if (ret) { 420eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n", 421eef9e0a6SBaolin Wang mmc_hostname(mmc)); 422eef9e0a6SBaolin Wang return ret; 423eef9e0a6SBaolin Wang } 424eef9e0a6SBaolin Wang } 425eef9e0a6SBaolin Wang 42629ca763fSBaolin Wang if (IS_ERR(sprd_host->pinctrl)) 42729ca763fSBaolin Wang return 0; 42829ca763fSBaolin Wang 42929ca763fSBaolin Wang switch (ios->signal_voltage) { 43029ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_180: 43129ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 43229ca763fSBaolin Wang sprd_host->pins_uhs); 43329ca763fSBaolin Wang if (ret) { 43429ca763fSBaolin Wang pr_err("%s: failed to select uhs pin state\n", 43529ca763fSBaolin Wang mmc_hostname(mmc)); 43629ca763fSBaolin Wang return ret; 43729ca763fSBaolin Wang } 43829ca763fSBaolin Wang break; 43929ca763fSBaolin Wang 44029ca763fSBaolin Wang default: 44129ca763fSBaolin Wang /* fall-through */ 44229ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_330: 44329ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 44429ca763fSBaolin Wang sprd_host->pins_default); 44529ca763fSBaolin Wang if (ret) { 44629ca763fSBaolin Wang pr_err("%s: failed to select default pin state\n", 44729ca763fSBaolin Wang mmc_hostname(mmc)); 44829ca763fSBaolin Wang return ret; 44929ca763fSBaolin Wang } 45029ca763fSBaolin Wang break; 45129ca763fSBaolin Wang } 45229ca763fSBaolin Wang 45329ca763fSBaolin Wang /* Wait for 300 ~ 500 us for pin state stable */ 45429ca763fSBaolin Wang usleep_range(300, 500); 45529ca763fSBaolin Wang sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 45629ca763fSBaolin Wang 457eef9e0a6SBaolin Wang return 0; 458eef9e0a6SBaolin Wang } 459eef9e0a6SBaolin Wang 460494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 461494c11e1SBaolin Wang struct mmc_ios *ios) 462494c11e1SBaolin Wang { 463494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 4645f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 4655f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 466494c11e1SBaolin Wang u16 ctrl_2; 467494c11e1SBaolin Wang 468494c11e1SBaolin Wang if (!ios->enhanced_strobe) 469494c11e1SBaolin Wang return; 470494c11e1SBaolin Wang 471494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 472494c11e1SBaolin Wang 473494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 474494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 475494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 476494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 477494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 478494c11e1SBaolin Wang 479494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 4805f2f4e0dSBaolin Wang 4815f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 4825f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 4835f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY); 4845f2f4e0dSBaolin Wang } 4855f2f4e0dSBaolin Wang 4865f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 4875f2f4e0dSBaolin Wang struct device_node *np) 4885f2f4e0dSBaolin Wang { 4895f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 4905f2f4e0dSBaolin Wang int ret, i, index; 4915f2f4e0dSBaolin Wang u32 val[4]; 4925f2f4e0dSBaolin Wang 4935f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 4945f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np, 4955f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4); 4965f2f4e0dSBaolin Wang if (ret) 4975f2f4e0dSBaolin Wang continue; 4985f2f4e0dSBaolin Wang 4995f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing; 5005f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 5015f2f4e0dSBaolin Wang } 502494c11e1SBaolin Wang } 503494c11e1SBaolin Wang 504fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 505fb8bd90fSChunyan Zhang .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 506fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 507fb8bd90fSChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 508fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 509fb8bd90fSChunyan Zhang }; 510fb8bd90fSChunyan Zhang 511fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 512fb8bd90fSChunyan Zhang { 513fb8bd90fSChunyan Zhang struct sdhci_host *host; 514fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 515fb8bd90fSChunyan Zhang struct clk *clk; 516fb8bd90fSChunyan Zhang int ret = 0; 517fb8bd90fSChunyan Zhang 518fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 519fb8bd90fSChunyan Zhang if (IS_ERR(host)) 520fb8bd90fSChunyan Zhang return PTR_ERR(host); 521fb8bd90fSChunyan Zhang 522fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 523fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 524fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 525494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 526494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 527eef9e0a6SBaolin Wang /* 528eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage 529eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator 530eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control 531eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage. 532eef9e0a6SBaolin Wang */ 533eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch = 534eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch; 535fb8bd90fSChunyan Zhang 536fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 537fb8bd90fSChunyan Zhang MMC_CAP_ERASE | MMC_CAP_CMD23; 538fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 539fb8bd90fSChunyan Zhang if (ret) 540fb8bd90fSChunyan Zhang goto pltfm_free; 541fb8bd90fSChunyan Zhang 542fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 5435f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 544fb8bd90fSChunyan Zhang 54529ca763fSBaolin Wang sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 54629ca763fSBaolin Wang if (!IS_ERR(sprd_host->pinctrl)) { 54729ca763fSBaolin Wang sprd_host->pins_uhs = 54829ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 54929ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_uhs)) { 55029ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_uhs); 55129ca763fSBaolin Wang goto pltfm_free; 55229ca763fSBaolin Wang } 55329ca763fSBaolin Wang 55429ca763fSBaolin Wang sprd_host->pins_default = 55529ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "default"); 55629ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_default)) { 55729ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_default); 55829ca763fSBaolin Wang goto pltfm_free; 55929ca763fSBaolin Wang } 56029ca763fSBaolin Wang } 56129ca763fSBaolin Wang 562fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 563fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 564fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 565fb8bd90fSChunyan Zhang goto pltfm_free; 566fb8bd90fSChunyan Zhang } 567fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 568fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 569fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 570fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 571fb8bd90fSChunyan Zhang 572fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 573fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 574fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 575fb8bd90fSChunyan Zhang goto pltfm_free; 576fb8bd90fSChunyan Zhang } 577fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 578fb8bd90fSChunyan Zhang 579ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 580ebd88a38SBaolin Wang if (!IS_ERR(clk)) 581ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 582ebd88a38SBaolin Wang 583fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 584fb8bd90fSChunyan Zhang if (ret) 585fb8bd90fSChunyan Zhang goto pltfm_free; 586fb8bd90fSChunyan Zhang 5871d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 588fb8bd90fSChunyan Zhang if (ret) 589fb8bd90fSChunyan Zhang goto clk_disable; 590fb8bd90fSChunyan Zhang 591ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 592ebd88a38SBaolin Wang if (ret) 593ebd88a38SBaolin Wang goto clk_disable2; 594ebd88a38SBaolin Wang 595fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 596fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 597fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 598fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 599fb8bd90fSChunyan Zhang 600fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 601fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 602fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 603fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 604fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 605fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 606fb8bd90fSChunyan Zhang 607fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 608fb8bd90fSChunyan Zhang 609fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 610fb8bd90fSChunyan Zhang if (ret) 611fb8bd90fSChunyan Zhang goto pm_runtime_disable; 612fb8bd90fSChunyan Zhang 613fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 614fb8bd90fSChunyan Zhang 615fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 616fb8bd90fSChunyan Zhang if (ret) 617fb8bd90fSChunyan Zhang goto err_cleanup_host; 618fb8bd90fSChunyan Zhang 619fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 620fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 621fb8bd90fSChunyan Zhang 622fb8bd90fSChunyan Zhang return 0; 623fb8bd90fSChunyan Zhang 624fb8bd90fSChunyan Zhang err_cleanup_host: 625fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 626fb8bd90fSChunyan Zhang 627fb8bd90fSChunyan Zhang pm_runtime_disable: 628fc62113bSBaolin Wang pm_runtime_put_noidle(&pdev->dev); 629fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 630fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 631fb8bd90fSChunyan Zhang 632ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 633ebd88a38SBaolin Wang 634ebd88a38SBaolin Wang clk_disable2: 635fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 636fb8bd90fSChunyan Zhang 637fb8bd90fSChunyan Zhang clk_disable: 638fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 639fb8bd90fSChunyan Zhang 640fb8bd90fSChunyan Zhang pltfm_free: 641fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 642fb8bd90fSChunyan Zhang return ret; 643fb8bd90fSChunyan Zhang } 644fb8bd90fSChunyan Zhang 645fb8bd90fSChunyan Zhang static int sdhci_sprd_remove(struct platform_device *pdev) 646fb8bd90fSChunyan Zhang { 647fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 648fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 649fb8bd90fSChunyan Zhang struct mmc_host *mmc = host->mmc; 650fb8bd90fSChunyan Zhang 651fb8bd90fSChunyan Zhang mmc_remove_host(mmc); 652fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 653fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 654ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 655fb8bd90fSChunyan Zhang 656fb8bd90fSChunyan Zhang mmc_free_host(mmc); 657fb8bd90fSChunyan Zhang 658fb8bd90fSChunyan Zhang return 0; 659fb8bd90fSChunyan Zhang } 660fb8bd90fSChunyan Zhang 661fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 662fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 663fb8bd90fSChunyan Zhang { } 664fb8bd90fSChunyan Zhang }; 665fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 666fb8bd90fSChunyan Zhang 667fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 668fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 669fb8bd90fSChunyan Zhang { 670fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 671fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 672fb8bd90fSChunyan Zhang 673fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 674fb8bd90fSChunyan Zhang 675fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 676fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 677ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 678fb8bd90fSChunyan Zhang 679fb8bd90fSChunyan Zhang return 0; 680fb8bd90fSChunyan Zhang } 681fb8bd90fSChunyan Zhang 682fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 683fb8bd90fSChunyan Zhang { 684fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 685fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 686fb8bd90fSChunyan Zhang int ret; 687fb8bd90fSChunyan Zhang 688ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 689fb8bd90fSChunyan Zhang if (ret) 690fb8bd90fSChunyan Zhang return ret; 691fb8bd90fSChunyan Zhang 692ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 693ebd88a38SBaolin Wang if (ret) 694ebd88a38SBaolin Wang goto clk_2x_disable; 695ebd88a38SBaolin Wang 696fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 697ebd88a38SBaolin Wang if (ret) 698ebd88a38SBaolin Wang goto clk_disable; 699fb8bd90fSChunyan Zhang 700c6303c5dSBaolin Wang sdhci_runtime_resume_host(host, 1); 701fb8bd90fSChunyan Zhang return 0; 702ebd88a38SBaolin Wang 703ebd88a38SBaolin Wang clk_disable: 704ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 705ebd88a38SBaolin Wang 706ebd88a38SBaolin Wang clk_2x_disable: 707ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 708ebd88a38SBaolin Wang 709ebd88a38SBaolin Wang return ret; 710fb8bd90fSChunyan Zhang } 711fb8bd90fSChunyan Zhang #endif 712fb8bd90fSChunyan Zhang 713fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 714fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 715fb8bd90fSChunyan Zhang pm_runtime_force_resume) 716fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 717fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 718fb8bd90fSChunyan Zhang }; 719fb8bd90fSChunyan Zhang 720fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 721fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 722fb8bd90fSChunyan Zhang .remove = sdhci_sprd_remove, 723fb8bd90fSChunyan Zhang .driver = { 724fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 725fb8bd90fSChunyan Zhang .of_match_table = of_match_ptr(sdhci_sprd_of_match), 726fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 727fb8bd90fSChunyan Zhang }, 728fb8bd90fSChunyan Zhang }; 729fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 730fb8bd90fSChunyan Zhang 731fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 732fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 733fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 734