1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 11fb8bd90fSChunyan Zhang #include <linux/module.h> 12fb8bd90fSChunyan Zhang #include <linux/of.h> 13fb8bd90fSChunyan Zhang #include <linux/of_device.h> 14fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 15fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 16fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 17fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 18fb8bd90fSChunyan Zhang #include <linux/slab.h> 19fb8bd90fSChunyan Zhang 20fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 21fb8bd90fSChunyan Zhang 22fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 23fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24fb8bd90fSChunyan Zhang 2587a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 2687a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 2787a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 2887a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 2987a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3187a395c2SBaolin Wang 325f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 335f2f4e0dSBaolin Wang 34fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 35fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 36fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 37fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 39fb8bd90fSChunyan Zhang 40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 41fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 43fb8bd90fSChunyan Zhang 44fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 45fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 46fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 47fb8bd90fSChunyan Zhang 48fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 49fb8bd90fSChunyan Zhang 50fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 51fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 52fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 53494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 54fb8bd90fSChunyan Zhang 55fb8bd90fSChunyan Zhang /* 56fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 57fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 58fb8bd90fSChunyan Zhang * if this bit is cleared. 59fb8bd90fSChunyan Zhang * 1 : normal work 60fb8bd90fSChunyan Zhang * 0 : hardware reset 61fb8bd90fSChunyan Zhang */ 62fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 63fb8bd90fSChunyan Zhang 64fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 65fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 66fb8bd90fSChunyan Zhang 67fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 6887a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 69fb8bd90fSChunyan Zhang 70fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 71fb8bd90fSChunyan Zhang u32 version; 72fb8bd90fSChunyan Zhang struct clk *clk_sdio; 73fb8bd90fSChunyan Zhang struct clk *clk_enable; 74ebd88a38SBaolin Wang struct clk *clk_2x_enable; 75fb8bd90fSChunyan Zhang u32 base_rate; 76fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 775f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 785f2f4e0dSBaolin Wang }; 795f2f4e0dSBaolin Wang 805f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg { 815f2f4e0dSBaolin Wang const char *property; 825f2f4e0dSBaolin Wang u8 timing; 835f2f4e0dSBaolin Wang }; 845f2f4e0dSBaolin Wang 855f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 865f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 875f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 885f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 895f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 905f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 915f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 925f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 935f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 945f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 95fb8bd90fSChunyan Zhang }; 96fb8bd90fSChunyan Zhang 97fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 98fb8bd90fSChunyan Zhang 99fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 100fb8bd90fSChunyan Zhang { 101fb8bd90fSChunyan Zhang u16 val; 102fb8bd90fSChunyan Zhang 103fb8bd90fSChunyan Zhang /* set dll backup mode */ 104fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 105fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 106fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 107fb8bd90fSChunyan Zhang } 108fb8bd90fSChunyan Zhang 109fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 110fb8bd90fSChunyan Zhang { 111fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 112fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 113fb8bd90fSChunyan Zhang 114fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 115fb8bd90fSChunyan Zhang } 116fb8bd90fSChunyan Zhang 117fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 118fb8bd90fSChunyan Zhang { 119fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 120fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 121fb8bd90fSChunyan Zhang return; 122fb8bd90fSChunyan Zhang 123fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 124fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 125fb8bd90fSChunyan Zhang 126fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 127fb8bd90fSChunyan Zhang } 128fb8bd90fSChunyan Zhang 129fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 130fb8bd90fSChunyan Zhang { 131fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 132fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 133fb8bd90fSChunyan Zhang return; 134fb8bd90fSChunyan Zhang 135fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 136fb8bd90fSChunyan Zhang } 137fb8bd90fSChunyan Zhang 138fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 139fb8bd90fSChunyan Zhang { 140fb8bd90fSChunyan Zhang /* 141fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 142fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 143fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 144fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 145fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 146fb8bd90fSChunyan Zhang * around it. 147fb8bd90fSChunyan Zhang */ 148fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 149fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 150fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 151fb8bd90fSChunyan Zhang } 152fb8bd90fSChunyan Zhang 153fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 154fb8bd90fSChunyan Zhang } 155fb8bd90fSChunyan Zhang 156fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 157fb8bd90fSChunyan Zhang { 158fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 159fb8bd90fSChunyan Zhang 160fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 161fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 162fb8bd90fSChunyan Zhang } 163fb8bd90fSChunyan Zhang 164494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 165494c11e1SBaolin Wang { 166494c11e1SBaolin Wang u16 ctrl; 167494c11e1SBaolin Wang 168494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 169494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 170494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 171494c11e1SBaolin Wang } 172494c11e1SBaolin Wang 173fb8bd90fSChunyan Zhang static inline void 174fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 175fb8bd90fSChunyan Zhang { 176fb8bd90fSChunyan Zhang u32 dll_dly_offset; 177fb8bd90fSChunyan Zhang 178fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 179fb8bd90fSChunyan Zhang if (en) 180fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 181fb8bd90fSChunyan Zhang else 182fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 183fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 184fb8bd90fSChunyan Zhang } 185fb8bd90fSChunyan Zhang 186fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 187fb8bd90fSChunyan Zhang { 188fb8bd90fSChunyan Zhang u32 div; 189fb8bd90fSChunyan Zhang 190fb8bd90fSChunyan Zhang /* select 2x clock source */ 191fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 192fb8bd90fSChunyan Zhang return 0; 193fb8bd90fSChunyan Zhang 194fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 195fb8bd90fSChunyan Zhang 196fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 197fb8bd90fSChunyan Zhang div++; 198fb8bd90fSChunyan Zhang 199fb8bd90fSChunyan Zhang if (div > SDHCI_SPRD_CLK_MAX_DIV) 200fb8bd90fSChunyan Zhang div = SDHCI_SPRD_CLK_MAX_DIV; 201fb8bd90fSChunyan Zhang 202fb8bd90fSChunyan Zhang if (div % 2) 203fb8bd90fSChunyan Zhang div = (div + 1) / 2; 204fb8bd90fSChunyan Zhang else 205fb8bd90fSChunyan Zhang div = div / 2; 206fb8bd90fSChunyan Zhang 207fb8bd90fSChunyan Zhang return div; 208fb8bd90fSChunyan Zhang } 209fb8bd90fSChunyan Zhang 210fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 211fb8bd90fSChunyan Zhang unsigned int clk) 212fb8bd90fSChunyan Zhang { 213fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 214fb8bd90fSChunyan Zhang u32 div, val, mask; 215fb8bd90fSChunyan Zhang 216fb8bd90fSChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 217fb8bd90fSChunyan Zhang 218fb8bd90fSChunyan Zhang clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 219fb8bd90fSChunyan Zhang sdhci_enable_clk(host, clk); 220fb8bd90fSChunyan Zhang 221fb8bd90fSChunyan Zhang /* enable auto gate sdhc_enable_auto_gate */ 222fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 223fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 224fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 225fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 226fb8bd90fSChunyan Zhang val |= mask; 227fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 228fb8bd90fSChunyan Zhang } 229fb8bd90fSChunyan Zhang } 230fb8bd90fSChunyan Zhang 23187a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 23287a395c2SBaolin Wang { 23387a395c2SBaolin Wang u32 tmp; 23487a395c2SBaolin Wang 23587a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 23687a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 23787a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 23887a395c2SBaolin Wang /* wait 1ms */ 23987a395c2SBaolin Wang usleep_range(1000, 1250); 24087a395c2SBaolin Wang 24187a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24287a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 24387a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 24487a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 24587a395c2SBaolin Wang /* wait 1ms */ 24687a395c2SBaolin Wang usleep_range(1000, 1250); 24787a395c2SBaolin Wang 24887a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24987a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 25087a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 25187a395c2SBaolin Wang /* wait 1ms */ 25287a395c2SBaolin Wang usleep_range(1000, 1250); 25387a395c2SBaolin Wang } 25487a395c2SBaolin Wang 255fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 256fb8bd90fSChunyan Zhang { 25787a395c2SBaolin Wang bool en = false, clk_changed = false; 258fb8bd90fSChunyan Zhang 259fb8bd90fSChunyan Zhang if (clock == 0) { 260fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 261fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 262fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 263fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 264fb8bd90fSChunyan Zhang 265fb8bd90fSChunyan Zhang if (clock <= 400000) 266fb8bd90fSChunyan Zhang en = true; 267fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 268fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 26987a395c2SBaolin Wang clk_changed = true; 270fb8bd90fSChunyan Zhang } else { 271fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 272fb8bd90fSChunyan Zhang } 27387a395c2SBaolin Wang 27487a395c2SBaolin Wang /* 27587a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 27687a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 27787a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 27887a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 27987a395c2SBaolin Wang */ 28087a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 28187a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 282fb8bd90fSChunyan Zhang } 283fb8bd90fSChunyan Zhang 284fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 285fb8bd90fSChunyan Zhang { 286fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 287fb8bd90fSChunyan Zhang 288fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 289fb8bd90fSChunyan Zhang } 290fb8bd90fSChunyan Zhang 291fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 292fb8bd90fSChunyan Zhang { 293fb8bd90fSChunyan Zhang return 400000; 294fb8bd90fSChunyan Zhang } 295fb8bd90fSChunyan Zhang 296fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 297fb8bd90fSChunyan Zhang unsigned int timing) 298fb8bd90fSChunyan Zhang { 2995f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 3005f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc; 3015f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 302fb8bd90fSChunyan Zhang u16 ctrl_2; 303fb8bd90fSChunyan Zhang 304fb8bd90fSChunyan Zhang if (timing == host->timing) 305fb8bd90fSChunyan Zhang return; 306fb8bd90fSChunyan Zhang 307fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 308fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 309fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 310fb8bd90fSChunyan Zhang switch (timing) { 311fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 312fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 313fb8bd90fSChunyan Zhang break; 314fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 315fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 316fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 317fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 318fb8bd90fSChunyan Zhang break; 319fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 320fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 321fb8bd90fSChunyan Zhang break; 322fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 323fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 324fb8bd90fSChunyan Zhang break; 325fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 326fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 327fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 328fb8bd90fSChunyan Zhang break; 329fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 330fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 331fb8bd90fSChunyan Zhang break; 332fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 333fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 334fb8bd90fSChunyan Zhang break; 335fb8bd90fSChunyan Zhang default: 336fb8bd90fSChunyan Zhang break; 337fb8bd90fSChunyan Zhang } 338fb8bd90fSChunyan Zhang 339fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 3405f2f4e0dSBaolin Wang 3415f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe) 3425f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 343fb8bd90fSChunyan Zhang } 344fb8bd90fSChunyan Zhang 345fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 346fb8bd90fSChunyan Zhang { 347fb8bd90fSChunyan Zhang int val; 348fb8bd90fSChunyan Zhang 349fb8bd90fSChunyan Zhang /* 350fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 351fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 352fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 353fb8bd90fSChunyan Zhang * not be cleared. 354fb8bd90fSChunyan Zhang */ 355fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 356fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 357fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 358fb8bd90fSChunyan Zhang /* wait for 10 us */ 359fb8bd90fSChunyan Zhang usleep_range(10, 20); 360fb8bd90fSChunyan Zhang 361fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 362fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 363fb8bd90fSChunyan Zhang usleep_range(300, 500); 364fb8bd90fSChunyan Zhang } 365fb8bd90fSChunyan Zhang 3667486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3677486831dSBaolin Wang { 3687486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 3697486831dSBaolin Wang return 1 << 31; 3707486831dSBaolin Wang } 3717486831dSBaolin Wang 372fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 373fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 374fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 375fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 376fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 377fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 378fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 379fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 380fb8bd90fSChunyan Zhang .reset = sdhci_reset, 381fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 382fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 3837486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 384fb8bd90fSChunyan Zhang }; 385fb8bd90fSChunyan Zhang 386fb8bd90fSChunyan Zhang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 387fb8bd90fSChunyan Zhang { 388fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 389fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 390fb8bd90fSChunyan Zhang 391fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 392fb8bd90fSChunyan Zhang 393fb8bd90fSChunyan Zhang /* 394fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 395fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 396fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 397fb8bd90fSChunyan Zhang */ 398fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 399fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 400fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 401fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 402fb8bd90fSChunyan Zhang 403fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 404fb8bd90fSChunyan Zhang } 405fb8bd90fSChunyan Zhang 406eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 407eef9e0a6SBaolin Wang { 408eef9e0a6SBaolin Wang int ret; 409eef9e0a6SBaolin Wang 410eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) { 411eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios); 412eef9e0a6SBaolin Wang if (ret) { 413eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n", 414eef9e0a6SBaolin Wang mmc_hostname(mmc)); 415eef9e0a6SBaolin Wang return ret; 416eef9e0a6SBaolin Wang } 417eef9e0a6SBaolin Wang } 418eef9e0a6SBaolin Wang 419eef9e0a6SBaolin Wang return 0; 420eef9e0a6SBaolin Wang } 421eef9e0a6SBaolin Wang 422494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 423494c11e1SBaolin Wang struct mmc_ios *ios) 424494c11e1SBaolin Wang { 425494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 4265f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 4275f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 428494c11e1SBaolin Wang u16 ctrl_2; 429494c11e1SBaolin Wang 430494c11e1SBaolin Wang if (!ios->enhanced_strobe) 431494c11e1SBaolin Wang return; 432494c11e1SBaolin Wang 433494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 434494c11e1SBaolin Wang 435494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 436494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 437494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 438494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 439494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 440494c11e1SBaolin Wang 441494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 4425f2f4e0dSBaolin Wang 4435f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 4445f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 4455f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY); 4465f2f4e0dSBaolin Wang } 4475f2f4e0dSBaolin Wang 4485f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 4495f2f4e0dSBaolin Wang struct device_node *np) 4505f2f4e0dSBaolin Wang { 4515f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 4525f2f4e0dSBaolin Wang int ret, i, index; 4535f2f4e0dSBaolin Wang u32 val[4]; 4545f2f4e0dSBaolin Wang 4555f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 4565f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np, 4575f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4); 4585f2f4e0dSBaolin Wang if (ret) 4595f2f4e0dSBaolin Wang continue; 4605f2f4e0dSBaolin Wang 4615f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing; 4625f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 4635f2f4e0dSBaolin Wang } 464494c11e1SBaolin Wang } 465494c11e1SBaolin Wang 466fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 467fb8bd90fSChunyan Zhang .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 468fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 469fb8bd90fSChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 470fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 471fb8bd90fSChunyan Zhang }; 472fb8bd90fSChunyan Zhang 473fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 474fb8bd90fSChunyan Zhang { 475fb8bd90fSChunyan Zhang struct sdhci_host *host; 476fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 477fb8bd90fSChunyan Zhang struct clk *clk; 478fb8bd90fSChunyan Zhang int ret = 0; 479fb8bd90fSChunyan Zhang 480fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 481fb8bd90fSChunyan Zhang if (IS_ERR(host)) 482fb8bd90fSChunyan Zhang return PTR_ERR(host); 483fb8bd90fSChunyan Zhang 484fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 485fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 486fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 487494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 488494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 489eef9e0a6SBaolin Wang /* 490eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage 491eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator 492eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control 493eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage. 494eef9e0a6SBaolin Wang */ 495eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch = 496eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch; 497fb8bd90fSChunyan Zhang 498fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 499fb8bd90fSChunyan Zhang MMC_CAP_ERASE | MMC_CAP_CMD23; 500fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 501fb8bd90fSChunyan Zhang if (ret) 502fb8bd90fSChunyan Zhang goto pltfm_free; 503fb8bd90fSChunyan Zhang 504fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 5055f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 506fb8bd90fSChunyan Zhang 507fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 508fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 509fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 510fb8bd90fSChunyan Zhang goto pltfm_free; 511fb8bd90fSChunyan Zhang } 512fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 513fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 514fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 515fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 516fb8bd90fSChunyan Zhang 517fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 518fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 519fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 520fb8bd90fSChunyan Zhang goto pltfm_free; 521fb8bd90fSChunyan Zhang } 522fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 523fb8bd90fSChunyan Zhang 524ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 525ebd88a38SBaolin Wang if (!IS_ERR(clk)) 526ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 527ebd88a38SBaolin Wang 528fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 529fb8bd90fSChunyan Zhang if (ret) 530fb8bd90fSChunyan Zhang goto pltfm_free; 531fb8bd90fSChunyan Zhang 5321d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 533fb8bd90fSChunyan Zhang if (ret) 534fb8bd90fSChunyan Zhang goto clk_disable; 535fb8bd90fSChunyan Zhang 536ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 537ebd88a38SBaolin Wang if (ret) 538ebd88a38SBaolin Wang goto clk_disable2; 539ebd88a38SBaolin Wang 540fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 541fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 542fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 543fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 544fb8bd90fSChunyan Zhang 545fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 546fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 547fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 548fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 549fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 550fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 551fb8bd90fSChunyan Zhang 552fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 553fb8bd90fSChunyan Zhang 554fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 555fb8bd90fSChunyan Zhang if (ret) 556fb8bd90fSChunyan Zhang goto pm_runtime_disable; 557fb8bd90fSChunyan Zhang 558fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 559fb8bd90fSChunyan Zhang 560fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 561fb8bd90fSChunyan Zhang if (ret) 562fb8bd90fSChunyan Zhang goto err_cleanup_host; 563fb8bd90fSChunyan Zhang 564fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 565fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 566fb8bd90fSChunyan Zhang 567fb8bd90fSChunyan Zhang return 0; 568fb8bd90fSChunyan Zhang 569fb8bd90fSChunyan Zhang err_cleanup_host: 570fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 571fb8bd90fSChunyan Zhang 572fb8bd90fSChunyan Zhang pm_runtime_disable: 573fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 574fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 575fb8bd90fSChunyan Zhang 576ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 577ebd88a38SBaolin Wang 578ebd88a38SBaolin Wang clk_disable2: 579fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 580fb8bd90fSChunyan Zhang 581fb8bd90fSChunyan Zhang clk_disable: 582fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 583fb8bd90fSChunyan Zhang 584fb8bd90fSChunyan Zhang pltfm_free: 585fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 586fb8bd90fSChunyan Zhang return ret; 587fb8bd90fSChunyan Zhang } 588fb8bd90fSChunyan Zhang 589fb8bd90fSChunyan Zhang static int sdhci_sprd_remove(struct platform_device *pdev) 590fb8bd90fSChunyan Zhang { 591fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 592fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 593fb8bd90fSChunyan Zhang struct mmc_host *mmc = host->mmc; 594fb8bd90fSChunyan Zhang 595fb8bd90fSChunyan Zhang mmc_remove_host(mmc); 596fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 597fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 598ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 599fb8bd90fSChunyan Zhang 600fb8bd90fSChunyan Zhang mmc_free_host(mmc); 601fb8bd90fSChunyan Zhang 602fb8bd90fSChunyan Zhang return 0; 603fb8bd90fSChunyan Zhang } 604fb8bd90fSChunyan Zhang 605fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 606fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 607fb8bd90fSChunyan Zhang { } 608fb8bd90fSChunyan Zhang }; 609fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 610fb8bd90fSChunyan Zhang 611fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 612fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 613fb8bd90fSChunyan Zhang { 614fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 615fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 616fb8bd90fSChunyan Zhang 617fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 618fb8bd90fSChunyan Zhang 619fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 620fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 621ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 622fb8bd90fSChunyan Zhang 623fb8bd90fSChunyan Zhang return 0; 624fb8bd90fSChunyan Zhang } 625fb8bd90fSChunyan Zhang 626fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 627fb8bd90fSChunyan Zhang { 628fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 629fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 630fb8bd90fSChunyan Zhang int ret; 631fb8bd90fSChunyan Zhang 632ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 633fb8bd90fSChunyan Zhang if (ret) 634fb8bd90fSChunyan Zhang return ret; 635fb8bd90fSChunyan Zhang 636ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 637ebd88a38SBaolin Wang if (ret) 638ebd88a38SBaolin Wang goto clk_2x_disable; 639ebd88a38SBaolin Wang 640fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 641ebd88a38SBaolin Wang if (ret) 642ebd88a38SBaolin Wang goto clk_disable; 643fb8bd90fSChunyan Zhang 644fb8bd90fSChunyan Zhang sdhci_runtime_resume_host(host); 645fb8bd90fSChunyan Zhang return 0; 646ebd88a38SBaolin Wang 647ebd88a38SBaolin Wang clk_disable: 648ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 649ebd88a38SBaolin Wang 650ebd88a38SBaolin Wang clk_2x_disable: 651ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 652ebd88a38SBaolin Wang 653ebd88a38SBaolin Wang return ret; 654fb8bd90fSChunyan Zhang } 655fb8bd90fSChunyan Zhang #endif 656fb8bd90fSChunyan Zhang 657fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 658fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 659fb8bd90fSChunyan Zhang pm_runtime_force_resume) 660fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 661fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 662fb8bd90fSChunyan Zhang }; 663fb8bd90fSChunyan Zhang 664fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 665fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 666fb8bd90fSChunyan Zhang .remove = sdhci_sprd_remove, 667fb8bd90fSChunyan Zhang .driver = { 668fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 669fb8bd90fSChunyan Zhang .of_match_table = of_match_ptr(sdhci_sprd_of_match), 670fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 671fb8bd90fSChunyan Zhang }, 672fb8bd90fSChunyan Zhang }; 673fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 674fb8bd90fSChunyan Zhang 675fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 676fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 677fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 678