1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 117f00917aSZhenxiong Lai #include <linux/iopoll.h> 12fb8bd90fSChunyan Zhang #include <linux/module.h> 13fb8bd90fSChunyan Zhang #include <linux/of.h> 14fb8bd90fSChunyan Zhang #include <linux/of_device.h> 15fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 1629ca763fSBaolin Wang #include <linux/pinctrl/consumer.h> 17fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 18fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 19fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 20fb8bd90fSChunyan Zhang #include <linux/slab.h> 21fb8bd90fSChunyan Zhang 22fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 23f4498549SBaolin Wang #include "mmc_hsq.h" 24fb8bd90fSChunyan Zhang 25fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 26fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 27fb8bd90fSChunyan Zhang 2887a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 2987a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 3187a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 3287a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3387a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3487a395c2SBaolin Wang 355f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 365f2f4e0dSBaolin Wang 37fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 38fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 39fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 41fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 42fb8bd90fSChunyan Zhang 437f00917aSZhenxiong Lai #define SDHCI_SPRD_REG_32_DLL_STS0 0x210 447f00917aSZhenxiong Lai #define SDHCI_SPRD_DLL_LOCKED BIT(18) 457f00917aSZhenxiong Lai 46fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 47fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 48fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 49fb8bd90fSChunyan Zhang 50fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 51fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 52fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 53fb8bd90fSChunyan Zhang 54fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 55fb8bd90fSChunyan Zhang 56fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 57fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 58fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 59494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 60fb8bd90fSChunyan Zhang 61fb8bd90fSChunyan Zhang /* 62fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 63fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 64fb8bd90fSChunyan Zhang * if this bit is cleared. 65fb8bd90fSChunyan Zhang * 1 : normal work 66fb8bd90fSChunyan Zhang * 0 : hardware reset 67fb8bd90fSChunyan Zhang */ 68fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 69fb8bd90fSChunyan Zhang 70fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 71fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 72fb8bd90fSChunyan Zhang 73fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 7487a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 75fb8bd90fSChunyan Zhang 76fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 77fb8bd90fSChunyan Zhang u32 version; 78fb8bd90fSChunyan Zhang struct clk *clk_sdio; 79fb8bd90fSChunyan Zhang struct clk *clk_enable; 80ebd88a38SBaolin Wang struct clk *clk_2x_enable; 8129ca763fSBaolin Wang struct pinctrl *pinctrl; 8229ca763fSBaolin Wang struct pinctrl_state *pins_uhs; 8329ca763fSBaolin Wang struct pinctrl_state *pins_default; 84fb8bd90fSChunyan Zhang u32 base_rate; 85fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 865f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 875f2f4e0dSBaolin Wang }; 885f2f4e0dSBaolin Wang 895f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg { 905f2f4e0dSBaolin Wang const char *property; 915f2f4e0dSBaolin Wang u8 timing; 925f2f4e0dSBaolin Wang }; 935f2f4e0dSBaolin Wang 945f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 955f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 965f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 975f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 985f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 995f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 1005f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 1015f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 1025f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 1035f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 104fb8bd90fSChunyan Zhang }; 105fb8bd90fSChunyan Zhang 106fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 107fb8bd90fSChunyan Zhang 108fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 109fb8bd90fSChunyan Zhang { 110fb8bd90fSChunyan Zhang u16 val; 111fb8bd90fSChunyan Zhang 112fb8bd90fSChunyan Zhang /* set dll backup mode */ 113fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 114fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 115fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 116fb8bd90fSChunyan Zhang } 117fb8bd90fSChunyan Zhang 118fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 119fb8bd90fSChunyan Zhang { 120fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 121fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 122fb8bd90fSChunyan Zhang 123fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 124fb8bd90fSChunyan Zhang } 125fb8bd90fSChunyan Zhang 126fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 127fb8bd90fSChunyan Zhang { 128fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 129fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 130fb8bd90fSChunyan Zhang return; 131fb8bd90fSChunyan Zhang 132fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 133fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 134fb8bd90fSChunyan Zhang 135fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 136fb8bd90fSChunyan Zhang } 137fb8bd90fSChunyan Zhang 138fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 139fb8bd90fSChunyan Zhang { 140fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 141fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 142fb8bd90fSChunyan Zhang return; 143fb8bd90fSChunyan Zhang 144fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 145fb8bd90fSChunyan Zhang } 146fb8bd90fSChunyan Zhang 147fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 148fb8bd90fSChunyan Zhang { 149fb8bd90fSChunyan Zhang /* 150fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 151fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 152fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 153fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 154fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 155fb8bd90fSChunyan Zhang * around it. 156fb8bd90fSChunyan Zhang */ 157fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 158fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 159fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 160fb8bd90fSChunyan Zhang } 161fb8bd90fSChunyan Zhang 162fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 163fb8bd90fSChunyan Zhang } 164fb8bd90fSChunyan Zhang 165fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 166fb8bd90fSChunyan Zhang { 167fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 168fb8bd90fSChunyan Zhang 169fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 170fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 171fb8bd90fSChunyan Zhang } 172fb8bd90fSChunyan Zhang 173494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 174494c11e1SBaolin Wang { 175494c11e1SBaolin Wang u16 ctrl; 176494c11e1SBaolin Wang 177494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 178494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 179494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 180494c11e1SBaolin Wang } 181494c11e1SBaolin Wang 182fb8bd90fSChunyan Zhang static inline void 183fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 184fb8bd90fSChunyan Zhang { 185fb8bd90fSChunyan Zhang u32 dll_dly_offset; 186fb8bd90fSChunyan Zhang 187fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 188fb8bd90fSChunyan Zhang if (en) 189fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 190fb8bd90fSChunyan Zhang else 191fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 192fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 193fb8bd90fSChunyan Zhang } 194fb8bd90fSChunyan Zhang 195fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 196fb8bd90fSChunyan Zhang { 197fb8bd90fSChunyan Zhang u32 div; 198fb8bd90fSChunyan Zhang 199fb8bd90fSChunyan Zhang /* select 2x clock source */ 200fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 201fb8bd90fSChunyan Zhang return 0; 202fb8bd90fSChunyan Zhang 203fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 204fb8bd90fSChunyan Zhang 205fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 206fb8bd90fSChunyan Zhang div++; 207fb8bd90fSChunyan Zhang 208fb8bd90fSChunyan Zhang if (div % 2) 209fb8bd90fSChunyan Zhang div = (div + 1) / 2; 210fb8bd90fSChunyan Zhang else 211fb8bd90fSChunyan Zhang div = div / 2; 212fb8bd90fSChunyan Zhang 213d252e9b1SWenchao Chen if (div > SDHCI_SPRD_CLK_MAX_DIV) 214d252e9b1SWenchao Chen div = SDHCI_SPRD_CLK_MAX_DIV; 215d252e9b1SWenchao Chen 216fb8bd90fSChunyan Zhang return div; 217fb8bd90fSChunyan Zhang } 218fb8bd90fSChunyan Zhang 219fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 220fb8bd90fSChunyan Zhang unsigned int clk) 221fb8bd90fSChunyan Zhang { 222fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 223fb8bd90fSChunyan Zhang u32 div, val, mask; 224fb8bd90fSChunyan Zhang 225efdaf275SChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 226fb8bd90fSChunyan Zhang 227efdaf275SChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 228efdaf275SChunyan Zhang div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 229efdaf275SChunyan Zhang sdhci_enable_clk(host, div); 230fb8bd90fSChunyan Zhang 231fb8bd90fSChunyan Zhang /* enable auto gate sdhc_enable_auto_gate */ 232fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 233fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 234fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 235fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 236fb8bd90fSChunyan Zhang val |= mask; 237fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 238fb8bd90fSChunyan Zhang } 239fb8bd90fSChunyan Zhang } 240fb8bd90fSChunyan Zhang 24187a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 24287a395c2SBaolin Wang { 24387a395c2SBaolin Wang u32 tmp; 24487a395c2SBaolin Wang 24587a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24687a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 24787a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 24887a395c2SBaolin Wang /* wait 1ms */ 24987a395c2SBaolin Wang usleep_range(1000, 1250); 25087a395c2SBaolin Wang 25187a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 25287a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 25387a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 25487a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 25587a395c2SBaolin Wang /* wait 1ms */ 25687a395c2SBaolin Wang usleep_range(1000, 1250); 25787a395c2SBaolin Wang 25887a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 25987a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 26087a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 26187a395c2SBaolin Wang /* wait 1ms */ 26287a395c2SBaolin Wang usleep_range(1000, 1250); 2637f00917aSZhenxiong Lai 2647f00917aSZhenxiong Lai if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), 2657f00917aSZhenxiong Lai 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) { 2667f00917aSZhenxiong Lai pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc)); 2677f00917aSZhenxiong Lai pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n", 2687f00917aSZhenxiong Lai mmc_hostname(host->mmc), 2697f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), 2707f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); 2717f00917aSZhenxiong Lai } 27287a395c2SBaolin Wang } 27387a395c2SBaolin Wang 274fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 275fb8bd90fSChunyan Zhang { 27687a395c2SBaolin Wang bool en = false, clk_changed = false; 277fb8bd90fSChunyan Zhang 278fb8bd90fSChunyan Zhang if (clock == 0) { 279fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 280fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 281fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 282fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 283fb8bd90fSChunyan Zhang 284fb8bd90fSChunyan Zhang if (clock <= 400000) 285fb8bd90fSChunyan Zhang en = true; 286fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 287fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 28887a395c2SBaolin Wang clk_changed = true; 289fb8bd90fSChunyan Zhang } else { 290fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 291fb8bd90fSChunyan Zhang } 29287a395c2SBaolin Wang 29387a395c2SBaolin Wang /* 29487a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 29587a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 29687a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 29787a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 29887a395c2SBaolin Wang */ 29987a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 30087a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 301fb8bd90fSChunyan Zhang } 302fb8bd90fSChunyan Zhang 303fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 304fb8bd90fSChunyan Zhang { 305fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 306fb8bd90fSChunyan Zhang 307fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 308fb8bd90fSChunyan Zhang } 309fb8bd90fSChunyan Zhang 310fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 311fb8bd90fSChunyan Zhang { 3126e141772SWenchao Chen return 100000; 313fb8bd90fSChunyan Zhang } 314fb8bd90fSChunyan Zhang 315fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 316fb8bd90fSChunyan Zhang unsigned int timing) 317fb8bd90fSChunyan Zhang { 3185f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 3195f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc; 3205f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 321fb8bd90fSChunyan Zhang u16 ctrl_2; 322fb8bd90fSChunyan Zhang 323fb8bd90fSChunyan Zhang if (timing == host->timing) 324fb8bd90fSChunyan Zhang return; 325fb8bd90fSChunyan Zhang 326fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 327fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 328fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 329fb8bd90fSChunyan Zhang switch (timing) { 330fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 331fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 332fb8bd90fSChunyan Zhang break; 333fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 334fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 335fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 336fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 337fb8bd90fSChunyan Zhang break; 338fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 339fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 340fb8bd90fSChunyan Zhang break; 341fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 342fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 343fb8bd90fSChunyan Zhang break; 344fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 345fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 346fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 347fb8bd90fSChunyan Zhang break; 348fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 349fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 350fb8bd90fSChunyan Zhang break; 351fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 352fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 353fb8bd90fSChunyan Zhang break; 354fb8bd90fSChunyan Zhang default: 355fb8bd90fSChunyan Zhang break; 356fb8bd90fSChunyan Zhang } 357fb8bd90fSChunyan Zhang 358fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 3595f2f4e0dSBaolin Wang 3605f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe) 3615f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 362fb8bd90fSChunyan Zhang } 363fb8bd90fSChunyan Zhang 364fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 365fb8bd90fSChunyan Zhang { 366fb8bd90fSChunyan Zhang int val; 367fb8bd90fSChunyan Zhang 368fb8bd90fSChunyan Zhang /* 369fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 370fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 371fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 372fb8bd90fSChunyan Zhang * not be cleared. 373fb8bd90fSChunyan Zhang */ 374fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 375fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 376fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 377fb8bd90fSChunyan Zhang /* wait for 10 us */ 378fb8bd90fSChunyan Zhang usleep_range(10, 20); 379fb8bd90fSChunyan Zhang 380fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 381fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 382fb8bd90fSChunyan Zhang usleep_range(300, 500); 383fb8bd90fSChunyan Zhang } 384fb8bd90fSChunyan Zhang 3857486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3867486831dSBaolin Wang { 3877486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 3887486831dSBaolin Wang return 1 << 31; 3897486831dSBaolin Wang } 3907486831dSBaolin Wang 3914eae8cbdSChunyan Zhang static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 3924eae8cbdSChunyan Zhang { 3934eae8cbdSChunyan Zhang return 0; 3944eae8cbdSChunyan Zhang } 3954eae8cbdSChunyan Zhang 396f4498549SBaolin Wang static void sdhci_sprd_request_done(struct sdhci_host *host, 397f4498549SBaolin Wang struct mmc_request *mrq) 398f4498549SBaolin Wang { 399f4498549SBaolin Wang /* Validate if the request was from software queue firstly. */ 400f4498549SBaolin Wang if (mmc_hsq_finalize_request(host->mmc, mrq)) 401f4498549SBaolin Wang return; 402f4498549SBaolin Wang 403f4498549SBaolin Wang mmc_request_done(host->mmc, mrq); 404f4498549SBaolin Wang } 405f4498549SBaolin Wang 406fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 407fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 408fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 40996147082SKrzysztof Kozlowski .write_w = sdhci_sprd_writew, 410fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 411fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 412fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 413fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 414fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 415fb8bd90fSChunyan Zhang .reset = sdhci_reset, 416fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 417fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 4187486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 4194eae8cbdSChunyan Zhang .get_ro = sdhci_sprd_get_ro, 420f4498549SBaolin Wang .request_done = sdhci_sprd_request_done, 421fb8bd90fSChunyan Zhang }; 422fb8bd90fSChunyan Zhang 42361ab64e2SBaolin Wang static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 42461ab64e2SBaolin Wang struct mmc_request *mrq) 425fb8bd90fSChunyan Zhang { 426fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 427fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 428fb8bd90fSChunyan Zhang 429fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 430fb8bd90fSChunyan Zhang 431fb8bd90fSChunyan Zhang /* 432fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 433fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 434fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 435fb8bd90fSChunyan Zhang */ 436fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 437fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 438fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 439fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 44061ab64e2SBaolin Wang } 44161ab64e2SBaolin Wang 44261ab64e2SBaolin Wang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 44361ab64e2SBaolin Wang { 44461ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 445fb8bd90fSChunyan Zhang 446fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 447fb8bd90fSChunyan Zhang } 448fb8bd90fSChunyan Zhang 44961ab64e2SBaolin Wang static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 45061ab64e2SBaolin Wang struct mmc_request *mrq) 45161ab64e2SBaolin Wang { 45261ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 45361ab64e2SBaolin Wang 45461ab64e2SBaolin Wang return sdhci_request_atomic(mmc, mrq); 45561ab64e2SBaolin Wang } 45661ab64e2SBaolin Wang 457eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 458eef9e0a6SBaolin Wang { 45929ca763fSBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 46029ca763fSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 461eef9e0a6SBaolin Wang int ret; 462eef9e0a6SBaolin Wang 463eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) { 464eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios); 4659cbe0fc8SMarek Vasut if (ret < 0) { 466eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n", 467eef9e0a6SBaolin Wang mmc_hostname(mmc)); 468eef9e0a6SBaolin Wang return ret; 469eef9e0a6SBaolin Wang } 470eef9e0a6SBaolin Wang } 471eef9e0a6SBaolin Wang 47229ca763fSBaolin Wang if (IS_ERR(sprd_host->pinctrl)) 473*dd30dcfaSWenchao Chen goto reset; 47429ca763fSBaolin Wang 47529ca763fSBaolin Wang switch (ios->signal_voltage) { 47629ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_180: 47729ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 47829ca763fSBaolin Wang sprd_host->pins_uhs); 47929ca763fSBaolin Wang if (ret) { 48029ca763fSBaolin Wang pr_err("%s: failed to select uhs pin state\n", 48129ca763fSBaolin Wang mmc_hostname(mmc)); 48229ca763fSBaolin Wang return ret; 48329ca763fSBaolin Wang } 48429ca763fSBaolin Wang break; 48529ca763fSBaolin Wang 48629ca763fSBaolin Wang default: 487df561f66SGustavo A. R. Silva fallthrough; 48829ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_330: 48929ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 49029ca763fSBaolin Wang sprd_host->pins_default); 49129ca763fSBaolin Wang if (ret) { 49229ca763fSBaolin Wang pr_err("%s: failed to select default pin state\n", 49329ca763fSBaolin Wang mmc_hostname(mmc)); 49429ca763fSBaolin Wang return ret; 49529ca763fSBaolin Wang } 49629ca763fSBaolin Wang break; 49729ca763fSBaolin Wang } 49829ca763fSBaolin Wang 49929ca763fSBaolin Wang /* Wait for 300 ~ 500 us for pin state stable */ 50029ca763fSBaolin Wang usleep_range(300, 500); 501*dd30dcfaSWenchao Chen 502*dd30dcfaSWenchao Chen reset: 50329ca763fSBaolin Wang sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 50429ca763fSBaolin Wang 505eef9e0a6SBaolin Wang return 0; 506eef9e0a6SBaolin Wang } 507eef9e0a6SBaolin Wang 508494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 509494c11e1SBaolin Wang struct mmc_ios *ios) 510494c11e1SBaolin Wang { 511494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 5125f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 5135f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 514494c11e1SBaolin Wang u16 ctrl_2; 515494c11e1SBaolin Wang 516494c11e1SBaolin Wang if (!ios->enhanced_strobe) 517494c11e1SBaolin Wang return; 518494c11e1SBaolin Wang 519494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 520494c11e1SBaolin Wang 521494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 522494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 523494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 524494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 525494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 526494c11e1SBaolin Wang 527494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 5285f2f4e0dSBaolin Wang 5295f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 5305f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 5315f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY); 5325f2f4e0dSBaolin Wang } 5335f2f4e0dSBaolin Wang 5345f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 5355f2f4e0dSBaolin Wang struct device_node *np) 5365f2f4e0dSBaolin Wang { 5375f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 5385f2f4e0dSBaolin Wang int ret, i, index; 5395f2f4e0dSBaolin Wang u32 val[4]; 5405f2f4e0dSBaolin Wang 5415f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 5425f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np, 5435f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4); 5445f2f4e0dSBaolin Wang if (ret) 5455f2f4e0dSBaolin Wang continue; 5465f2f4e0dSBaolin Wang 5475f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing; 5485f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 5495f2f4e0dSBaolin Wang } 550494c11e1SBaolin Wang } 551494c11e1SBaolin Wang 552fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 5534324e54bSChunyan Zhang .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 5542f765c17SChunyan Zhang SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 5552f765c17SChunyan Zhang SDHCI_QUIRK_MISSING_CAPS, 556fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 5576a526f66SChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 5586a526f66SChunyan Zhang SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 559fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 560fb8bd90fSChunyan Zhang }; 561fb8bd90fSChunyan Zhang 562fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 563fb8bd90fSChunyan Zhang { 564fb8bd90fSChunyan Zhang struct sdhci_host *host; 565fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 566f4498549SBaolin Wang struct mmc_hsq *hsq; 567fb8bd90fSChunyan Zhang struct clk *clk; 568fb8bd90fSChunyan Zhang int ret = 0; 569fb8bd90fSChunyan Zhang 570fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 571fb8bd90fSChunyan Zhang if (IS_ERR(host)) 572fb8bd90fSChunyan Zhang return PTR_ERR(host); 573fb8bd90fSChunyan Zhang 574fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 575fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 576fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 577494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 578494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 579eef9e0a6SBaolin Wang /* 580eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage 581eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator 582eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control 583eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage. 584eef9e0a6SBaolin Wang */ 585eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch = 586eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch; 587fb8bd90fSChunyan Zhang 588fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 589a049b5aeSUlf Hansson MMC_CAP_WAIT_WHILE_BUSY; 590a049b5aeSUlf Hansson 591fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 592fb8bd90fSChunyan Zhang if (ret) 593fb8bd90fSChunyan Zhang goto pltfm_free; 594fb8bd90fSChunyan Zhang 59561ab64e2SBaolin Wang if (!mmc_card_is_removable(host->mmc)) 59661ab64e2SBaolin Wang host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 59761ab64e2SBaolin Wang else 59861ab64e2SBaolin Wang host->always_defer_done = true; 59961ab64e2SBaolin Wang 600fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 6015f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 602fb8bd90fSChunyan Zhang 60329ca763fSBaolin Wang sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 60429ca763fSBaolin Wang if (!IS_ERR(sprd_host->pinctrl)) { 60529ca763fSBaolin Wang sprd_host->pins_uhs = 60629ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 60729ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_uhs)) { 60829ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_uhs); 60929ca763fSBaolin Wang goto pltfm_free; 61029ca763fSBaolin Wang } 61129ca763fSBaolin Wang 61229ca763fSBaolin Wang sprd_host->pins_default = 61329ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "default"); 61429ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_default)) { 61529ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_default); 61629ca763fSBaolin Wang goto pltfm_free; 61729ca763fSBaolin Wang } 61829ca763fSBaolin Wang } 61929ca763fSBaolin Wang 620fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 621fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 622fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 623fb8bd90fSChunyan Zhang goto pltfm_free; 624fb8bd90fSChunyan Zhang } 625fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 626fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 627fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 628fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 629fb8bd90fSChunyan Zhang 630fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 631fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 632fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 633fb8bd90fSChunyan Zhang goto pltfm_free; 634fb8bd90fSChunyan Zhang } 635fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 636fb8bd90fSChunyan Zhang 637ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 638ebd88a38SBaolin Wang if (!IS_ERR(clk)) 639ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 640ebd88a38SBaolin Wang 641fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 642fb8bd90fSChunyan Zhang if (ret) 643fb8bd90fSChunyan Zhang goto pltfm_free; 644fb8bd90fSChunyan Zhang 6451d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 646fb8bd90fSChunyan Zhang if (ret) 647fb8bd90fSChunyan Zhang goto clk_disable; 648fb8bd90fSChunyan Zhang 649ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 650ebd88a38SBaolin Wang if (ret) 651ebd88a38SBaolin Wang goto clk_disable2; 652ebd88a38SBaolin Wang 653fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 654fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 655fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 656fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 657fb8bd90fSChunyan Zhang 658fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 659fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 660fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 661fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 662fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 663fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 664fb8bd90fSChunyan Zhang 665fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 666fb8bd90fSChunyan Zhang 6672f765c17SChunyan Zhang /* 6682f765c17SChunyan Zhang * Supply the existing CAPS, but clear the UHS-I modes. This 6692f765c17SChunyan Zhang * will allow these modes to be specified only by device 6702f765c17SChunyan Zhang * tree properties through mmc_of_parse(). 6712f765c17SChunyan Zhang */ 6722f765c17SChunyan Zhang host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 6732f765c17SChunyan Zhang host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 6742f765c17SChunyan Zhang host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 6752f765c17SChunyan Zhang SDHCI_SUPPORT_DDR50); 6762f765c17SChunyan Zhang 677fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 678fb8bd90fSChunyan Zhang if (ret) 679fb8bd90fSChunyan Zhang goto pm_runtime_disable; 680fb8bd90fSChunyan Zhang 681fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 682fb8bd90fSChunyan Zhang 683f4498549SBaolin Wang hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 684f4498549SBaolin Wang if (!hsq) { 685f4498549SBaolin Wang ret = -ENOMEM; 686f4498549SBaolin Wang goto err_cleanup_host; 687f4498549SBaolin Wang } 688f4498549SBaolin Wang 689f4498549SBaolin Wang ret = mmc_hsq_init(hsq, host->mmc); 690f4498549SBaolin Wang if (ret) 691f4498549SBaolin Wang goto err_cleanup_host; 692f4498549SBaolin Wang 693fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 694fb8bd90fSChunyan Zhang if (ret) 695fb8bd90fSChunyan Zhang goto err_cleanup_host; 696fb8bd90fSChunyan Zhang 697fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 698fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 699fb8bd90fSChunyan Zhang 700fb8bd90fSChunyan Zhang return 0; 701fb8bd90fSChunyan Zhang 702fb8bd90fSChunyan Zhang err_cleanup_host: 703fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 704fb8bd90fSChunyan Zhang 705fb8bd90fSChunyan Zhang pm_runtime_disable: 706fc62113bSBaolin Wang pm_runtime_put_noidle(&pdev->dev); 707fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 708fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 709fb8bd90fSChunyan Zhang 710ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 711ebd88a38SBaolin Wang 712ebd88a38SBaolin Wang clk_disable2: 713fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 714fb8bd90fSChunyan Zhang 715fb8bd90fSChunyan Zhang clk_disable: 716fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 717fb8bd90fSChunyan Zhang 718fb8bd90fSChunyan Zhang pltfm_free: 719fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 720fb8bd90fSChunyan Zhang return ret; 721fb8bd90fSChunyan Zhang } 722fb8bd90fSChunyan Zhang 723fb8bd90fSChunyan Zhang static int sdhci_sprd_remove(struct platform_device *pdev) 724fb8bd90fSChunyan Zhang { 725fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 726fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 727fb8bd90fSChunyan Zhang 728c9c256a8SChristophe JAILLET sdhci_remove_host(host, 0); 729c9c256a8SChristophe JAILLET 730fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 731fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 732ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 733fb8bd90fSChunyan Zhang 734c9c256a8SChristophe JAILLET sdhci_pltfm_free(pdev); 735fb8bd90fSChunyan Zhang 736fb8bd90fSChunyan Zhang return 0; 737fb8bd90fSChunyan Zhang } 738fb8bd90fSChunyan Zhang 739fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 740fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 741fb8bd90fSChunyan Zhang { } 742fb8bd90fSChunyan Zhang }; 743fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 744fb8bd90fSChunyan Zhang 745fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 746fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 747fb8bd90fSChunyan Zhang { 748fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 749fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 750fb8bd90fSChunyan Zhang 751f4498549SBaolin Wang mmc_hsq_suspend(host->mmc); 752fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 753fb8bd90fSChunyan Zhang 754fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 755fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 756ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 757fb8bd90fSChunyan Zhang 758fb8bd90fSChunyan Zhang return 0; 759fb8bd90fSChunyan Zhang } 760fb8bd90fSChunyan Zhang 761fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 762fb8bd90fSChunyan Zhang { 763fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 764fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 765fb8bd90fSChunyan Zhang int ret; 766fb8bd90fSChunyan Zhang 767ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 768fb8bd90fSChunyan Zhang if (ret) 769fb8bd90fSChunyan Zhang return ret; 770fb8bd90fSChunyan Zhang 771ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 772ebd88a38SBaolin Wang if (ret) 773ebd88a38SBaolin Wang goto clk_2x_disable; 774ebd88a38SBaolin Wang 775fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 776ebd88a38SBaolin Wang if (ret) 777ebd88a38SBaolin Wang goto clk_disable; 778fb8bd90fSChunyan Zhang 779c6303c5dSBaolin Wang sdhci_runtime_resume_host(host, 1); 780f4498549SBaolin Wang mmc_hsq_resume(host->mmc); 781f4498549SBaolin Wang 782fb8bd90fSChunyan Zhang return 0; 783ebd88a38SBaolin Wang 784ebd88a38SBaolin Wang clk_disable: 785ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 786ebd88a38SBaolin Wang 787ebd88a38SBaolin Wang clk_2x_disable: 788ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 789ebd88a38SBaolin Wang 790ebd88a38SBaolin Wang return ret; 791fb8bd90fSChunyan Zhang } 792fb8bd90fSChunyan Zhang #endif 793fb8bd90fSChunyan Zhang 794fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 795fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 796fb8bd90fSChunyan Zhang pm_runtime_force_resume) 797fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 798fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 799fb8bd90fSChunyan Zhang }; 800fb8bd90fSChunyan Zhang 801fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 802fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 803fb8bd90fSChunyan Zhang .remove = sdhci_sprd_remove, 804fb8bd90fSChunyan Zhang .driver = { 805fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 806d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 807a96e6523SKrzysztof Kozlowski .of_match_table = sdhci_sprd_of_match, 808fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 809fb8bd90fSChunyan Zhang }, 810fb8bd90fSChunyan Zhang }; 811fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 812fb8bd90fSChunyan Zhang 813fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 814fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 815fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 816