1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 117f00917aSZhenxiong Lai #include <linux/iopoll.h> 12*d83d251bSWenchao Chen #include <linux/mmc/host.h> 13*d83d251bSWenchao Chen #include <linux/mmc/mmc.h> 14fb8bd90fSChunyan Zhang #include <linux/module.h> 15fb8bd90fSChunyan Zhang #include <linux/of.h> 16fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 1729ca763fSBaolin Wang #include <linux/pinctrl/consumer.h> 18fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 19fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 20fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 21fb8bd90fSChunyan Zhang #include <linux/slab.h> 22fb8bd90fSChunyan Zhang 23fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 24f4498549SBaolin Wang #include "mmc_hsq.h" 25fb8bd90fSChunyan Zhang 26fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 27fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 28fb8bd90fSChunyan Zhang 2987a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 3187a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 3287a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 3387a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3487a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3587a395c2SBaolin Wang 365f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 375f2f4e0dSBaolin Wang 38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 39fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 41fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 43fb8bd90fSChunyan Zhang 447f00917aSZhenxiong Lai #define SDHCI_SPRD_REG_32_DLL_STS0 0x210 457f00917aSZhenxiong Lai #define SDHCI_SPRD_DLL_LOCKED BIT(18) 467f00917aSZhenxiong Lai 47fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 48fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 49fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 50fb8bd90fSChunyan Zhang 51fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 52fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 53fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 54fb8bd90fSChunyan Zhang 55fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 56fb8bd90fSChunyan Zhang 57fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 58fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 59fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 60494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 61fb8bd90fSChunyan Zhang 62fb8bd90fSChunyan Zhang /* 63fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 64fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 65fb8bd90fSChunyan Zhang * if this bit is cleared. 66fb8bd90fSChunyan Zhang * 1 : normal work 67fb8bd90fSChunyan Zhang * 0 : hardware reset 68fb8bd90fSChunyan Zhang */ 69fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 70fb8bd90fSChunyan Zhang 71fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 72fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 73fb8bd90fSChunyan Zhang 74fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 7587a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 76fb8bd90fSChunyan Zhang 77*d83d251bSWenchao Chen #define SDHCI_SPRD_MAX_RANGE 0xff 78*d83d251bSWenchao Chen #define SDHCI_SPRD_CMD_DLY_MASK GENMASK(15, 8) 79*d83d251bSWenchao Chen #define SDHCI_SPRD_POSRD_DLY_MASK GENMASK(23, 16) 80*d83d251bSWenchao Chen #define SDHCI_SPRD_CPST_EN GENMASK(27, 24) 81*d83d251bSWenchao Chen 82fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 83fb8bd90fSChunyan Zhang u32 version; 84fb8bd90fSChunyan Zhang struct clk *clk_sdio; 85fb8bd90fSChunyan Zhang struct clk *clk_enable; 86ebd88a38SBaolin Wang struct clk *clk_2x_enable; 8729ca763fSBaolin Wang struct pinctrl *pinctrl; 8829ca763fSBaolin Wang struct pinctrl_state *pins_uhs; 8929ca763fSBaolin Wang struct pinctrl_state *pins_default; 90fb8bd90fSChunyan Zhang u32 base_rate; 91fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 925f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 935f2f4e0dSBaolin Wang }; 945f2f4e0dSBaolin Wang 95*d83d251bSWenchao Chen enum sdhci_sprd_tuning_type { 96*d83d251bSWenchao Chen SDHCI_SPRD_TUNING_SD_HS_CMD, 97*d83d251bSWenchao Chen SDHCI_SPRD_TUNING_SD_HS_DATA, 98*d83d251bSWenchao Chen }; 99*d83d251bSWenchao Chen 1005f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg { 1015f2f4e0dSBaolin Wang const char *property; 1025f2f4e0dSBaolin Wang u8 timing; 1035f2f4e0dSBaolin Wang }; 1045f2f4e0dSBaolin Wang 1055f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 1065f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 1075f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 1085f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 1095f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 1105f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 1115f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 1125f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 1135f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 1145f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 115fb8bd90fSChunyan Zhang }; 116fb8bd90fSChunyan Zhang 117fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 118fb8bd90fSChunyan Zhang 119fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 120fb8bd90fSChunyan Zhang { 121fb8bd90fSChunyan Zhang u16 val; 122fb8bd90fSChunyan Zhang 123fb8bd90fSChunyan Zhang /* set dll backup mode */ 124fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 125fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 126fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 127fb8bd90fSChunyan Zhang } 128fb8bd90fSChunyan Zhang 129fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 130fb8bd90fSChunyan Zhang { 131fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 132fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 133fb8bd90fSChunyan Zhang 134fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 135fb8bd90fSChunyan Zhang } 136fb8bd90fSChunyan Zhang 137fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 138fb8bd90fSChunyan Zhang { 139fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 140fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 141fb8bd90fSChunyan Zhang return; 142fb8bd90fSChunyan Zhang 143fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 144fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 145fb8bd90fSChunyan Zhang 146fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 147fb8bd90fSChunyan Zhang } 148fb8bd90fSChunyan Zhang 149fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 150fb8bd90fSChunyan Zhang { 151fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 152fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 153fb8bd90fSChunyan Zhang return; 154fb8bd90fSChunyan Zhang 155fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 156fb8bd90fSChunyan Zhang } 157fb8bd90fSChunyan Zhang 158fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 159fb8bd90fSChunyan Zhang { 160fb8bd90fSChunyan Zhang /* 161fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 162fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 163fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 164fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 165fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 166fb8bd90fSChunyan Zhang * around it. 167fb8bd90fSChunyan Zhang */ 168fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 169fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 170fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 171fb8bd90fSChunyan Zhang } 172fb8bd90fSChunyan Zhang 173fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 174fb8bd90fSChunyan Zhang } 175fb8bd90fSChunyan Zhang 176fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 177fb8bd90fSChunyan Zhang { 178fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 179fb8bd90fSChunyan Zhang 180fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 181fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 182fb8bd90fSChunyan Zhang } 183fb8bd90fSChunyan Zhang 184494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 185494c11e1SBaolin Wang { 186494c11e1SBaolin Wang u16 ctrl; 187494c11e1SBaolin Wang 188494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 189494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 190494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 191494c11e1SBaolin Wang } 192494c11e1SBaolin Wang 193fb8bd90fSChunyan Zhang static inline void 194fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 195fb8bd90fSChunyan Zhang { 196fb8bd90fSChunyan Zhang u32 dll_dly_offset; 197fb8bd90fSChunyan Zhang 198fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 199fb8bd90fSChunyan Zhang if (en) 200fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 201fb8bd90fSChunyan Zhang else 202fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 203fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 204fb8bd90fSChunyan Zhang } 205fb8bd90fSChunyan Zhang 206fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 207fb8bd90fSChunyan Zhang { 208fb8bd90fSChunyan Zhang u32 div; 209fb8bd90fSChunyan Zhang 210fb8bd90fSChunyan Zhang /* select 2x clock source */ 211fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 212fb8bd90fSChunyan Zhang return 0; 213fb8bd90fSChunyan Zhang 214fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 215fb8bd90fSChunyan Zhang 216fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 217fb8bd90fSChunyan Zhang div++; 218fb8bd90fSChunyan Zhang 219fb8bd90fSChunyan Zhang if (div % 2) 220fb8bd90fSChunyan Zhang div = (div + 1) / 2; 221fb8bd90fSChunyan Zhang else 222fb8bd90fSChunyan Zhang div = div / 2; 223fb8bd90fSChunyan Zhang 224d252e9b1SWenchao Chen if (div > SDHCI_SPRD_CLK_MAX_DIV) 225d252e9b1SWenchao Chen div = SDHCI_SPRD_CLK_MAX_DIV; 226d252e9b1SWenchao Chen 227fb8bd90fSChunyan Zhang return div; 228fb8bd90fSChunyan Zhang } 229fb8bd90fSChunyan Zhang 230fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 231fb8bd90fSChunyan Zhang unsigned int clk) 232fb8bd90fSChunyan Zhang { 233fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 234fb8bd90fSChunyan Zhang u32 div, val, mask; 235fb8bd90fSChunyan Zhang 236efdaf275SChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 237fb8bd90fSChunyan Zhang 238efdaf275SChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 239efdaf275SChunyan Zhang div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 240efdaf275SChunyan Zhang sdhci_enable_clk(host, div); 241fb8bd90fSChunyan Zhang 242ff874dbcSWenchao Chen /* Enable CLK_AUTO when the clock is greater than 400K. */ 243ff874dbcSWenchao Chen if (clk > 400000) { 244fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 245fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 246fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 247fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 248fb8bd90fSChunyan Zhang val |= mask; 249fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 250fb8bd90fSChunyan Zhang } 251fb8bd90fSChunyan Zhang } 252ff874dbcSWenchao Chen } 253fb8bd90fSChunyan Zhang 25487a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 25587a395c2SBaolin Wang { 25687a395c2SBaolin Wang u32 tmp; 25787a395c2SBaolin Wang 25887a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 25987a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 26087a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 26187a395c2SBaolin Wang /* wait 1ms */ 26287a395c2SBaolin Wang usleep_range(1000, 1250); 26387a395c2SBaolin Wang 26487a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 26587a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 26687a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 26787a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 26887a395c2SBaolin Wang /* wait 1ms */ 26987a395c2SBaolin Wang usleep_range(1000, 1250); 27087a395c2SBaolin Wang 27187a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 27287a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 27387a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 27487a395c2SBaolin Wang /* wait 1ms */ 27587a395c2SBaolin Wang usleep_range(1000, 1250); 2767f00917aSZhenxiong Lai 2777f00917aSZhenxiong Lai if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), 2787f00917aSZhenxiong Lai 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) { 2797f00917aSZhenxiong Lai pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc)); 2807f00917aSZhenxiong Lai pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n", 2817f00917aSZhenxiong Lai mmc_hostname(host->mmc), 2827f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), 2837f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); 2847f00917aSZhenxiong Lai } 28587a395c2SBaolin Wang } 28687a395c2SBaolin Wang 287fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 288fb8bd90fSChunyan Zhang { 28987a395c2SBaolin Wang bool en = false, clk_changed = false; 290fb8bd90fSChunyan Zhang 291fb8bd90fSChunyan Zhang if (clock == 0) { 292fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 293fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 294fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 295fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 296fb8bd90fSChunyan Zhang 297fb8bd90fSChunyan Zhang if (clock <= 400000) 298fb8bd90fSChunyan Zhang en = true; 299fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 300fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 30187a395c2SBaolin Wang clk_changed = true; 302fb8bd90fSChunyan Zhang } else { 303fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 304fb8bd90fSChunyan Zhang } 30587a395c2SBaolin Wang 30687a395c2SBaolin Wang /* 30787a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 30887a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 30987a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 31087a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 31187a395c2SBaolin Wang */ 31287a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 31387a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 314fb8bd90fSChunyan Zhang } 315fb8bd90fSChunyan Zhang 316fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 317fb8bd90fSChunyan Zhang { 318fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 319fb8bd90fSChunyan Zhang 320fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 321fb8bd90fSChunyan Zhang } 322fb8bd90fSChunyan Zhang 323fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 324fb8bd90fSChunyan Zhang { 3256e141772SWenchao Chen return 100000; 326fb8bd90fSChunyan Zhang } 327fb8bd90fSChunyan Zhang 328fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 329fb8bd90fSChunyan Zhang unsigned int timing) 330fb8bd90fSChunyan Zhang { 3315f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 3325f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc; 3335f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 334fb8bd90fSChunyan Zhang u16 ctrl_2; 335fb8bd90fSChunyan Zhang 336fb8bd90fSChunyan Zhang if (timing == host->timing) 337fb8bd90fSChunyan Zhang return; 338fb8bd90fSChunyan Zhang 339fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 340fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 341fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 342fb8bd90fSChunyan Zhang switch (timing) { 343fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 344fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 345fb8bd90fSChunyan Zhang break; 346fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 347fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 348fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 349fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 350fb8bd90fSChunyan Zhang break; 351fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 352fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 353fb8bd90fSChunyan Zhang break; 354fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 355fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 356fb8bd90fSChunyan Zhang break; 357fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 358fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 359fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 360fb8bd90fSChunyan Zhang break; 361fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 362fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 363fb8bd90fSChunyan Zhang break; 364fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 365fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 366fb8bd90fSChunyan Zhang break; 367fb8bd90fSChunyan Zhang default: 368fb8bd90fSChunyan Zhang break; 369fb8bd90fSChunyan Zhang } 370fb8bd90fSChunyan Zhang 371fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 3725f2f4e0dSBaolin Wang 3735f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe) 3745f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 375fb8bd90fSChunyan Zhang } 376fb8bd90fSChunyan Zhang 377fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 378fb8bd90fSChunyan Zhang { 379fb8bd90fSChunyan Zhang int val; 380fb8bd90fSChunyan Zhang 381fb8bd90fSChunyan Zhang /* 382fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 383fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 384fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 385fb8bd90fSChunyan Zhang * not be cleared. 386fb8bd90fSChunyan Zhang */ 387fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 388fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 389fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 390fb8bd90fSChunyan Zhang /* wait for 10 us */ 391fb8bd90fSChunyan Zhang usleep_range(10, 20); 392fb8bd90fSChunyan Zhang 393fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 394fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 395fb8bd90fSChunyan Zhang usleep_range(300, 500); 396fb8bd90fSChunyan Zhang } 397fb8bd90fSChunyan Zhang 3987486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3997486831dSBaolin Wang { 4007486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 4017486831dSBaolin Wang return 1 << 31; 4027486831dSBaolin Wang } 4037486831dSBaolin Wang 4044eae8cbdSChunyan Zhang static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 4054eae8cbdSChunyan Zhang { 4064eae8cbdSChunyan Zhang return 0; 4074eae8cbdSChunyan Zhang } 4084eae8cbdSChunyan Zhang 409f4498549SBaolin Wang static void sdhci_sprd_request_done(struct sdhci_host *host, 410f4498549SBaolin Wang struct mmc_request *mrq) 411f4498549SBaolin Wang { 412f4498549SBaolin Wang /* Validate if the request was from software queue firstly. */ 413f4498549SBaolin Wang if (mmc_hsq_finalize_request(host->mmc, mrq)) 414f4498549SBaolin Wang return; 415f4498549SBaolin Wang 416f4498549SBaolin Wang mmc_request_done(host->mmc, mrq); 417f4498549SBaolin Wang } 418f4498549SBaolin Wang 419fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 420fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 421fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 42296147082SKrzysztof Kozlowski .write_w = sdhci_sprd_writew, 423fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 424fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 425fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 426fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 427fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 428fb8bd90fSChunyan Zhang .reset = sdhci_reset, 429fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 430fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 4317486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 4324eae8cbdSChunyan Zhang .get_ro = sdhci_sprd_get_ro, 433f4498549SBaolin Wang .request_done = sdhci_sprd_request_done, 434fb8bd90fSChunyan Zhang }; 435fb8bd90fSChunyan Zhang 43661ab64e2SBaolin Wang static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 43761ab64e2SBaolin Wang struct mmc_request *mrq) 438fb8bd90fSChunyan Zhang { 439fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 440fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 441fb8bd90fSChunyan Zhang 442fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 443fb8bd90fSChunyan Zhang 444fb8bd90fSChunyan Zhang /* 445fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 446fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 447fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 448fb8bd90fSChunyan Zhang */ 449fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 450fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 451fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 452fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 45361ab64e2SBaolin Wang } 45461ab64e2SBaolin Wang 45561ab64e2SBaolin Wang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 45661ab64e2SBaolin Wang { 45761ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 458fb8bd90fSChunyan Zhang 459fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 460fb8bd90fSChunyan Zhang } 461fb8bd90fSChunyan Zhang 46261ab64e2SBaolin Wang static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 46361ab64e2SBaolin Wang struct mmc_request *mrq) 46461ab64e2SBaolin Wang { 46561ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 46661ab64e2SBaolin Wang 46761ab64e2SBaolin Wang return sdhci_request_atomic(mmc, mrq); 46861ab64e2SBaolin Wang } 46961ab64e2SBaolin Wang 470eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 471eef9e0a6SBaolin Wang { 47229ca763fSBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 47329ca763fSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 474eef9e0a6SBaolin Wang int ret; 475eef9e0a6SBaolin Wang 476eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) { 477eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios); 4789cbe0fc8SMarek Vasut if (ret < 0) { 479eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n", 480eef9e0a6SBaolin Wang mmc_hostname(mmc)); 481eef9e0a6SBaolin Wang return ret; 482eef9e0a6SBaolin Wang } 483eef9e0a6SBaolin Wang } 484eef9e0a6SBaolin Wang 48529ca763fSBaolin Wang if (IS_ERR(sprd_host->pinctrl)) 486dd30dcfaSWenchao Chen goto reset; 48729ca763fSBaolin Wang 48829ca763fSBaolin Wang switch (ios->signal_voltage) { 48929ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_180: 49029ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 49129ca763fSBaolin Wang sprd_host->pins_uhs); 49229ca763fSBaolin Wang if (ret) { 49329ca763fSBaolin Wang pr_err("%s: failed to select uhs pin state\n", 49429ca763fSBaolin Wang mmc_hostname(mmc)); 49529ca763fSBaolin Wang return ret; 49629ca763fSBaolin Wang } 49729ca763fSBaolin Wang break; 49829ca763fSBaolin Wang 49929ca763fSBaolin Wang default: 500df561f66SGustavo A. R. Silva fallthrough; 50129ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_330: 50229ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 50329ca763fSBaolin Wang sprd_host->pins_default); 50429ca763fSBaolin Wang if (ret) { 50529ca763fSBaolin Wang pr_err("%s: failed to select default pin state\n", 50629ca763fSBaolin Wang mmc_hostname(mmc)); 50729ca763fSBaolin Wang return ret; 50829ca763fSBaolin Wang } 50929ca763fSBaolin Wang break; 51029ca763fSBaolin Wang } 51129ca763fSBaolin Wang 51229ca763fSBaolin Wang /* Wait for 300 ~ 500 us for pin state stable */ 51329ca763fSBaolin Wang usleep_range(300, 500); 514dd30dcfaSWenchao Chen 515dd30dcfaSWenchao Chen reset: 51629ca763fSBaolin Wang sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 51729ca763fSBaolin Wang 518eef9e0a6SBaolin Wang return 0; 519eef9e0a6SBaolin Wang } 520eef9e0a6SBaolin Wang 521494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 522494c11e1SBaolin Wang struct mmc_ios *ios) 523494c11e1SBaolin Wang { 524494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 5255f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 5265f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 527494c11e1SBaolin Wang u16 ctrl_2; 528494c11e1SBaolin Wang 529494c11e1SBaolin Wang if (!ios->enhanced_strobe) 530494c11e1SBaolin Wang return; 531494c11e1SBaolin Wang 532494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 533494c11e1SBaolin Wang 534494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 535494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 536494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 537494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 538494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 539494c11e1SBaolin Wang 540494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 5415f2f4e0dSBaolin Wang 5425f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 5435f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 5445f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY); 5455f2f4e0dSBaolin Wang } 5465f2f4e0dSBaolin Wang 547*d83d251bSWenchao Chen static int mmc_send_tuning_cmd(struct mmc_card *card) 548*d83d251bSWenchao Chen { 549*d83d251bSWenchao Chen return mmc_send_status(card, NULL); 550*d83d251bSWenchao Chen } 551*d83d251bSWenchao Chen 552*d83d251bSWenchao Chen static int mmc_send_tuning_data(struct mmc_card *card) 553*d83d251bSWenchao Chen { 554*d83d251bSWenchao Chen u8 *status; 555*d83d251bSWenchao Chen int ret; 556*d83d251bSWenchao Chen 557*d83d251bSWenchao Chen status = kmalloc(64, GFP_KERNEL); 558*d83d251bSWenchao Chen if (!status) 559*d83d251bSWenchao Chen return -ENOMEM; 560*d83d251bSWenchao Chen 561*d83d251bSWenchao Chen ret = mmc_sd_switch(card, 0, 0, 0, status); 562*d83d251bSWenchao Chen 563*d83d251bSWenchao Chen kfree(status); 564*d83d251bSWenchao Chen 565*d83d251bSWenchao Chen return ret; 566*d83d251bSWenchao Chen } 567*d83d251bSWenchao Chen 568*d83d251bSWenchao Chen static int sdhci_sprd_get_best_clk_sample(struct mmc_host *mmc, u8 *value) 569*d83d251bSWenchao Chen { 570*d83d251bSWenchao Chen int range_end = SDHCI_SPRD_MAX_RANGE; 571*d83d251bSWenchao Chen int range_length = 0; 572*d83d251bSWenchao Chen int middle_range = 0; 573*d83d251bSWenchao Chen int count = 0; 574*d83d251bSWenchao Chen int i; 575*d83d251bSWenchao Chen 576*d83d251bSWenchao Chen for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) { 577*d83d251bSWenchao Chen if (value[i]) { 578*d83d251bSWenchao Chen pr_debug("%s: tuning ok: %d\n", mmc_hostname(mmc), i); 579*d83d251bSWenchao Chen count++; 580*d83d251bSWenchao Chen } else { 581*d83d251bSWenchao Chen pr_debug("%s: tuning fail: %d\n", mmc_hostname(mmc), i); 582*d83d251bSWenchao Chen if (range_length < count) { 583*d83d251bSWenchao Chen range_length = count; 584*d83d251bSWenchao Chen range_end = i - 1; 585*d83d251bSWenchao Chen count = 0; 586*d83d251bSWenchao Chen } 587*d83d251bSWenchao Chen } 588*d83d251bSWenchao Chen } 589*d83d251bSWenchao Chen 590*d83d251bSWenchao Chen if (!count) 591*d83d251bSWenchao Chen return -EIO; 592*d83d251bSWenchao Chen 593*d83d251bSWenchao Chen if (count > range_length) { 594*d83d251bSWenchao Chen range_length = count; 595*d83d251bSWenchao Chen range_end = i - 1; 596*d83d251bSWenchao Chen } 597*d83d251bSWenchao Chen 598*d83d251bSWenchao Chen middle_range = range_end - (range_length - 1) / 2; 599*d83d251bSWenchao Chen 600*d83d251bSWenchao Chen return middle_range; 601*d83d251bSWenchao Chen } 602*d83d251bSWenchao Chen 603*d83d251bSWenchao Chen static int sdhci_sprd_tuning(struct mmc_host *mmc, struct mmc_card *card, 604*d83d251bSWenchao Chen enum sdhci_sprd_tuning_type type) 605*d83d251bSWenchao Chen { 606*d83d251bSWenchao Chen struct sdhci_host *host = mmc_priv(mmc); 607*d83d251bSWenchao Chen struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 608*d83d251bSWenchao Chen u32 *p = sprd_host->phy_delay; 609*d83d251bSWenchao Chen u32 dll_cfg, dll_dly; 610*d83d251bSWenchao Chen int best_clk_sample; 611*d83d251bSWenchao Chen int err = 0; 612*d83d251bSWenchao Chen u8 *value; 613*d83d251bSWenchao Chen int i; 614*d83d251bSWenchao Chen 615*d83d251bSWenchao Chen value = kmalloc(SDHCI_SPRD_MAX_RANGE + 1, GFP_KERNEL); 616*d83d251bSWenchao Chen if (!value) 617*d83d251bSWenchao Chen return -ENOMEM; 618*d83d251bSWenchao Chen 619*d83d251bSWenchao Chen sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 620*d83d251bSWenchao Chen 621*d83d251bSWenchao Chen dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 622*d83d251bSWenchao Chen dll_cfg &= ~SDHCI_SPRD_CPST_EN; 623*d83d251bSWenchao Chen sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG); 624*d83d251bSWenchao Chen 625*d83d251bSWenchao Chen dll_dly = p[mmc->ios.timing]; 626*d83d251bSWenchao Chen 627*d83d251bSWenchao Chen for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) { 628*d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) { 629*d83d251bSWenchao Chen dll_dly &= ~SDHCI_SPRD_CMD_DLY_MASK; 630*d83d251bSWenchao Chen dll_dly |= ((i << 8) & SDHCI_SPRD_CMD_DLY_MASK); 631*d83d251bSWenchao Chen } else { 632*d83d251bSWenchao Chen dll_dly &= ~SDHCI_SPRD_POSRD_DLY_MASK; 633*d83d251bSWenchao Chen dll_dly |= ((i << 16) & SDHCI_SPRD_POSRD_DLY_MASK); 634*d83d251bSWenchao Chen } 635*d83d251bSWenchao Chen 636*d83d251bSWenchao Chen sdhci_writel(host, dll_dly, SDHCI_SPRD_REG_32_DLL_DLY); 637*d83d251bSWenchao Chen 638*d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) 639*d83d251bSWenchao Chen value[i] = !mmc_send_tuning_cmd(card); 640*d83d251bSWenchao Chen else 641*d83d251bSWenchao Chen value[i] = !mmc_send_tuning_data(card); 642*d83d251bSWenchao Chen } 643*d83d251bSWenchao Chen 644*d83d251bSWenchao Chen best_clk_sample = sdhci_sprd_get_best_clk_sample(mmc, value); 645*d83d251bSWenchao Chen if (best_clk_sample < 0) { 646*d83d251bSWenchao Chen dev_err(mmc_dev(host->mmc), "all tuning phase fail!\n"); 647*d83d251bSWenchao Chen goto out; 648*d83d251bSWenchao Chen } 649*d83d251bSWenchao Chen 650*d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) { 651*d83d251bSWenchao Chen p[mmc->ios.timing] &= ~SDHCI_SPRD_CMD_DLY_MASK; 652*d83d251bSWenchao Chen p[mmc->ios.timing] |= ((best_clk_sample << 8) & SDHCI_SPRD_CMD_DLY_MASK); 653*d83d251bSWenchao Chen } else { 654*d83d251bSWenchao Chen p[mmc->ios.timing] &= ~(SDHCI_SPRD_POSRD_DLY_MASK); 655*d83d251bSWenchao Chen p[mmc->ios.timing] |= ((best_clk_sample << 16) & SDHCI_SPRD_POSRD_DLY_MASK); 656*d83d251bSWenchao Chen } 657*d83d251bSWenchao Chen 658*d83d251bSWenchao Chen pr_debug("%s: the best clk sample %d, delay value 0x%08x\n", 659*d83d251bSWenchao Chen mmc_hostname(host->mmc), best_clk_sample, p[mmc->ios.timing]); 660*d83d251bSWenchao Chen 661*d83d251bSWenchao Chen out: 662*d83d251bSWenchao Chen sdhci_writel(host, p[mmc->ios.timing], SDHCI_SPRD_REG_32_DLL_DLY); 663*d83d251bSWenchao Chen 664*d83d251bSWenchao Chen kfree(value); 665*d83d251bSWenchao Chen 666*d83d251bSWenchao Chen return err; 667*d83d251bSWenchao Chen } 668*d83d251bSWenchao Chen 669*d83d251bSWenchao Chen static int sdhci_sprd_prepare_sd_hs_cmd_tuning(struct mmc_host *mmc, struct mmc_card *card) 670*d83d251bSWenchao Chen { 671*d83d251bSWenchao Chen return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_CMD); 672*d83d251bSWenchao Chen } 673*d83d251bSWenchao Chen 674*d83d251bSWenchao Chen static int sdhci_sprd_execute_sd_hs_data_tuning(struct mmc_host *mmc, struct mmc_card *card) 675*d83d251bSWenchao Chen { 676*d83d251bSWenchao Chen return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_DATA); 677*d83d251bSWenchao Chen } 678*d83d251bSWenchao Chen 6795f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 6805f2f4e0dSBaolin Wang struct device_node *np) 6815f2f4e0dSBaolin Wang { 6825f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 6835f2f4e0dSBaolin Wang int ret, i, index; 6845f2f4e0dSBaolin Wang u32 val[4]; 6855f2f4e0dSBaolin Wang 6865f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 6875f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np, 6885f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4); 6895f2f4e0dSBaolin Wang if (ret) 6905f2f4e0dSBaolin Wang continue; 6915f2f4e0dSBaolin Wang 6925f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing; 6935f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 6945f2f4e0dSBaolin Wang } 695494c11e1SBaolin Wang } 696494c11e1SBaolin Wang 697fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 6984324e54bSChunyan Zhang .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 699924ea310SAdrian Hunter SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 700fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 7016a526f66SChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 7026a526f66SChunyan Zhang SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 703fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 704fb8bd90fSChunyan Zhang }; 705fb8bd90fSChunyan Zhang 706fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 707fb8bd90fSChunyan Zhang { 708fb8bd90fSChunyan Zhang struct sdhci_host *host; 709fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 710f4498549SBaolin Wang struct mmc_hsq *hsq; 711fb8bd90fSChunyan Zhang struct clk *clk; 712fb8bd90fSChunyan Zhang int ret = 0; 713fb8bd90fSChunyan Zhang 714fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 715fb8bd90fSChunyan Zhang if (IS_ERR(host)) 716fb8bd90fSChunyan Zhang return PTR_ERR(host); 717fb8bd90fSChunyan Zhang 718fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 719fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 720fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 721494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 722494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 723*d83d251bSWenchao Chen host->mmc_host_ops.prepare_sd_hs_tuning = 724*d83d251bSWenchao Chen sdhci_sprd_prepare_sd_hs_cmd_tuning; 725*d83d251bSWenchao Chen host->mmc_host_ops.execute_sd_hs_tuning = 726*d83d251bSWenchao Chen sdhci_sprd_execute_sd_hs_data_tuning; 727*d83d251bSWenchao Chen 728eef9e0a6SBaolin Wang /* 729eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage 730eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator 731eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control 732eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage. 733eef9e0a6SBaolin Wang */ 734eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch = 735eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch; 736fb8bd90fSChunyan Zhang 737fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 738a049b5aeSUlf Hansson MMC_CAP_WAIT_WHILE_BUSY; 739a049b5aeSUlf Hansson 740fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 741fb8bd90fSChunyan Zhang if (ret) 742fb8bd90fSChunyan Zhang goto pltfm_free; 743fb8bd90fSChunyan Zhang 74461ab64e2SBaolin Wang if (!mmc_card_is_removable(host->mmc)) 74561ab64e2SBaolin Wang host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 74661ab64e2SBaolin Wang else 74761ab64e2SBaolin Wang host->always_defer_done = true; 74861ab64e2SBaolin Wang 749fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 7505f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 751fb8bd90fSChunyan Zhang 75229ca763fSBaolin Wang sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 75329ca763fSBaolin Wang if (!IS_ERR(sprd_host->pinctrl)) { 75429ca763fSBaolin Wang sprd_host->pins_uhs = 75529ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 75629ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_uhs)) { 75729ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_uhs); 75829ca763fSBaolin Wang goto pltfm_free; 75929ca763fSBaolin Wang } 76029ca763fSBaolin Wang 76129ca763fSBaolin Wang sprd_host->pins_default = 76229ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "default"); 76329ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_default)) { 76429ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_default); 76529ca763fSBaolin Wang goto pltfm_free; 76629ca763fSBaolin Wang } 76729ca763fSBaolin Wang } 76829ca763fSBaolin Wang 769fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 770fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 771fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 772fb8bd90fSChunyan Zhang goto pltfm_free; 773fb8bd90fSChunyan Zhang } 774fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 775fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 776fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 777fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 778fb8bd90fSChunyan Zhang 779fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 780fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 781fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 782fb8bd90fSChunyan Zhang goto pltfm_free; 783fb8bd90fSChunyan Zhang } 784fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 785fb8bd90fSChunyan Zhang 786ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 787ebd88a38SBaolin Wang if (!IS_ERR(clk)) 788ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 789ebd88a38SBaolin Wang 790fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 791fb8bd90fSChunyan Zhang if (ret) 792fb8bd90fSChunyan Zhang goto pltfm_free; 793fb8bd90fSChunyan Zhang 7941d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 795fb8bd90fSChunyan Zhang if (ret) 796fb8bd90fSChunyan Zhang goto clk_disable; 797fb8bd90fSChunyan Zhang 798ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 799ebd88a38SBaolin Wang if (ret) 800ebd88a38SBaolin Wang goto clk_disable2; 801ebd88a38SBaolin Wang 802fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 803fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 804fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 805fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 806fb8bd90fSChunyan Zhang 807fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 808fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 809fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 810fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 811fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 812fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 813fb8bd90fSChunyan Zhang 814fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 815fb8bd90fSChunyan Zhang 8162f765c17SChunyan Zhang /* 8172f765c17SChunyan Zhang * Supply the existing CAPS, but clear the UHS-I modes. This 8182f765c17SChunyan Zhang * will allow these modes to be specified only by device 8192f765c17SChunyan Zhang * tree properties through mmc_of_parse(). 8202f765c17SChunyan Zhang */ 821924ea310SAdrian Hunter sdhci_read_caps(host); 8222f765c17SChunyan Zhang host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 8232f765c17SChunyan Zhang SDHCI_SUPPORT_DDR50); 8242f765c17SChunyan Zhang 825fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 826fb8bd90fSChunyan Zhang if (ret) 827fb8bd90fSChunyan Zhang goto pm_runtime_disable; 828fb8bd90fSChunyan Zhang 829fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 830fb8bd90fSChunyan Zhang 831f4498549SBaolin Wang hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 832f4498549SBaolin Wang if (!hsq) { 833f4498549SBaolin Wang ret = -ENOMEM; 834f4498549SBaolin Wang goto err_cleanup_host; 835f4498549SBaolin Wang } 836f4498549SBaolin Wang 837f4498549SBaolin Wang ret = mmc_hsq_init(hsq, host->mmc); 838f4498549SBaolin Wang if (ret) 839f4498549SBaolin Wang goto err_cleanup_host; 840f4498549SBaolin Wang 841fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 842fb8bd90fSChunyan Zhang if (ret) 843fb8bd90fSChunyan Zhang goto err_cleanup_host; 844fb8bd90fSChunyan Zhang 845fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 846fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 847fb8bd90fSChunyan Zhang 848fb8bd90fSChunyan Zhang return 0; 849fb8bd90fSChunyan Zhang 850fb8bd90fSChunyan Zhang err_cleanup_host: 851fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 852fb8bd90fSChunyan Zhang 853fb8bd90fSChunyan Zhang pm_runtime_disable: 854fc62113bSBaolin Wang pm_runtime_put_noidle(&pdev->dev); 855fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 856fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 857fb8bd90fSChunyan Zhang 858ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 859ebd88a38SBaolin Wang 860ebd88a38SBaolin Wang clk_disable2: 861fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 862fb8bd90fSChunyan Zhang 863fb8bd90fSChunyan Zhang clk_disable: 864fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 865fb8bd90fSChunyan Zhang 866fb8bd90fSChunyan Zhang pltfm_free: 867fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 868fb8bd90fSChunyan Zhang return ret; 869fb8bd90fSChunyan Zhang } 870fb8bd90fSChunyan Zhang 871c618ba0fSYangtao Li static void sdhci_sprd_remove(struct platform_device *pdev) 872fb8bd90fSChunyan Zhang { 873fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 874fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 875fb8bd90fSChunyan Zhang 876c9c256a8SChristophe JAILLET sdhci_remove_host(host, 0); 877c9c256a8SChristophe JAILLET 878fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 879fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 880ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 881fb8bd90fSChunyan Zhang 882c9c256a8SChristophe JAILLET sdhci_pltfm_free(pdev); 883fb8bd90fSChunyan Zhang } 884fb8bd90fSChunyan Zhang 885fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 886fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 887fb8bd90fSChunyan Zhang { } 888fb8bd90fSChunyan Zhang }; 889fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 890fb8bd90fSChunyan Zhang 891fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 892fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 893fb8bd90fSChunyan Zhang { 894fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 895fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 896fb8bd90fSChunyan Zhang 897f4498549SBaolin Wang mmc_hsq_suspend(host->mmc); 898fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 899fb8bd90fSChunyan Zhang 900fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 901fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 902ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 903fb8bd90fSChunyan Zhang 904fb8bd90fSChunyan Zhang return 0; 905fb8bd90fSChunyan Zhang } 906fb8bd90fSChunyan Zhang 907fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 908fb8bd90fSChunyan Zhang { 909fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 910fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 911fb8bd90fSChunyan Zhang int ret; 912fb8bd90fSChunyan Zhang 913ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 914fb8bd90fSChunyan Zhang if (ret) 915fb8bd90fSChunyan Zhang return ret; 916fb8bd90fSChunyan Zhang 917ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 918ebd88a38SBaolin Wang if (ret) 919ebd88a38SBaolin Wang goto clk_2x_disable; 920ebd88a38SBaolin Wang 921fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 922ebd88a38SBaolin Wang if (ret) 923ebd88a38SBaolin Wang goto clk_disable; 924fb8bd90fSChunyan Zhang 925c6303c5dSBaolin Wang sdhci_runtime_resume_host(host, 1); 926f4498549SBaolin Wang mmc_hsq_resume(host->mmc); 927f4498549SBaolin Wang 928fb8bd90fSChunyan Zhang return 0; 929ebd88a38SBaolin Wang 930ebd88a38SBaolin Wang clk_disable: 931ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 932ebd88a38SBaolin Wang 933ebd88a38SBaolin Wang clk_2x_disable: 934ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 935ebd88a38SBaolin Wang 936ebd88a38SBaolin Wang return ret; 937fb8bd90fSChunyan Zhang } 938fb8bd90fSChunyan Zhang #endif 939fb8bd90fSChunyan Zhang 940fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 941fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 942fb8bd90fSChunyan Zhang pm_runtime_force_resume) 943fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 944fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 945fb8bd90fSChunyan Zhang }; 946fb8bd90fSChunyan Zhang 947fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 948fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 949c618ba0fSYangtao Li .remove_new = sdhci_sprd_remove, 950fb8bd90fSChunyan Zhang .driver = { 951fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 952d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 953a96e6523SKrzysztof Kozlowski .of_match_table = sdhci_sprd_of_match, 954fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 955fb8bd90fSChunyan Zhang }, 956fb8bd90fSChunyan Zhang }; 957fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 958fb8bd90fSChunyan Zhang 959fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 960fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 961fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 962