1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 117f00917aSZhenxiong Lai #include <linux/iopoll.h> 12d83d251bSWenchao Chen #include <linux/mmc/host.h> 13d83d251bSWenchao Chen #include <linux/mmc/mmc.h> 14fb8bd90fSChunyan Zhang #include <linux/module.h> 15fb8bd90fSChunyan Zhang #include <linux/of.h> 16fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 1729ca763fSBaolin Wang #include <linux/pinctrl/consumer.h> 18fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 19fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 20fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 21fb8bd90fSChunyan Zhang #include <linux/slab.h> 22fb8bd90fSChunyan Zhang 23fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 24f4498549SBaolin Wang #include "mmc_hsq.h" 25fb8bd90fSChunyan Zhang 26fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 27fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 28fb8bd90fSChunyan Zhang 2987a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 3187a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 3287a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 3387a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3487a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3587a395c2SBaolin Wang 365f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 375f2f4e0dSBaolin Wang 38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 39fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 41fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 43fb8bd90fSChunyan Zhang 447f00917aSZhenxiong Lai #define SDHCI_SPRD_REG_32_DLL_STS0 0x210 457f00917aSZhenxiong Lai #define SDHCI_SPRD_DLL_LOCKED BIT(18) 467f00917aSZhenxiong Lai 47fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 48fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 49fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 50fb8bd90fSChunyan Zhang 51fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 52fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 53fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 54fb8bd90fSChunyan Zhang 55fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 56fb8bd90fSChunyan Zhang 57fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 58fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 59fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 60494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 61fb8bd90fSChunyan Zhang 62fb8bd90fSChunyan Zhang /* 63fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 64fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 65fb8bd90fSChunyan Zhang * if this bit is cleared. 66fb8bd90fSChunyan Zhang * 1 : normal work 67fb8bd90fSChunyan Zhang * 0 : hardware reset 68fb8bd90fSChunyan Zhang */ 69fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 70fb8bd90fSChunyan Zhang 71fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 72fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 73fb8bd90fSChunyan Zhang 74fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 7587a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 76fb8bd90fSChunyan Zhang 77d83d251bSWenchao Chen #define SDHCI_SPRD_MAX_RANGE 0xff 78d83d251bSWenchao Chen #define SDHCI_SPRD_CMD_DLY_MASK GENMASK(15, 8) 79d83d251bSWenchao Chen #define SDHCI_SPRD_POSRD_DLY_MASK GENMASK(23, 16) 80d83d251bSWenchao Chen #define SDHCI_SPRD_CPST_EN GENMASK(27, 24) 81d83d251bSWenchao Chen 82fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 83fb8bd90fSChunyan Zhang u32 version; 84fb8bd90fSChunyan Zhang struct clk *clk_sdio; 85fb8bd90fSChunyan Zhang struct clk *clk_enable; 86ebd88a38SBaolin Wang struct clk *clk_2x_enable; 8729ca763fSBaolin Wang struct pinctrl *pinctrl; 8829ca763fSBaolin Wang struct pinctrl_state *pins_uhs; 8929ca763fSBaolin Wang struct pinctrl_state *pins_default; 90fb8bd90fSChunyan Zhang u32 base_rate; 91fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 925f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 935f2f4e0dSBaolin Wang }; 945f2f4e0dSBaolin Wang 95d83d251bSWenchao Chen enum sdhci_sprd_tuning_type { 96d83d251bSWenchao Chen SDHCI_SPRD_TUNING_SD_HS_CMD, 97d83d251bSWenchao Chen SDHCI_SPRD_TUNING_SD_HS_DATA, 98d83d251bSWenchao Chen }; 99d83d251bSWenchao Chen 1005f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg { 1015f2f4e0dSBaolin Wang const char *property; 1025f2f4e0dSBaolin Wang u8 timing; 1035f2f4e0dSBaolin Wang }; 1045f2f4e0dSBaolin Wang 1055f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 1065f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 1075f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 1085f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 1095f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 1105f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 1115f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 1125f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 1135f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 1145f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 115fb8bd90fSChunyan Zhang }; 116fb8bd90fSChunyan Zhang 117fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 118fb8bd90fSChunyan Zhang 119fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 120fb8bd90fSChunyan Zhang { 121fb8bd90fSChunyan Zhang u16 val; 122fb8bd90fSChunyan Zhang 123fb8bd90fSChunyan Zhang /* set dll backup mode */ 124fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 125fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 126fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 127fb8bd90fSChunyan Zhang } 128fb8bd90fSChunyan Zhang 129fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 130fb8bd90fSChunyan Zhang { 131fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 132fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 133fb8bd90fSChunyan Zhang 134fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 135fb8bd90fSChunyan Zhang } 136fb8bd90fSChunyan Zhang 137fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 138fb8bd90fSChunyan Zhang { 139fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 140fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 141fb8bd90fSChunyan Zhang return; 142fb8bd90fSChunyan Zhang 143fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 144fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 145fb8bd90fSChunyan Zhang 146fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 147fb8bd90fSChunyan Zhang } 148fb8bd90fSChunyan Zhang 149fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 150fb8bd90fSChunyan Zhang { 151fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 152fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 153fb8bd90fSChunyan Zhang return; 154fb8bd90fSChunyan Zhang 155fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 156fb8bd90fSChunyan Zhang } 157fb8bd90fSChunyan Zhang 158fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 159fb8bd90fSChunyan Zhang { 160fb8bd90fSChunyan Zhang /* 161fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 162fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 163fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 164fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 165fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 166fb8bd90fSChunyan Zhang * around it. 167fb8bd90fSChunyan Zhang */ 168fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 169fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 170fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 171fb8bd90fSChunyan Zhang } 172fb8bd90fSChunyan Zhang 173fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 174fb8bd90fSChunyan Zhang } 175fb8bd90fSChunyan Zhang 176fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 177fb8bd90fSChunyan Zhang { 178fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 179fb8bd90fSChunyan Zhang 180fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 181fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 182fb8bd90fSChunyan Zhang } 183fb8bd90fSChunyan Zhang 184494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 185494c11e1SBaolin Wang { 186494c11e1SBaolin Wang u16 ctrl; 187494c11e1SBaolin Wang 188494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 189494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 190494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 191494c11e1SBaolin Wang } 192494c11e1SBaolin Wang 193fb8bd90fSChunyan Zhang static inline void 194fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 195fb8bd90fSChunyan Zhang { 196fb8bd90fSChunyan Zhang u32 dll_dly_offset; 197fb8bd90fSChunyan Zhang 198fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 199fb8bd90fSChunyan Zhang if (en) 200fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 201fb8bd90fSChunyan Zhang else 202fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 203fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 204fb8bd90fSChunyan Zhang } 205fb8bd90fSChunyan Zhang 206fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 207fb8bd90fSChunyan Zhang { 208fb8bd90fSChunyan Zhang u32 div; 209fb8bd90fSChunyan Zhang 210fb8bd90fSChunyan Zhang /* select 2x clock source */ 211fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 212fb8bd90fSChunyan Zhang return 0; 213fb8bd90fSChunyan Zhang 214fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 215fb8bd90fSChunyan Zhang 216fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 217fb8bd90fSChunyan Zhang div++; 218fb8bd90fSChunyan Zhang 219fb8bd90fSChunyan Zhang if (div % 2) 220fb8bd90fSChunyan Zhang div = (div + 1) / 2; 221fb8bd90fSChunyan Zhang else 222fb8bd90fSChunyan Zhang div = div / 2; 223fb8bd90fSChunyan Zhang 224d252e9b1SWenchao Chen if (div > SDHCI_SPRD_CLK_MAX_DIV) 225d252e9b1SWenchao Chen div = SDHCI_SPRD_CLK_MAX_DIV; 226d252e9b1SWenchao Chen 227fb8bd90fSChunyan Zhang return div; 228fb8bd90fSChunyan Zhang } 229fb8bd90fSChunyan Zhang 230fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 231fb8bd90fSChunyan Zhang unsigned int clk) 232fb8bd90fSChunyan Zhang { 233fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 234fb8bd90fSChunyan Zhang u32 div, val, mask; 235fb8bd90fSChunyan Zhang 236efdaf275SChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 237fb8bd90fSChunyan Zhang 238efdaf275SChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 239efdaf275SChunyan Zhang div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 240efdaf275SChunyan Zhang sdhci_enable_clk(host, div); 241fb8bd90fSChunyan Zhang 242ff874dbcSWenchao Chen /* Enable CLK_AUTO when the clock is greater than 400K. */ 243ff874dbcSWenchao Chen if (clk > 400000) { 244fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 245fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 246fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 247fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 248fb8bd90fSChunyan Zhang val |= mask; 249fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 250fb8bd90fSChunyan Zhang } 251fb8bd90fSChunyan Zhang } 252ff874dbcSWenchao Chen } 253fb8bd90fSChunyan Zhang 25487a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 25587a395c2SBaolin Wang { 25687a395c2SBaolin Wang u32 tmp; 25787a395c2SBaolin Wang 25887a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 25987a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 26087a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 26187a395c2SBaolin Wang /* wait 1ms */ 26287a395c2SBaolin Wang usleep_range(1000, 1250); 26387a395c2SBaolin Wang 26487a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 26587a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 26687a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 26787a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 26887a395c2SBaolin Wang /* wait 1ms */ 26987a395c2SBaolin Wang usleep_range(1000, 1250); 27087a395c2SBaolin Wang 27187a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 27287a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 27387a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 27487a395c2SBaolin Wang /* wait 1ms */ 27587a395c2SBaolin Wang usleep_range(1000, 1250); 2767f00917aSZhenxiong Lai 2777f00917aSZhenxiong Lai if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), 2787f00917aSZhenxiong Lai 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) { 2797f00917aSZhenxiong Lai pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc)); 2807f00917aSZhenxiong Lai pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n", 2817f00917aSZhenxiong Lai mmc_hostname(host->mmc), 2827f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), 2837f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); 2847f00917aSZhenxiong Lai } 28587a395c2SBaolin Wang } 28687a395c2SBaolin Wang 287fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 288fb8bd90fSChunyan Zhang { 28987a395c2SBaolin Wang bool en = false, clk_changed = false; 290fb8bd90fSChunyan Zhang 291fb8bd90fSChunyan Zhang if (clock == 0) { 292fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 293fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 294fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 295fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 296fb8bd90fSChunyan Zhang 297fb8bd90fSChunyan Zhang if (clock <= 400000) 298fb8bd90fSChunyan Zhang en = true; 299fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 300fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 30187a395c2SBaolin Wang clk_changed = true; 302fb8bd90fSChunyan Zhang } else { 303fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 304fb8bd90fSChunyan Zhang } 30587a395c2SBaolin Wang 30687a395c2SBaolin Wang /* 30787a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 30887a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 30987a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 31087a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 31187a395c2SBaolin Wang */ 31287a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 31387a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 314fb8bd90fSChunyan Zhang } 315fb8bd90fSChunyan Zhang 316fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 317fb8bd90fSChunyan Zhang { 318fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 319fb8bd90fSChunyan Zhang 320fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 321fb8bd90fSChunyan Zhang } 322fb8bd90fSChunyan Zhang 323fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 324fb8bd90fSChunyan Zhang { 3256e141772SWenchao Chen return 100000; 326fb8bd90fSChunyan Zhang } 327fb8bd90fSChunyan Zhang 328fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 329fb8bd90fSChunyan Zhang unsigned int timing) 330fb8bd90fSChunyan Zhang { 3315f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 3325f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc; 3335f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 334fb8bd90fSChunyan Zhang u16 ctrl_2; 335fb8bd90fSChunyan Zhang 336fb8bd90fSChunyan Zhang if (timing == host->timing) 337fb8bd90fSChunyan Zhang return; 338fb8bd90fSChunyan Zhang 339fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 340fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 341fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 342fb8bd90fSChunyan Zhang switch (timing) { 343fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 344fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 345fb8bd90fSChunyan Zhang break; 346fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 347fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 348fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 349fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 350fb8bd90fSChunyan Zhang break; 351fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 352fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 353fb8bd90fSChunyan Zhang break; 354fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 355fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 356fb8bd90fSChunyan Zhang break; 357fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 358fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 359fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 360fb8bd90fSChunyan Zhang break; 361fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 362fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 363fb8bd90fSChunyan Zhang break; 364fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 365fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 366fb8bd90fSChunyan Zhang break; 367fb8bd90fSChunyan Zhang default: 368fb8bd90fSChunyan Zhang break; 369fb8bd90fSChunyan Zhang } 370fb8bd90fSChunyan Zhang 371fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 3725f2f4e0dSBaolin Wang 3735f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe) 3745f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 375fb8bd90fSChunyan Zhang } 376fb8bd90fSChunyan Zhang 377fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 378fb8bd90fSChunyan Zhang { 379fb8bd90fSChunyan Zhang int val; 380fb8bd90fSChunyan Zhang 381fb8bd90fSChunyan Zhang /* 382fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 383fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 384fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 385fb8bd90fSChunyan Zhang * not be cleared. 386fb8bd90fSChunyan Zhang */ 387fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 388fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 389fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 390fb8bd90fSChunyan Zhang /* wait for 10 us */ 391fb8bd90fSChunyan Zhang usleep_range(10, 20); 392fb8bd90fSChunyan Zhang 393fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 394fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 395fb8bd90fSChunyan Zhang usleep_range(300, 500); 396fb8bd90fSChunyan Zhang } 397fb8bd90fSChunyan Zhang 3987486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3997486831dSBaolin Wang { 4007486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 4017486831dSBaolin Wang return 1 << 31; 4027486831dSBaolin Wang } 4037486831dSBaolin Wang 4044eae8cbdSChunyan Zhang static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 4054eae8cbdSChunyan Zhang { 4064eae8cbdSChunyan Zhang return 0; 4074eae8cbdSChunyan Zhang } 4084eae8cbdSChunyan Zhang 409f4498549SBaolin Wang static void sdhci_sprd_request_done(struct sdhci_host *host, 410f4498549SBaolin Wang struct mmc_request *mrq) 411f4498549SBaolin Wang { 412f4498549SBaolin Wang /* Validate if the request was from software queue firstly. */ 413f4498549SBaolin Wang if (mmc_hsq_finalize_request(host->mmc, mrq)) 414f4498549SBaolin Wang return; 415f4498549SBaolin Wang 416f4498549SBaolin Wang mmc_request_done(host->mmc, mrq); 417f4498549SBaolin Wang } 418f4498549SBaolin Wang 419*cb42d0dcSWenchao Chen static void sdhci_sprd_set_power(struct sdhci_host *host, unsigned char mode, 420*cb42d0dcSWenchao Chen unsigned short vdd) 421*cb42d0dcSWenchao Chen { 422*cb42d0dcSWenchao Chen struct mmc_host *mmc = host->mmc; 423*cb42d0dcSWenchao Chen 424*cb42d0dcSWenchao Chen switch (mode) { 425*cb42d0dcSWenchao Chen case MMC_POWER_OFF: 426*cb42d0dcSWenchao Chen mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, 0); 427*cb42d0dcSWenchao Chen 428*cb42d0dcSWenchao Chen mmc_regulator_disable_vqmmc(mmc); 429*cb42d0dcSWenchao Chen break; 430*cb42d0dcSWenchao Chen case MMC_POWER_ON: 431*cb42d0dcSWenchao Chen mmc_regulator_enable_vqmmc(mmc); 432*cb42d0dcSWenchao Chen break; 433*cb42d0dcSWenchao Chen case MMC_POWER_UP: 434*cb42d0dcSWenchao Chen mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, vdd); 435*cb42d0dcSWenchao Chen break; 436*cb42d0dcSWenchao Chen } 437*cb42d0dcSWenchao Chen } 438*cb42d0dcSWenchao Chen 439fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 440fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 441fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 44296147082SKrzysztof Kozlowski .write_w = sdhci_sprd_writew, 443fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 444fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 445*cb42d0dcSWenchao Chen .set_power = sdhci_sprd_set_power, 446fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 447fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 448fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 449fb8bd90fSChunyan Zhang .reset = sdhci_reset, 450fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 451fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 4527486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 4534eae8cbdSChunyan Zhang .get_ro = sdhci_sprd_get_ro, 454f4498549SBaolin Wang .request_done = sdhci_sprd_request_done, 455fb8bd90fSChunyan Zhang }; 456fb8bd90fSChunyan Zhang 45761ab64e2SBaolin Wang static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 45861ab64e2SBaolin Wang struct mmc_request *mrq) 459fb8bd90fSChunyan Zhang { 460fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 461fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 462fb8bd90fSChunyan Zhang 463fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 464fb8bd90fSChunyan Zhang 465fb8bd90fSChunyan Zhang /* 466fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 467fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 468fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 469fb8bd90fSChunyan Zhang */ 470fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 471fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 472fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 473fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 47461ab64e2SBaolin Wang } 47561ab64e2SBaolin Wang 47661ab64e2SBaolin Wang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 47761ab64e2SBaolin Wang { 47861ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 479fb8bd90fSChunyan Zhang 480fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 481fb8bd90fSChunyan Zhang } 482fb8bd90fSChunyan Zhang 48361ab64e2SBaolin Wang static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 48461ab64e2SBaolin Wang struct mmc_request *mrq) 48561ab64e2SBaolin Wang { 48661ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 48761ab64e2SBaolin Wang 48861ab64e2SBaolin Wang return sdhci_request_atomic(mmc, mrq); 48961ab64e2SBaolin Wang } 49061ab64e2SBaolin Wang 491eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 492eef9e0a6SBaolin Wang { 49329ca763fSBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 49429ca763fSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 495eef9e0a6SBaolin Wang int ret; 496eef9e0a6SBaolin Wang 497eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) { 498eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios); 4999cbe0fc8SMarek Vasut if (ret < 0) { 500eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n", 501eef9e0a6SBaolin Wang mmc_hostname(mmc)); 502eef9e0a6SBaolin Wang return ret; 503eef9e0a6SBaolin Wang } 504eef9e0a6SBaolin Wang } 505eef9e0a6SBaolin Wang 50629ca763fSBaolin Wang if (IS_ERR(sprd_host->pinctrl)) 507dd30dcfaSWenchao Chen goto reset; 50829ca763fSBaolin Wang 50929ca763fSBaolin Wang switch (ios->signal_voltage) { 51029ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_180: 51129ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 51229ca763fSBaolin Wang sprd_host->pins_uhs); 51329ca763fSBaolin Wang if (ret) { 51429ca763fSBaolin Wang pr_err("%s: failed to select uhs pin state\n", 51529ca763fSBaolin Wang mmc_hostname(mmc)); 51629ca763fSBaolin Wang return ret; 51729ca763fSBaolin Wang } 51829ca763fSBaolin Wang break; 51929ca763fSBaolin Wang 52029ca763fSBaolin Wang default: 521df561f66SGustavo A. R. Silva fallthrough; 52229ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_330: 52329ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 52429ca763fSBaolin Wang sprd_host->pins_default); 52529ca763fSBaolin Wang if (ret) { 52629ca763fSBaolin Wang pr_err("%s: failed to select default pin state\n", 52729ca763fSBaolin Wang mmc_hostname(mmc)); 52829ca763fSBaolin Wang return ret; 52929ca763fSBaolin Wang } 53029ca763fSBaolin Wang break; 53129ca763fSBaolin Wang } 53229ca763fSBaolin Wang 53329ca763fSBaolin Wang /* Wait for 300 ~ 500 us for pin state stable */ 53429ca763fSBaolin Wang usleep_range(300, 500); 535dd30dcfaSWenchao Chen 536dd30dcfaSWenchao Chen reset: 53729ca763fSBaolin Wang sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 53829ca763fSBaolin Wang 539eef9e0a6SBaolin Wang return 0; 540eef9e0a6SBaolin Wang } 541eef9e0a6SBaolin Wang 542494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 543494c11e1SBaolin Wang struct mmc_ios *ios) 544494c11e1SBaolin Wang { 545494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 5465f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 5475f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 548494c11e1SBaolin Wang u16 ctrl_2; 549494c11e1SBaolin Wang 550494c11e1SBaolin Wang if (!ios->enhanced_strobe) 551494c11e1SBaolin Wang return; 552494c11e1SBaolin Wang 553494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 554494c11e1SBaolin Wang 555494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 556494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 557494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 558494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 559494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 560494c11e1SBaolin Wang 561494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 5625f2f4e0dSBaolin Wang 5635f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 5645f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 5655f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY); 5665f2f4e0dSBaolin Wang } 5675f2f4e0dSBaolin Wang 568d83d251bSWenchao Chen static int mmc_send_tuning_cmd(struct mmc_card *card) 569d83d251bSWenchao Chen { 570d83d251bSWenchao Chen return mmc_send_status(card, NULL); 571d83d251bSWenchao Chen } 572d83d251bSWenchao Chen 573d83d251bSWenchao Chen static int mmc_send_tuning_data(struct mmc_card *card) 574d83d251bSWenchao Chen { 575d83d251bSWenchao Chen u8 *status; 576d83d251bSWenchao Chen int ret; 577d83d251bSWenchao Chen 578d83d251bSWenchao Chen status = kmalloc(64, GFP_KERNEL); 579d83d251bSWenchao Chen if (!status) 580d83d251bSWenchao Chen return -ENOMEM; 581d83d251bSWenchao Chen 582d83d251bSWenchao Chen ret = mmc_sd_switch(card, 0, 0, 0, status); 583d83d251bSWenchao Chen 584d83d251bSWenchao Chen kfree(status); 585d83d251bSWenchao Chen 586d83d251bSWenchao Chen return ret; 587d83d251bSWenchao Chen } 588d83d251bSWenchao Chen 589d83d251bSWenchao Chen static int sdhci_sprd_get_best_clk_sample(struct mmc_host *mmc, u8 *value) 590d83d251bSWenchao Chen { 591d83d251bSWenchao Chen int range_end = SDHCI_SPRD_MAX_RANGE; 592d83d251bSWenchao Chen int range_length = 0; 593d83d251bSWenchao Chen int middle_range = 0; 594d83d251bSWenchao Chen int count = 0; 595d83d251bSWenchao Chen int i; 596d83d251bSWenchao Chen 597d83d251bSWenchao Chen for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) { 598d83d251bSWenchao Chen if (value[i]) { 599d83d251bSWenchao Chen pr_debug("%s: tuning ok: %d\n", mmc_hostname(mmc), i); 600d83d251bSWenchao Chen count++; 601d83d251bSWenchao Chen } else { 602d83d251bSWenchao Chen pr_debug("%s: tuning fail: %d\n", mmc_hostname(mmc), i); 603d83d251bSWenchao Chen if (range_length < count) { 604d83d251bSWenchao Chen range_length = count; 605d83d251bSWenchao Chen range_end = i - 1; 606d83d251bSWenchao Chen count = 0; 607d83d251bSWenchao Chen } 608d83d251bSWenchao Chen } 609d83d251bSWenchao Chen } 610d83d251bSWenchao Chen 611d83d251bSWenchao Chen if (!count) 612d83d251bSWenchao Chen return -EIO; 613d83d251bSWenchao Chen 614d83d251bSWenchao Chen if (count > range_length) { 615d83d251bSWenchao Chen range_length = count; 616d83d251bSWenchao Chen range_end = i - 1; 617d83d251bSWenchao Chen } 618d83d251bSWenchao Chen 619d83d251bSWenchao Chen middle_range = range_end - (range_length - 1) / 2; 620d83d251bSWenchao Chen 621d83d251bSWenchao Chen return middle_range; 622d83d251bSWenchao Chen } 623d83d251bSWenchao Chen 624d83d251bSWenchao Chen static int sdhci_sprd_tuning(struct mmc_host *mmc, struct mmc_card *card, 625d83d251bSWenchao Chen enum sdhci_sprd_tuning_type type) 626d83d251bSWenchao Chen { 627d83d251bSWenchao Chen struct sdhci_host *host = mmc_priv(mmc); 628d83d251bSWenchao Chen struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 629d83d251bSWenchao Chen u32 *p = sprd_host->phy_delay; 630d83d251bSWenchao Chen u32 dll_cfg, dll_dly; 631d83d251bSWenchao Chen int best_clk_sample; 632d83d251bSWenchao Chen int err = 0; 633d83d251bSWenchao Chen u8 *value; 634d83d251bSWenchao Chen int i; 635d83d251bSWenchao Chen 636d83d251bSWenchao Chen value = kmalloc(SDHCI_SPRD_MAX_RANGE + 1, GFP_KERNEL); 637d83d251bSWenchao Chen if (!value) 638d83d251bSWenchao Chen return -ENOMEM; 639d83d251bSWenchao Chen 640d83d251bSWenchao Chen sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 641d83d251bSWenchao Chen 642d83d251bSWenchao Chen dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 643d83d251bSWenchao Chen dll_cfg &= ~SDHCI_SPRD_CPST_EN; 644d83d251bSWenchao Chen sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG); 645d83d251bSWenchao Chen 646d83d251bSWenchao Chen dll_dly = p[mmc->ios.timing]; 647d83d251bSWenchao Chen 648d83d251bSWenchao Chen for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) { 649d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) { 650d83d251bSWenchao Chen dll_dly &= ~SDHCI_SPRD_CMD_DLY_MASK; 651d83d251bSWenchao Chen dll_dly |= ((i << 8) & SDHCI_SPRD_CMD_DLY_MASK); 652d83d251bSWenchao Chen } else { 653d83d251bSWenchao Chen dll_dly &= ~SDHCI_SPRD_POSRD_DLY_MASK; 654d83d251bSWenchao Chen dll_dly |= ((i << 16) & SDHCI_SPRD_POSRD_DLY_MASK); 655d83d251bSWenchao Chen } 656d83d251bSWenchao Chen 657d83d251bSWenchao Chen sdhci_writel(host, dll_dly, SDHCI_SPRD_REG_32_DLL_DLY); 658d83d251bSWenchao Chen 659d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) 660d83d251bSWenchao Chen value[i] = !mmc_send_tuning_cmd(card); 661d83d251bSWenchao Chen else 662d83d251bSWenchao Chen value[i] = !mmc_send_tuning_data(card); 663d83d251bSWenchao Chen } 664d83d251bSWenchao Chen 665d83d251bSWenchao Chen best_clk_sample = sdhci_sprd_get_best_clk_sample(mmc, value); 666d83d251bSWenchao Chen if (best_clk_sample < 0) { 667d83d251bSWenchao Chen dev_err(mmc_dev(host->mmc), "all tuning phase fail!\n"); 668168054caSDan Carpenter err = best_clk_sample; 669d83d251bSWenchao Chen goto out; 670d83d251bSWenchao Chen } 671d83d251bSWenchao Chen 672d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) { 673d83d251bSWenchao Chen p[mmc->ios.timing] &= ~SDHCI_SPRD_CMD_DLY_MASK; 674d83d251bSWenchao Chen p[mmc->ios.timing] |= ((best_clk_sample << 8) & SDHCI_SPRD_CMD_DLY_MASK); 675d83d251bSWenchao Chen } else { 676d83d251bSWenchao Chen p[mmc->ios.timing] &= ~(SDHCI_SPRD_POSRD_DLY_MASK); 677d83d251bSWenchao Chen p[mmc->ios.timing] |= ((best_clk_sample << 16) & SDHCI_SPRD_POSRD_DLY_MASK); 678d83d251bSWenchao Chen } 679d83d251bSWenchao Chen 680d83d251bSWenchao Chen pr_debug("%s: the best clk sample %d, delay value 0x%08x\n", 681d83d251bSWenchao Chen mmc_hostname(host->mmc), best_clk_sample, p[mmc->ios.timing]); 682d83d251bSWenchao Chen 683d83d251bSWenchao Chen out: 684d83d251bSWenchao Chen sdhci_writel(host, p[mmc->ios.timing], SDHCI_SPRD_REG_32_DLL_DLY); 685d83d251bSWenchao Chen 686d83d251bSWenchao Chen kfree(value); 687d83d251bSWenchao Chen 688d83d251bSWenchao Chen return err; 689d83d251bSWenchao Chen } 690d83d251bSWenchao Chen 691d83d251bSWenchao Chen static int sdhci_sprd_prepare_sd_hs_cmd_tuning(struct mmc_host *mmc, struct mmc_card *card) 692d83d251bSWenchao Chen { 693d83d251bSWenchao Chen return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_CMD); 694d83d251bSWenchao Chen } 695d83d251bSWenchao Chen 696d83d251bSWenchao Chen static int sdhci_sprd_execute_sd_hs_data_tuning(struct mmc_host *mmc, struct mmc_card *card) 697d83d251bSWenchao Chen { 698d83d251bSWenchao Chen return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_DATA); 699d83d251bSWenchao Chen } 700d83d251bSWenchao Chen 7015f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 7025f2f4e0dSBaolin Wang struct device_node *np) 7035f2f4e0dSBaolin Wang { 7045f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 7055f2f4e0dSBaolin Wang int ret, i, index; 7065f2f4e0dSBaolin Wang u32 val[4]; 7075f2f4e0dSBaolin Wang 7085f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 7095f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np, 7105f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4); 7115f2f4e0dSBaolin Wang if (ret) 7125f2f4e0dSBaolin Wang continue; 7135f2f4e0dSBaolin Wang 7145f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing; 7155f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 7165f2f4e0dSBaolin Wang } 717494c11e1SBaolin Wang } 718494c11e1SBaolin Wang 719fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 7204324e54bSChunyan Zhang .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 721924ea310SAdrian Hunter SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 722fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 7236a526f66SChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 7246a526f66SChunyan Zhang SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 725fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 726fb8bd90fSChunyan Zhang }; 727fb8bd90fSChunyan Zhang 728fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 729fb8bd90fSChunyan Zhang { 730fb8bd90fSChunyan Zhang struct sdhci_host *host; 731fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 732f4498549SBaolin Wang struct mmc_hsq *hsq; 733fb8bd90fSChunyan Zhang struct clk *clk; 734fb8bd90fSChunyan Zhang int ret = 0; 735fb8bd90fSChunyan Zhang 736fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 737fb8bd90fSChunyan Zhang if (IS_ERR(host)) 738fb8bd90fSChunyan Zhang return PTR_ERR(host); 739fb8bd90fSChunyan Zhang 740fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 741fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 742fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 743494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 744494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 745d83d251bSWenchao Chen host->mmc_host_ops.prepare_sd_hs_tuning = 746d83d251bSWenchao Chen sdhci_sprd_prepare_sd_hs_cmd_tuning; 747d83d251bSWenchao Chen host->mmc_host_ops.execute_sd_hs_tuning = 748d83d251bSWenchao Chen sdhci_sprd_execute_sd_hs_data_tuning; 749d83d251bSWenchao Chen 750eef9e0a6SBaolin Wang /* 751eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage 752eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator 753eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control 754eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage. 755eef9e0a6SBaolin Wang */ 756eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch = 757eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch; 758fb8bd90fSChunyan Zhang 759fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 760a049b5aeSUlf Hansson MMC_CAP_WAIT_WHILE_BUSY; 761a049b5aeSUlf Hansson 762fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 763fb8bd90fSChunyan Zhang if (ret) 764fb8bd90fSChunyan Zhang goto pltfm_free; 765fb8bd90fSChunyan Zhang 76661ab64e2SBaolin Wang if (!mmc_card_is_removable(host->mmc)) 76761ab64e2SBaolin Wang host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 76861ab64e2SBaolin Wang else 76961ab64e2SBaolin Wang host->always_defer_done = true; 77061ab64e2SBaolin Wang 771fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 7725f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 773fb8bd90fSChunyan Zhang 77429ca763fSBaolin Wang sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 77529ca763fSBaolin Wang if (!IS_ERR(sprd_host->pinctrl)) { 77629ca763fSBaolin Wang sprd_host->pins_uhs = 77729ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 77829ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_uhs)) { 77929ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_uhs); 78029ca763fSBaolin Wang goto pltfm_free; 78129ca763fSBaolin Wang } 78229ca763fSBaolin Wang 78329ca763fSBaolin Wang sprd_host->pins_default = 78429ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "default"); 78529ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_default)) { 78629ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_default); 78729ca763fSBaolin Wang goto pltfm_free; 78829ca763fSBaolin Wang } 78929ca763fSBaolin Wang } 79029ca763fSBaolin Wang 791fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 792fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 793fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 794fb8bd90fSChunyan Zhang goto pltfm_free; 795fb8bd90fSChunyan Zhang } 796fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 797fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 798fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 799fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 800fb8bd90fSChunyan Zhang 801fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 802fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 803fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 804fb8bd90fSChunyan Zhang goto pltfm_free; 805fb8bd90fSChunyan Zhang } 806fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 807fb8bd90fSChunyan Zhang 808ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 809ebd88a38SBaolin Wang if (!IS_ERR(clk)) 810ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 811ebd88a38SBaolin Wang 812fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 813fb8bd90fSChunyan Zhang if (ret) 814fb8bd90fSChunyan Zhang goto pltfm_free; 815fb8bd90fSChunyan Zhang 8161d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 817fb8bd90fSChunyan Zhang if (ret) 818fb8bd90fSChunyan Zhang goto clk_disable; 819fb8bd90fSChunyan Zhang 820ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 821ebd88a38SBaolin Wang if (ret) 822ebd88a38SBaolin Wang goto clk_disable2; 823ebd88a38SBaolin Wang 824fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 825fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 826fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 827fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 828fb8bd90fSChunyan Zhang 829fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 830fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 831fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 832fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 833fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 834fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 835fb8bd90fSChunyan Zhang 836fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 837fb8bd90fSChunyan Zhang 8382f765c17SChunyan Zhang /* 8392f765c17SChunyan Zhang * Supply the existing CAPS, but clear the UHS-I modes. This 8402f765c17SChunyan Zhang * will allow these modes to be specified only by device 8412f765c17SChunyan Zhang * tree properties through mmc_of_parse(). 8422f765c17SChunyan Zhang */ 843924ea310SAdrian Hunter sdhci_read_caps(host); 8442f765c17SChunyan Zhang host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 8452f765c17SChunyan Zhang SDHCI_SUPPORT_DDR50); 8462f765c17SChunyan Zhang 847*cb42d0dcSWenchao Chen ret = mmc_regulator_get_supply(host->mmc); 848*cb42d0dcSWenchao Chen if (ret) 849*cb42d0dcSWenchao Chen goto pm_runtime_disable; 850*cb42d0dcSWenchao Chen 851fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 852fb8bd90fSChunyan Zhang if (ret) 853fb8bd90fSChunyan Zhang goto pm_runtime_disable; 854fb8bd90fSChunyan Zhang 855fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 856fb8bd90fSChunyan Zhang 857f4498549SBaolin Wang hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 858f4498549SBaolin Wang if (!hsq) { 859f4498549SBaolin Wang ret = -ENOMEM; 860f4498549SBaolin Wang goto err_cleanup_host; 861f4498549SBaolin Wang } 862f4498549SBaolin Wang 863f4498549SBaolin Wang ret = mmc_hsq_init(hsq, host->mmc); 864f4498549SBaolin Wang if (ret) 865f4498549SBaolin Wang goto err_cleanup_host; 866f4498549SBaolin Wang 867fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 868fb8bd90fSChunyan Zhang if (ret) 869fb8bd90fSChunyan Zhang goto err_cleanup_host; 870fb8bd90fSChunyan Zhang 871fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 872fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 873fb8bd90fSChunyan Zhang 874fb8bd90fSChunyan Zhang return 0; 875fb8bd90fSChunyan Zhang 876fb8bd90fSChunyan Zhang err_cleanup_host: 877fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 878fb8bd90fSChunyan Zhang 879fb8bd90fSChunyan Zhang pm_runtime_disable: 880fc62113bSBaolin Wang pm_runtime_put_noidle(&pdev->dev); 881fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 882fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 883fb8bd90fSChunyan Zhang 884ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 885ebd88a38SBaolin Wang 886ebd88a38SBaolin Wang clk_disable2: 887fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 888fb8bd90fSChunyan Zhang 889fb8bd90fSChunyan Zhang clk_disable: 890fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 891fb8bd90fSChunyan Zhang 892fb8bd90fSChunyan Zhang pltfm_free: 893fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 894fb8bd90fSChunyan Zhang return ret; 895fb8bd90fSChunyan Zhang } 896fb8bd90fSChunyan Zhang 897c618ba0fSYangtao Li static void sdhci_sprd_remove(struct platform_device *pdev) 898fb8bd90fSChunyan Zhang { 899fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 900fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 901fb8bd90fSChunyan Zhang 902c9c256a8SChristophe JAILLET sdhci_remove_host(host, 0); 903c9c256a8SChristophe JAILLET 904fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 905fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 906ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 907fb8bd90fSChunyan Zhang 908c9c256a8SChristophe JAILLET sdhci_pltfm_free(pdev); 909fb8bd90fSChunyan Zhang } 910fb8bd90fSChunyan Zhang 911fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 912fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 913fb8bd90fSChunyan Zhang { } 914fb8bd90fSChunyan Zhang }; 915fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 916fb8bd90fSChunyan Zhang 917fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 918fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 919fb8bd90fSChunyan Zhang { 920fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 921fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 922fb8bd90fSChunyan Zhang 923f4498549SBaolin Wang mmc_hsq_suspend(host->mmc); 924fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 925fb8bd90fSChunyan Zhang 926fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 927fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 928ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 929fb8bd90fSChunyan Zhang 930fb8bd90fSChunyan Zhang return 0; 931fb8bd90fSChunyan Zhang } 932fb8bd90fSChunyan Zhang 933fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 934fb8bd90fSChunyan Zhang { 935fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 936fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 937fb8bd90fSChunyan Zhang int ret; 938fb8bd90fSChunyan Zhang 939ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 940fb8bd90fSChunyan Zhang if (ret) 941fb8bd90fSChunyan Zhang return ret; 942fb8bd90fSChunyan Zhang 943ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 944ebd88a38SBaolin Wang if (ret) 945ebd88a38SBaolin Wang goto clk_2x_disable; 946ebd88a38SBaolin Wang 947fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 948ebd88a38SBaolin Wang if (ret) 949ebd88a38SBaolin Wang goto clk_disable; 950fb8bd90fSChunyan Zhang 951c6303c5dSBaolin Wang sdhci_runtime_resume_host(host, 1); 952f4498549SBaolin Wang mmc_hsq_resume(host->mmc); 953f4498549SBaolin Wang 954fb8bd90fSChunyan Zhang return 0; 955ebd88a38SBaolin Wang 956ebd88a38SBaolin Wang clk_disable: 957ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 958ebd88a38SBaolin Wang 959ebd88a38SBaolin Wang clk_2x_disable: 960ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 961ebd88a38SBaolin Wang 962ebd88a38SBaolin Wang return ret; 963fb8bd90fSChunyan Zhang } 964fb8bd90fSChunyan Zhang #endif 965fb8bd90fSChunyan Zhang 966fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 967fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 968fb8bd90fSChunyan Zhang pm_runtime_force_resume) 969fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 970fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 971fb8bd90fSChunyan Zhang }; 972fb8bd90fSChunyan Zhang 973fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 974fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 975c618ba0fSYangtao Li .remove_new = sdhci_sprd_remove, 976fb8bd90fSChunyan Zhang .driver = { 977fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 978d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 979a96e6523SKrzysztof Kozlowski .of_match_table = sdhci_sprd_of_match, 980fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 981fb8bd90fSChunyan Zhang }, 982fb8bd90fSChunyan Zhang }; 983fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 984fb8bd90fSChunyan Zhang 985fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 986fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 987fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 988