1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 117f00917aSZhenxiong Lai #include <linux/iopoll.h> 12fb8bd90fSChunyan Zhang #include <linux/module.h> 13fb8bd90fSChunyan Zhang #include <linux/of.h> 14fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 1529ca763fSBaolin Wang #include <linux/pinctrl/consumer.h> 16fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 17fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 18fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 19fb8bd90fSChunyan Zhang #include <linux/slab.h> 20fb8bd90fSChunyan Zhang 21fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 22f4498549SBaolin Wang #include "mmc_hsq.h" 23fb8bd90fSChunyan Zhang 24fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 25fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 26fb8bd90fSChunyan Zhang 2787a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 2887a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 2987a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 3187a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3287a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3387a395c2SBaolin Wang 345f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 355f2f4e0dSBaolin Wang 36fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 37fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 39fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 41fb8bd90fSChunyan Zhang 427f00917aSZhenxiong Lai #define SDHCI_SPRD_REG_32_DLL_STS0 0x210 437f00917aSZhenxiong Lai #define SDHCI_SPRD_DLL_LOCKED BIT(18) 447f00917aSZhenxiong Lai 45fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 46fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 47fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 48fb8bd90fSChunyan Zhang 49fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 50fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 51fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 52fb8bd90fSChunyan Zhang 53fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 54fb8bd90fSChunyan Zhang 55fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 56fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 57fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 58494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 59fb8bd90fSChunyan Zhang 60fb8bd90fSChunyan Zhang /* 61fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 62fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 63fb8bd90fSChunyan Zhang * if this bit is cleared. 64fb8bd90fSChunyan Zhang * 1 : normal work 65fb8bd90fSChunyan Zhang * 0 : hardware reset 66fb8bd90fSChunyan Zhang */ 67fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 68fb8bd90fSChunyan Zhang 69fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 70fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 71fb8bd90fSChunyan Zhang 72fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 7387a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 74fb8bd90fSChunyan Zhang 75fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 76fb8bd90fSChunyan Zhang u32 version; 77fb8bd90fSChunyan Zhang struct clk *clk_sdio; 78fb8bd90fSChunyan Zhang struct clk *clk_enable; 79ebd88a38SBaolin Wang struct clk *clk_2x_enable; 8029ca763fSBaolin Wang struct pinctrl *pinctrl; 8129ca763fSBaolin Wang struct pinctrl_state *pins_uhs; 8229ca763fSBaolin Wang struct pinctrl_state *pins_default; 83fb8bd90fSChunyan Zhang u32 base_rate; 84fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 855f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 865f2f4e0dSBaolin Wang }; 875f2f4e0dSBaolin Wang 885f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg { 895f2f4e0dSBaolin Wang const char *property; 905f2f4e0dSBaolin Wang u8 timing; 915f2f4e0dSBaolin Wang }; 925f2f4e0dSBaolin Wang 935f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 945f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 955f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 965f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 975f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 985f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 995f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 1005f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 1015f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 1025f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 103fb8bd90fSChunyan Zhang }; 104fb8bd90fSChunyan Zhang 105fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 106fb8bd90fSChunyan Zhang 107fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 108fb8bd90fSChunyan Zhang { 109fb8bd90fSChunyan Zhang u16 val; 110fb8bd90fSChunyan Zhang 111fb8bd90fSChunyan Zhang /* set dll backup mode */ 112fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 113fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 114fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 115fb8bd90fSChunyan Zhang } 116fb8bd90fSChunyan Zhang 117fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 118fb8bd90fSChunyan Zhang { 119fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 120fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 121fb8bd90fSChunyan Zhang 122fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 123fb8bd90fSChunyan Zhang } 124fb8bd90fSChunyan Zhang 125fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 126fb8bd90fSChunyan Zhang { 127fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 128fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 129fb8bd90fSChunyan Zhang return; 130fb8bd90fSChunyan Zhang 131fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 132fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 133fb8bd90fSChunyan Zhang 134fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 135fb8bd90fSChunyan Zhang } 136fb8bd90fSChunyan Zhang 137fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 138fb8bd90fSChunyan Zhang { 139fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 140fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 141fb8bd90fSChunyan Zhang return; 142fb8bd90fSChunyan Zhang 143fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 144fb8bd90fSChunyan Zhang } 145fb8bd90fSChunyan Zhang 146fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 147fb8bd90fSChunyan Zhang { 148fb8bd90fSChunyan Zhang /* 149fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 150fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 151fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 152fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 153fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 154fb8bd90fSChunyan Zhang * around it. 155fb8bd90fSChunyan Zhang */ 156fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 157fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 158fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 159fb8bd90fSChunyan Zhang } 160fb8bd90fSChunyan Zhang 161fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 162fb8bd90fSChunyan Zhang } 163fb8bd90fSChunyan Zhang 164fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 165fb8bd90fSChunyan Zhang { 166fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 167fb8bd90fSChunyan Zhang 168fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 169fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 170fb8bd90fSChunyan Zhang } 171fb8bd90fSChunyan Zhang 172494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 173494c11e1SBaolin Wang { 174494c11e1SBaolin Wang u16 ctrl; 175494c11e1SBaolin Wang 176494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 177494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 178494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 179494c11e1SBaolin Wang } 180494c11e1SBaolin Wang 181fb8bd90fSChunyan Zhang static inline void 182fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 183fb8bd90fSChunyan Zhang { 184fb8bd90fSChunyan Zhang u32 dll_dly_offset; 185fb8bd90fSChunyan Zhang 186fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 187fb8bd90fSChunyan Zhang if (en) 188fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 189fb8bd90fSChunyan Zhang else 190fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 191fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 192fb8bd90fSChunyan Zhang } 193fb8bd90fSChunyan Zhang 194fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 195fb8bd90fSChunyan Zhang { 196fb8bd90fSChunyan Zhang u32 div; 197fb8bd90fSChunyan Zhang 198fb8bd90fSChunyan Zhang /* select 2x clock source */ 199fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 200fb8bd90fSChunyan Zhang return 0; 201fb8bd90fSChunyan Zhang 202fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 203fb8bd90fSChunyan Zhang 204fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 205fb8bd90fSChunyan Zhang div++; 206fb8bd90fSChunyan Zhang 207fb8bd90fSChunyan Zhang if (div % 2) 208fb8bd90fSChunyan Zhang div = (div + 1) / 2; 209fb8bd90fSChunyan Zhang else 210fb8bd90fSChunyan Zhang div = div / 2; 211fb8bd90fSChunyan Zhang 212d252e9b1SWenchao Chen if (div > SDHCI_SPRD_CLK_MAX_DIV) 213d252e9b1SWenchao Chen div = SDHCI_SPRD_CLK_MAX_DIV; 214d252e9b1SWenchao Chen 215fb8bd90fSChunyan Zhang return div; 216fb8bd90fSChunyan Zhang } 217fb8bd90fSChunyan Zhang 218fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 219fb8bd90fSChunyan Zhang unsigned int clk) 220fb8bd90fSChunyan Zhang { 221fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 222fb8bd90fSChunyan Zhang u32 div, val, mask; 223fb8bd90fSChunyan Zhang 224efdaf275SChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 225fb8bd90fSChunyan Zhang 226efdaf275SChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 227efdaf275SChunyan Zhang div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 228efdaf275SChunyan Zhang sdhci_enable_clk(host, div); 229fb8bd90fSChunyan Zhang 230ff874dbcSWenchao Chen /* Enable CLK_AUTO when the clock is greater than 400K. */ 231ff874dbcSWenchao Chen if (clk > 400000) { 232fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 233fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 234fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 235fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 236fb8bd90fSChunyan Zhang val |= mask; 237fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 238fb8bd90fSChunyan Zhang } 239fb8bd90fSChunyan Zhang } 240ff874dbcSWenchao Chen } 241fb8bd90fSChunyan Zhang 24287a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 24387a395c2SBaolin Wang { 24487a395c2SBaolin Wang u32 tmp; 24587a395c2SBaolin Wang 24687a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24787a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 24887a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 24987a395c2SBaolin Wang /* wait 1ms */ 25087a395c2SBaolin Wang usleep_range(1000, 1250); 25187a395c2SBaolin Wang 25287a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 25387a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 25487a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 25587a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 25687a395c2SBaolin Wang /* wait 1ms */ 25787a395c2SBaolin Wang usleep_range(1000, 1250); 25887a395c2SBaolin Wang 25987a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 26087a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 26187a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 26287a395c2SBaolin Wang /* wait 1ms */ 26387a395c2SBaolin Wang usleep_range(1000, 1250); 2647f00917aSZhenxiong Lai 2657f00917aSZhenxiong Lai if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED), 2667f00917aSZhenxiong Lai 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) { 2677f00917aSZhenxiong Lai pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc)); 2687f00917aSZhenxiong Lai pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n", 2697f00917aSZhenxiong Lai mmc_hostname(host->mmc), 2707f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0), 2717f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG)); 2727f00917aSZhenxiong Lai } 27387a395c2SBaolin Wang } 27487a395c2SBaolin Wang 275fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 276fb8bd90fSChunyan Zhang { 27787a395c2SBaolin Wang bool en = false, clk_changed = false; 278fb8bd90fSChunyan Zhang 279fb8bd90fSChunyan Zhang if (clock == 0) { 280fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 281fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 282fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 283fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 284fb8bd90fSChunyan Zhang 285fb8bd90fSChunyan Zhang if (clock <= 400000) 286fb8bd90fSChunyan Zhang en = true; 287fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 288fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 28987a395c2SBaolin Wang clk_changed = true; 290fb8bd90fSChunyan Zhang } else { 291fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 292fb8bd90fSChunyan Zhang } 29387a395c2SBaolin Wang 29487a395c2SBaolin Wang /* 29587a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 29687a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 29787a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 29887a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 29987a395c2SBaolin Wang */ 30087a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 30187a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 302fb8bd90fSChunyan Zhang } 303fb8bd90fSChunyan Zhang 304fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 305fb8bd90fSChunyan Zhang { 306fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 307fb8bd90fSChunyan Zhang 308fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 309fb8bd90fSChunyan Zhang } 310fb8bd90fSChunyan Zhang 311fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 312fb8bd90fSChunyan Zhang { 3136e141772SWenchao Chen return 100000; 314fb8bd90fSChunyan Zhang } 315fb8bd90fSChunyan Zhang 316fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 317fb8bd90fSChunyan Zhang unsigned int timing) 318fb8bd90fSChunyan Zhang { 3195f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 3205f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc; 3215f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 322fb8bd90fSChunyan Zhang u16 ctrl_2; 323fb8bd90fSChunyan Zhang 324fb8bd90fSChunyan Zhang if (timing == host->timing) 325fb8bd90fSChunyan Zhang return; 326fb8bd90fSChunyan Zhang 327fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 328fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 329fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 330fb8bd90fSChunyan Zhang switch (timing) { 331fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 332fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 333fb8bd90fSChunyan Zhang break; 334fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 335fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 336fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 337fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 338fb8bd90fSChunyan Zhang break; 339fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 340fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 341fb8bd90fSChunyan Zhang break; 342fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 343fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 344fb8bd90fSChunyan Zhang break; 345fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 346fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 347fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 348fb8bd90fSChunyan Zhang break; 349fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 350fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 351fb8bd90fSChunyan Zhang break; 352fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 353fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 354fb8bd90fSChunyan Zhang break; 355fb8bd90fSChunyan Zhang default: 356fb8bd90fSChunyan Zhang break; 357fb8bd90fSChunyan Zhang } 358fb8bd90fSChunyan Zhang 359fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 3605f2f4e0dSBaolin Wang 3615f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe) 3625f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 363fb8bd90fSChunyan Zhang } 364fb8bd90fSChunyan Zhang 365fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 366fb8bd90fSChunyan Zhang { 367fb8bd90fSChunyan Zhang int val; 368fb8bd90fSChunyan Zhang 369fb8bd90fSChunyan Zhang /* 370fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 371fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 372fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 373fb8bd90fSChunyan Zhang * not be cleared. 374fb8bd90fSChunyan Zhang */ 375fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 376fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 377fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 378fb8bd90fSChunyan Zhang /* wait for 10 us */ 379fb8bd90fSChunyan Zhang usleep_range(10, 20); 380fb8bd90fSChunyan Zhang 381fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 382fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 383fb8bd90fSChunyan Zhang usleep_range(300, 500); 384fb8bd90fSChunyan Zhang } 385fb8bd90fSChunyan Zhang 3867486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3877486831dSBaolin Wang { 3887486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 3897486831dSBaolin Wang return 1 << 31; 3907486831dSBaolin Wang } 3917486831dSBaolin Wang 3924eae8cbdSChunyan Zhang static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 3934eae8cbdSChunyan Zhang { 3944eae8cbdSChunyan Zhang return 0; 3954eae8cbdSChunyan Zhang } 3964eae8cbdSChunyan Zhang 397f4498549SBaolin Wang static void sdhci_sprd_request_done(struct sdhci_host *host, 398f4498549SBaolin Wang struct mmc_request *mrq) 399f4498549SBaolin Wang { 400f4498549SBaolin Wang /* Validate if the request was from software queue firstly. */ 401f4498549SBaolin Wang if (mmc_hsq_finalize_request(host->mmc, mrq)) 402f4498549SBaolin Wang return; 403f4498549SBaolin Wang 404f4498549SBaolin Wang mmc_request_done(host->mmc, mrq); 405f4498549SBaolin Wang } 406f4498549SBaolin Wang 407fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 408fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 409fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 41096147082SKrzysztof Kozlowski .write_w = sdhci_sprd_writew, 411fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 412fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 413fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 414fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 415fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 416fb8bd90fSChunyan Zhang .reset = sdhci_reset, 417fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 418fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 4197486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 4204eae8cbdSChunyan Zhang .get_ro = sdhci_sprd_get_ro, 421f4498549SBaolin Wang .request_done = sdhci_sprd_request_done, 422fb8bd90fSChunyan Zhang }; 423fb8bd90fSChunyan Zhang 42461ab64e2SBaolin Wang static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 42561ab64e2SBaolin Wang struct mmc_request *mrq) 426fb8bd90fSChunyan Zhang { 427fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 428fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 429fb8bd90fSChunyan Zhang 430fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 431fb8bd90fSChunyan Zhang 432fb8bd90fSChunyan Zhang /* 433fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 434fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 435fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 436fb8bd90fSChunyan Zhang */ 437fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 438fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 439fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 440fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 44161ab64e2SBaolin Wang } 44261ab64e2SBaolin Wang 44361ab64e2SBaolin Wang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 44461ab64e2SBaolin Wang { 44561ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 446fb8bd90fSChunyan Zhang 447fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 448fb8bd90fSChunyan Zhang } 449fb8bd90fSChunyan Zhang 45061ab64e2SBaolin Wang static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 45161ab64e2SBaolin Wang struct mmc_request *mrq) 45261ab64e2SBaolin Wang { 45361ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 45461ab64e2SBaolin Wang 45561ab64e2SBaolin Wang return sdhci_request_atomic(mmc, mrq); 45661ab64e2SBaolin Wang } 45761ab64e2SBaolin Wang 458eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 459eef9e0a6SBaolin Wang { 46029ca763fSBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 46129ca763fSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 462eef9e0a6SBaolin Wang int ret; 463eef9e0a6SBaolin Wang 464eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) { 465eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios); 4669cbe0fc8SMarek Vasut if (ret < 0) { 467eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n", 468eef9e0a6SBaolin Wang mmc_hostname(mmc)); 469eef9e0a6SBaolin Wang return ret; 470eef9e0a6SBaolin Wang } 471eef9e0a6SBaolin Wang } 472eef9e0a6SBaolin Wang 47329ca763fSBaolin Wang if (IS_ERR(sprd_host->pinctrl)) 474dd30dcfaSWenchao Chen goto reset; 47529ca763fSBaolin Wang 47629ca763fSBaolin Wang switch (ios->signal_voltage) { 47729ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_180: 47829ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 47929ca763fSBaolin Wang sprd_host->pins_uhs); 48029ca763fSBaolin Wang if (ret) { 48129ca763fSBaolin Wang pr_err("%s: failed to select uhs pin state\n", 48229ca763fSBaolin Wang mmc_hostname(mmc)); 48329ca763fSBaolin Wang return ret; 48429ca763fSBaolin Wang } 48529ca763fSBaolin Wang break; 48629ca763fSBaolin Wang 48729ca763fSBaolin Wang default: 488df561f66SGustavo A. R. Silva fallthrough; 48929ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_330: 49029ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 49129ca763fSBaolin Wang sprd_host->pins_default); 49229ca763fSBaolin Wang if (ret) { 49329ca763fSBaolin Wang pr_err("%s: failed to select default pin state\n", 49429ca763fSBaolin Wang mmc_hostname(mmc)); 49529ca763fSBaolin Wang return ret; 49629ca763fSBaolin Wang } 49729ca763fSBaolin Wang break; 49829ca763fSBaolin Wang } 49929ca763fSBaolin Wang 50029ca763fSBaolin Wang /* Wait for 300 ~ 500 us for pin state stable */ 50129ca763fSBaolin Wang usleep_range(300, 500); 502dd30dcfaSWenchao Chen 503dd30dcfaSWenchao Chen reset: 50429ca763fSBaolin Wang sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 50529ca763fSBaolin Wang 506eef9e0a6SBaolin Wang return 0; 507eef9e0a6SBaolin Wang } 508eef9e0a6SBaolin Wang 509494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 510494c11e1SBaolin Wang struct mmc_ios *ios) 511494c11e1SBaolin Wang { 512494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 5135f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 5145f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 515494c11e1SBaolin Wang u16 ctrl_2; 516494c11e1SBaolin Wang 517494c11e1SBaolin Wang if (!ios->enhanced_strobe) 518494c11e1SBaolin Wang return; 519494c11e1SBaolin Wang 520494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 521494c11e1SBaolin Wang 522494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 523494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 524494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 525494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 526494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 527494c11e1SBaolin Wang 528494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 5295f2f4e0dSBaolin Wang 5305f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 5315f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 5325f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY); 5335f2f4e0dSBaolin Wang } 5345f2f4e0dSBaolin Wang 5355f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 5365f2f4e0dSBaolin Wang struct device_node *np) 5375f2f4e0dSBaolin Wang { 5385f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 5395f2f4e0dSBaolin Wang int ret, i, index; 5405f2f4e0dSBaolin Wang u32 val[4]; 5415f2f4e0dSBaolin Wang 5425f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 5435f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np, 5445f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4); 5455f2f4e0dSBaolin Wang if (ret) 5465f2f4e0dSBaolin Wang continue; 5475f2f4e0dSBaolin Wang 5485f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing; 5495f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 5505f2f4e0dSBaolin Wang } 551494c11e1SBaolin Wang } 552494c11e1SBaolin Wang 553fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 5544324e54bSChunyan Zhang .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 555924ea310SAdrian Hunter SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 556fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 5576a526f66SChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 5586a526f66SChunyan Zhang SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 559fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 560fb8bd90fSChunyan Zhang }; 561fb8bd90fSChunyan Zhang 562fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 563fb8bd90fSChunyan Zhang { 564fb8bd90fSChunyan Zhang struct sdhci_host *host; 565fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 566f4498549SBaolin Wang struct mmc_hsq *hsq; 567fb8bd90fSChunyan Zhang struct clk *clk; 568fb8bd90fSChunyan Zhang int ret = 0; 569fb8bd90fSChunyan Zhang 570fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 571fb8bd90fSChunyan Zhang if (IS_ERR(host)) 572fb8bd90fSChunyan Zhang return PTR_ERR(host); 573fb8bd90fSChunyan Zhang 574fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 575fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 576fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 577494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 578494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 579eef9e0a6SBaolin Wang /* 580eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage 581eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator 582eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control 583eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage. 584eef9e0a6SBaolin Wang */ 585eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch = 586eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch; 587fb8bd90fSChunyan Zhang 588fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 589a049b5aeSUlf Hansson MMC_CAP_WAIT_WHILE_BUSY; 590a049b5aeSUlf Hansson 591fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 592fb8bd90fSChunyan Zhang if (ret) 593fb8bd90fSChunyan Zhang goto pltfm_free; 594fb8bd90fSChunyan Zhang 59561ab64e2SBaolin Wang if (!mmc_card_is_removable(host->mmc)) 59661ab64e2SBaolin Wang host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 59761ab64e2SBaolin Wang else 59861ab64e2SBaolin Wang host->always_defer_done = true; 59961ab64e2SBaolin Wang 600fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 6015f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 602fb8bd90fSChunyan Zhang 60329ca763fSBaolin Wang sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 60429ca763fSBaolin Wang if (!IS_ERR(sprd_host->pinctrl)) { 60529ca763fSBaolin Wang sprd_host->pins_uhs = 60629ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 60729ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_uhs)) { 60829ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_uhs); 60929ca763fSBaolin Wang goto pltfm_free; 61029ca763fSBaolin Wang } 61129ca763fSBaolin Wang 61229ca763fSBaolin Wang sprd_host->pins_default = 61329ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "default"); 61429ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_default)) { 61529ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_default); 61629ca763fSBaolin Wang goto pltfm_free; 61729ca763fSBaolin Wang } 61829ca763fSBaolin Wang } 61929ca763fSBaolin Wang 620fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 621fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 622fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 623fb8bd90fSChunyan Zhang goto pltfm_free; 624fb8bd90fSChunyan Zhang } 625fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 626fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 627fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 628fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 629fb8bd90fSChunyan Zhang 630fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 631fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 632fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 633fb8bd90fSChunyan Zhang goto pltfm_free; 634fb8bd90fSChunyan Zhang } 635fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 636fb8bd90fSChunyan Zhang 637ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 638ebd88a38SBaolin Wang if (!IS_ERR(clk)) 639ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 640ebd88a38SBaolin Wang 641fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 642fb8bd90fSChunyan Zhang if (ret) 643fb8bd90fSChunyan Zhang goto pltfm_free; 644fb8bd90fSChunyan Zhang 6451d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 646fb8bd90fSChunyan Zhang if (ret) 647fb8bd90fSChunyan Zhang goto clk_disable; 648fb8bd90fSChunyan Zhang 649ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 650ebd88a38SBaolin Wang if (ret) 651ebd88a38SBaolin Wang goto clk_disable2; 652ebd88a38SBaolin Wang 653fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 654fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 655fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 656fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 657fb8bd90fSChunyan Zhang 658fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 659fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 660fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 661fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 662fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 663fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 664fb8bd90fSChunyan Zhang 665fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 666fb8bd90fSChunyan Zhang 6672f765c17SChunyan Zhang /* 6682f765c17SChunyan Zhang * Supply the existing CAPS, but clear the UHS-I modes. This 6692f765c17SChunyan Zhang * will allow these modes to be specified only by device 6702f765c17SChunyan Zhang * tree properties through mmc_of_parse(). 6712f765c17SChunyan Zhang */ 672924ea310SAdrian Hunter sdhci_read_caps(host); 6732f765c17SChunyan Zhang host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 6742f765c17SChunyan Zhang SDHCI_SUPPORT_DDR50); 6752f765c17SChunyan Zhang 676fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 677fb8bd90fSChunyan Zhang if (ret) 678fb8bd90fSChunyan Zhang goto pm_runtime_disable; 679fb8bd90fSChunyan Zhang 680fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 681fb8bd90fSChunyan Zhang 682f4498549SBaolin Wang hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 683f4498549SBaolin Wang if (!hsq) { 684f4498549SBaolin Wang ret = -ENOMEM; 685f4498549SBaolin Wang goto err_cleanup_host; 686f4498549SBaolin Wang } 687f4498549SBaolin Wang 688f4498549SBaolin Wang ret = mmc_hsq_init(hsq, host->mmc); 689f4498549SBaolin Wang if (ret) 690f4498549SBaolin Wang goto err_cleanup_host; 691f4498549SBaolin Wang 692fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 693fb8bd90fSChunyan Zhang if (ret) 694fb8bd90fSChunyan Zhang goto err_cleanup_host; 695fb8bd90fSChunyan Zhang 696fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 697fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 698fb8bd90fSChunyan Zhang 699fb8bd90fSChunyan Zhang return 0; 700fb8bd90fSChunyan Zhang 701fb8bd90fSChunyan Zhang err_cleanup_host: 702fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 703fb8bd90fSChunyan Zhang 704fb8bd90fSChunyan Zhang pm_runtime_disable: 705fc62113bSBaolin Wang pm_runtime_put_noidle(&pdev->dev); 706fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 707fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 708fb8bd90fSChunyan Zhang 709ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 710ebd88a38SBaolin Wang 711ebd88a38SBaolin Wang clk_disable2: 712fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 713fb8bd90fSChunyan Zhang 714fb8bd90fSChunyan Zhang clk_disable: 715fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 716fb8bd90fSChunyan Zhang 717fb8bd90fSChunyan Zhang pltfm_free: 718fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 719fb8bd90fSChunyan Zhang return ret; 720fb8bd90fSChunyan Zhang } 721fb8bd90fSChunyan Zhang 722*c618ba0fSYangtao Li static void sdhci_sprd_remove(struct platform_device *pdev) 723fb8bd90fSChunyan Zhang { 724fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 725fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 726fb8bd90fSChunyan Zhang 727c9c256a8SChristophe JAILLET sdhci_remove_host(host, 0); 728c9c256a8SChristophe JAILLET 729fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 730fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 731ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 732fb8bd90fSChunyan Zhang 733c9c256a8SChristophe JAILLET sdhci_pltfm_free(pdev); 734fb8bd90fSChunyan Zhang } 735fb8bd90fSChunyan Zhang 736fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 737fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 738fb8bd90fSChunyan Zhang { } 739fb8bd90fSChunyan Zhang }; 740fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 741fb8bd90fSChunyan Zhang 742fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 743fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 744fb8bd90fSChunyan Zhang { 745fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 746fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 747fb8bd90fSChunyan Zhang 748f4498549SBaolin Wang mmc_hsq_suspend(host->mmc); 749fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 750fb8bd90fSChunyan Zhang 751fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 752fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 753ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 754fb8bd90fSChunyan Zhang 755fb8bd90fSChunyan Zhang return 0; 756fb8bd90fSChunyan Zhang } 757fb8bd90fSChunyan Zhang 758fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 759fb8bd90fSChunyan Zhang { 760fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 761fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 762fb8bd90fSChunyan Zhang int ret; 763fb8bd90fSChunyan Zhang 764ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 765fb8bd90fSChunyan Zhang if (ret) 766fb8bd90fSChunyan Zhang return ret; 767fb8bd90fSChunyan Zhang 768ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 769ebd88a38SBaolin Wang if (ret) 770ebd88a38SBaolin Wang goto clk_2x_disable; 771ebd88a38SBaolin Wang 772fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 773ebd88a38SBaolin Wang if (ret) 774ebd88a38SBaolin Wang goto clk_disable; 775fb8bd90fSChunyan Zhang 776c6303c5dSBaolin Wang sdhci_runtime_resume_host(host, 1); 777f4498549SBaolin Wang mmc_hsq_resume(host->mmc); 778f4498549SBaolin Wang 779fb8bd90fSChunyan Zhang return 0; 780ebd88a38SBaolin Wang 781ebd88a38SBaolin Wang clk_disable: 782ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 783ebd88a38SBaolin Wang 784ebd88a38SBaolin Wang clk_2x_disable: 785ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 786ebd88a38SBaolin Wang 787ebd88a38SBaolin Wang return ret; 788fb8bd90fSChunyan Zhang } 789fb8bd90fSChunyan Zhang #endif 790fb8bd90fSChunyan Zhang 791fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 792fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 793fb8bd90fSChunyan Zhang pm_runtime_force_resume) 794fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 795fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 796fb8bd90fSChunyan Zhang }; 797fb8bd90fSChunyan Zhang 798fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 799fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 800*c618ba0fSYangtao Li .remove_new = sdhci_sprd_remove, 801fb8bd90fSChunyan Zhang .driver = { 802fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 803d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 804a96e6523SKrzysztof Kozlowski .of_match_table = sdhci_sprd_of_match, 805fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 806fb8bd90fSChunyan Zhang }, 807fb8bd90fSChunyan Zhang }; 808fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 809fb8bd90fSChunyan Zhang 810fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 811fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 812fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 813