1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 11fb8bd90fSChunyan Zhang #include <linux/module.h> 12fb8bd90fSChunyan Zhang #include <linux/of.h> 13fb8bd90fSChunyan Zhang #include <linux/of_device.h> 14fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 1529ca763fSBaolin Wang #include <linux/pinctrl/consumer.h> 16fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 17fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 18fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 19fb8bd90fSChunyan Zhang #include <linux/slab.h> 20fb8bd90fSChunyan Zhang 21fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 22f4498549SBaolin Wang #include "mmc_hsq.h" 23fb8bd90fSChunyan Zhang 24fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 25fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 26fb8bd90fSChunyan Zhang 2787a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 2887a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 2987a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 3187a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3287a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3387a395c2SBaolin Wang 345f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204 355f2f4e0dSBaolin Wang 36fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 37fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 39fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 41fb8bd90fSChunyan Zhang 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 43fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 44fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 45fb8bd90fSChunyan Zhang 46fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 47fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 48fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 49fb8bd90fSChunyan Zhang 50fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 51fb8bd90fSChunyan Zhang 52fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 53fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 54fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 55494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 56fb8bd90fSChunyan Zhang 57fb8bd90fSChunyan Zhang /* 58fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 59fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 60fb8bd90fSChunyan Zhang * if this bit is cleared. 61fb8bd90fSChunyan Zhang * 1 : normal work 62fb8bd90fSChunyan Zhang * 0 : hardware reset 63fb8bd90fSChunyan Zhang */ 64fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 65fb8bd90fSChunyan Zhang 66fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 67fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 68fb8bd90fSChunyan Zhang 69fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 7087a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 71fb8bd90fSChunyan Zhang 72fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 73fb8bd90fSChunyan Zhang u32 version; 74fb8bd90fSChunyan Zhang struct clk *clk_sdio; 75fb8bd90fSChunyan Zhang struct clk *clk_enable; 76ebd88a38SBaolin Wang struct clk *clk_2x_enable; 7729ca763fSBaolin Wang struct pinctrl *pinctrl; 7829ca763fSBaolin Wang struct pinctrl_state *pins_uhs; 7929ca763fSBaolin Wang struct pinctrl_state *pins_default; 80fb8bd90fSChunyan Zhang u32 base_rate; 81fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 825f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2]; 835f2f4e0dSBaolin Wang }; 845f2f4e0dSBaolin Wang 855f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg { 865f2f4e0dSBaolin Wang const char *property; 875f2f4e0dSBaolin Wang u8 timing; 885f2f4e0dSBaolin Wang }; 895f2f4e0dSBaolin Wang 905f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = { 915f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, }, 925f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, }, 935f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, }, 945f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, }, 955f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, }, 965f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, }, 975f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, }, 985f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, }, 995f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, }, 100fb8bd90fSChunyan Zhang }; 101fb8bd90fSChunyan Zhang 102fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 103fb8bd90fSChunyan Zhang 104fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 105fb8bd90fSChunyan Zhang { 106fb8bd90fSChunyan Zhang u16 val; 107fb8bd90fSChunyan Zhang 108fb8bd90fSChunyan Zhang /* set dll backup mode */ 109fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 110fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 111fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 112fb8bd90fSChunyan Zhang } 113fb8bd90fSChunyan Zhang 114fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 115fb8bd90fSChunyan Zhang { 116fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 117fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 118fb8bd90fSChunyan Zhang 119fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 120fb8bd90fSChunyan Zhang } 121fb8bd90fSChunyan Zhang 122fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 123fb8bd90fSChunyan Zhang { 124fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 125fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 126fb8bd90fSChunyan Zhang return; 127fb8bd90fSChunyan Zhang 128fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 129fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 130fb8bd90fSChunyan Zhang 131fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 132fb8bd90fSChunyan Zhang } 133fb8bd90fSChunyan Zhang 134fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 135fb8bd90fSChunyan Zhang { 136fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 137fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 138fb8bd90fSChunyan Zhang return; 139fb8bd90fSChunyan Zhang 140fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 141fb8bd90fSChunyan Zhang } 142fb8bd90fSChunyan Zhang 143fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 144fb8bd90fSChunyan Zhang { 145fb8bd90fSChunyan Zhang /* 146fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 147fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 148fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 149fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 150fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 151fb8bd90fSChunyan Zhang * around it. 152fb8bd90fSChunyan Zhang */ 153fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 154fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 155fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 156fb8bd90fSChunyan Zhang } 157fb8bd90fSChunyan Zhang 158fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 159fb8bd90fSChunyan Zhang } 160fb8bd90fSChunyan Zhang 161fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 162fb8bd90fSChunyan Zhang { 163fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 164fb8bd90fSChunyan Zhang 165fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 166fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 167fb8bd90fSChunyan Zhang } 168fb8bd90fSChunyan Zhang 169494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 170494c11e1SBaolin Wang { 171494c11e1SBaolin Wang u16 ctrl; 172494c11e1SBaolin Wang 173494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 174494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 175494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 176494c11e1SBaolin Wang } 177494c11e1SBaolin Wang 178fb8bd90fSChunyan Zhang static inline void 179fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 180fb8bd90fSChunyan Zhang { 181fb8bd90fSChunyan Zhang u32 dll_dly_offset; 182fb8bd90fSChunyan Zhang 183fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 184fb8bd90fSChunyan Zhang if (en) 185fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 186fb8bd90fSChunyan Zhang else 187fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 188fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 189fb8bd90fSChunyan Zhang } 190fb8bd90fSChunyan Zhang 191fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 192fb8bd90fSChunyan Zhang { 193fb8bd90fSChunyan Zhang u32 div; 194fb8bd90fSChunyan Zhang 195fb8bd90fSChunyan Zhang /* select 2x clock source */ 196fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 197fb8bd90fSChunyan Zhang return 0; 198fb8bd90fSChunyan Zhang 199fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 200fb8bd90fSChunyan Zhang 201fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 202fb8bd90fSChunyan Zhang div++; 203fb8bd90fSChunyan Zhang 204fb8bd90fSChunyan Zhang if (div > SDHCI_SPRD_CLK_MAX_DIV) 205fb8bd90fSChunyan Zhang div = SDHCI_SPRD_CLK_MAX_DIV; 206fb8bd90fSChunyan Zhang 207fb8bd90fSChunyan Zhang if (div % 2) 208fb8bd90fSChunyan Zhang div = (div + 1) / 2; 209fb8bd90fSChunyan Zhang else 210fb8bd90fSChunyan Zhang div = div / 2; 211fb8bd90fSChunyan Zhang 212fb8bd90fSChunyan Zhang return div; 213fb8bd90fSChunyan Zhang } 214fb8bd90fSChunyan Zhang 215fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 216fb8bd90fSChunyan Zhang unsigned int clk) 217fb8bd90fSChunyan Zhang { 218fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 219fb8bd90fSChunyan Zhang u32 div, val, mask; 220fb8bd90fSChunyan Zhang 221efdaf275SChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 222fb8bd90fSChunyan Zhang 223efdaf275SChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 224efdaf275SChunyan Zhang div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 225efdaf275SChunyan Zhang sdhci_enable_clk(host, div); 226fb8bd90fSChunyan Zhang 227fb8bd90fSChunyan Zhang /* enable auto gate sdhc_enable_auto_gate */ 228fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 229fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 230fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 231fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 232fb8bd90fSChunyan Zhang val |= mask; 233fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 234fb8bd90fSChunyan Zhang } 235fb8bd90fSChunyan Zhang } 236fb8bd90fSChunyan Zhang 23787a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 23887a395c2SBaolin Wang { 23987a395c2SBaolin Wang u32 tmp; 24087a395c2SBaolin Wang 24187a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24287a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 24387a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 24487a395c2SBaolin Wang /* wait 1ms */ 24587a395c2SBaolin Wang usleep_range(1000, 1250); 24687a395c2SBaolin Wang 24787a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 24887a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 24987a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 25087a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 25187a395c2SBaolin Wang /* wait 1ms */ 25287a395c2SBaolin Wang usleep_range(1000, 1250); 25387a395c2SBaolin Wang 25487a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 25587a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 25687a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 25787a395c2SBaolin Wang /* wait 1ms */ 25887a395c2SBaolin Wang usleep_range(1000, 1250); 25987a395c2SBaolin Wang } 26087a395c2SBaolin Wang 261fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 262fb8bd90fSChunyan Zhang { 26387a395c2SBaolin Wang bool en = false, clk_changed = false; 264fb8bd90fSChunyan Zhang 265fb8bd90fSChunyan Zhang if (clock == 0) { 266fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 267fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 268fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 269fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 270fb8bd90fSChunyan Zhang 271fb8bd90fSChunyan Zhang if (clock <= 400000) 272fb8bd90fSChunyan Zhang en = true; 273fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 274fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 27587a395c2SBaolin Wang clk_changed = true; 276fb8bd90fSChunyan Zhang } else { 277fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 278fb8bd90fSChunyan Zhang } 27987a395c2SBaolin Wang 28087a395c2SBaolin Wang /* 28187a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 28287a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 28387a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 28487a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 28587a395c2SBaolin Wang */ 28687a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 28787a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 288fb8bd90fSChunyan Zhang } 289fb8bd90fSChunyan Zhang 290fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 291fb8bd90fSChunyan Zhang { 292fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 293fb8bd90fSChunyan Zhang 294fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 295fb8bd90fSChunyan Zhang } 296fb8bd90fSChunyan Zhang 297fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 298fb8bd90fSChunyan Zhang { 299fb8bd90fSChunyan Zhang return 400000; 300fb8bd90fSChunyan Zhang } 301fb8bd90fSChunyan Zhang 302fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 303fb8bd90fSChunyan Zhang unsigned int timing) 304fb8bd90fSChunyan Zhang { 3055f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 3065f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc; 3075f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 308fb8bd90fSChunyan Zhang u16 ctrl_2; 309fb8bd90fSChunyan Zhang 310fb8bd90fSChunyan Zhang if (timing == host->timing) 311fb8bd90fSChunyan Zhang return; 312fb8bd90fSChunyan Zhang 313fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 314fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 315fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 316fb8bd90fSChunyan Zhang switch (timing) { 317fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 318fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 319fb8bd90fSChunyan Zhang break; 320fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 321fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 322fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 323fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 324fb8bd90fSChunyan Zhang break; 325fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 326fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 327fb8bd90fSChunyan Zhang break; 328fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 329fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 330fb8bd90fSChunyan Zhang break; 331fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 332fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 333fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 334fb8bd90fSChunyan Zhang break; 335fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 336fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 337fb8bd90fSChunyan Zhang break; 338fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 339fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 340fb8bd90fSChunyan Zhang break; 341fb8bd90fSChunyan Zhang default: 342fb8bd90fSChunyan Zhang break; 343fb8bd90fSChunyan Zhang } 344fb8bd90fSChunyan Zhang 345fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 3465f2f4e0dSBaolin Wang 3475f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe) 3485f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY); 349fb8bd90fSChunyan Zhang } 350fb8bd90fSChunyan Zhang 351fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 352fb8bd90fSChunyan Zhang { 353fb8bd90fSChunyan Zhang int val; 354fb8bd90fSChunyan Zhang 355fb8bd90fSChunyan Zhang /* 356fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 357fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 358fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 359fb8bd90fSChunyan Zhang * not be cleared. 360fb8bd90fSChunyan Zhang */ 361fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 362fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 363fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 364fb8bd90fSChunyan Zhang /* wait for 10 us */ 365fb8bd90fSChunyan Zhang usleep_range(10, 20); 366fb8bd90fSChunyan Zhang 367fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 368fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 369fb8bd90fSChunyan Zhang usleep_range(300, 500); 370fb8bd90fSChunyan Zhang } 371fb8bd90fSChunyan Zhang 3727486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3737486831dSBaolin Wang { 3747486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 3757486831dSBaolin Wang return 1 << 31; 3767486831dSBaolin Wang } 3777486831dSBaolin Wang 3784eae8cbdSChunyan Zhang static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host) 3794eae8cbdSChunyan Zhang { 3804eae8cbdSChunyan Zhang return 0; 3814eae8cbdSChunyan Zhang } 3824eae8cbdSChunyan Zhang 383f4498549SBaolin Wang static void sdhci_sprd_request_done(struct sdhci_host *host, 384f4498549SBaolin Wang struct mmc_request *mrq) 385f4498549SBaolin Wang { 386f4498549SBaolin Wang /* Validate if the request was from software queue firstly. */ 387f4498549SBaolin Wang if (mmc_hsq_finalize_request(host->mmc, mrq)) 388f4498549SBaolin Wang return; 389f4498549SBaolin Wang 390f4498549SBaolin Wang mmc_request_done(host->mmc, mrq); 391f4498549SBaolin Wang } 392f4498549SBaolin Wang 393fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 394fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 395fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 396*96147082SKrzysztof Kozlowski .write_w = sdhci_sprd_writew, 397fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 398fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 399fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 400fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 401fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 402fb8bd90fSChunyan Zhang .reset = sdhci_reset, 403fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 404fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 4057486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 4064eae8cbdSChunyan Zhang .get_ro = sdhci_sprd_get_ro, 407f4498549SBaolin Wang .request_done = sdhci_sprd_request_done, 408fb8bd90fSChunyan Zhang }; 409fb8bd90fSChunyan Zhang 41061ab64e2SBaolin Wang static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc, 41161ab64e2SBaolin Wang struct mmc_request *mrq) 412fb8bd90fSChunyan Zhang { 413fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 414fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 415fb8bd90fSChunyan Zhang 416fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 417fb8bd90fSChunyan Zhang 418fb8bd90fSChunyan Zhang /* 419fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 420fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 421fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 422fb8bd90fSChunyan Zhang */ 423fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 424fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 425fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 426fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 42761ab64e2SBaolin Wang } 42861ab64e2SBaolin Wang 42961ab64e2SBaolin Wang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 43061ab64e2SBaolin Wang { 43161ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 432fb8bd90fSChunyan Zhang 433fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 434fb8bd90fSChunyan Zhang } 435fb8bd90fSChunyan Zhang 43661ab64e2SBaolin Wang static int sdhci_sprd_request_atomic(struct mmc_host *mmc, 43761ab64e2SBaolin Wang struct mmc_request *mrq) 43861ab64e2SBaolin Wang { 43961ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq); 44061ab64e2SBaolin Wang 44161ab64e2SBaolin Wang return sdhci_request_atomic(mmc, mrq); 44261ab64e2SBaolin Wang } 44361ab64e2SBaolin Wang 444eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) 445eef9e0a6SBaolin Wang { 44629ca763fSBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 44729ca763fSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 448eef9e0a6SBaolin Wang int ret; 449eef9e0a6SBaolin Wang 450eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) { 451eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios); 4529cbe0fc8SMarek Vasut if (ret < 0) { 453eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n", 454eef9e0a6SBaolin Wang mmc_hostname(mmc)); 455eef9e0a6SBaolin Wang return ret; 456eef9e0a6SBaolin Wang } 457eef9e0a6SBaolin Wang } 458eef9e0a6SBaolin Wang 45929ca763fSBaolin Wang if (IS_ERR(sprd_host->pinctrl)) 46029ca763fSBaolin Wang return 0; 46129ca763fSBaolin Wang 46229ca763fSBaolin Wang switch (ios->signal_voltage) { 46329ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_180: 46429ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 46529ca763fSBaolin Wang sprd_host->pins_uhs); 46629ca763fSBaolin Wang if (ret) { 46729ca763fSBaolin Wang pr_err("%s: failed to select uhs pin state\n", 46829ca763fSBaolin Wang mmc_hostname(mmc)); 46929ca763fSBaolin Wang return ret; 47029ca763fSBaolin Wang } 47129ca763fSBaolin Wang break; 47229ca763fSBaolin Wang 47329ca763fSBaolin Wang default: 474df561f66SGustavo A. R. Silva fallthrough; 47529ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_330: 47629ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl, 47729ca763fSBaolin Wang sprd_host->pins_default); 47829ca763fSBaolin Wang if (ret) { 47929ca763fSBaolin Wang pr_err("%s: failed to select default pin state\n", 48029ca763fSBaolin Wang mmc_hostname(mmc)); 48129ca763fSBaolin Wang return ret; 48229ca763fSBaolin Wang } 48329ca763fSBaolin Wang break; 48429ca763fSBaolin Wang } 48529ca763fSBaolin Wang 48629ca763fSBaolin Wang /* Wait for 300 ~ 500 us for pin state stable */ 48729ca763fSBaolin Wang usleep_range(300, 500); 48829ca763fSBaolin Wang sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 48929ca763fSBaolin Wang 490eef9e0a6SBaolin Wang return 0; 491eef9e0a6SBaolin Wang } 492eef9e0a6SBaolin Wang 493494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 494494c11e1SBaolin Wang struct mmc_ios *ios) 495494c11e1SBaolin Wang { 496494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 4975f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 4985f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 499494c11e1SBaolin Wang u16 ctrl_2; 500494c11e1SBaolin Wang 501494c11e1SBaolin Wang if (!ios->enhanced_strobe) 502494c11e1SBaolin Wang return; 503494c11e1SBaolin Wang 504494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 505494c11e1SBaolin Wang 506494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 507494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 508494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 509494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 510494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 511494c11e1SBaolin Wang 512494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 5135f2f4e0dSBaolin Wang 5145f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */ 5155f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1], 5165f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY); 5175f2f4e0dSBaolin Wang } 5185f2f4e0dSBaolin Wang 5195f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host, 5205f2f4e0dSBaolin Wang struct device_node *np) 5215f2f4e0dSBaolin Wang { 5225f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay; 5235f2f4e0dSBaolin Wang int ret, i, index; 5245f2f4e0dSBaolin Wang u32 val[4]; 5255f2f4e0dSBaolin Wang 5265f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) { 5275f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np, 5285f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4); 5295f2f4e0dSBaolin Wang if (ret) 5305f2f4e0dSBaolin Wang continue; 5315f2f4e0dSBaolin Wang 5325f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing; 5335f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24); 5345f2f4e0dSBaolin Wang } 535494c11e1SBaolin Wang } 536494c11e1SBaolin Wang 537fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 5384324e54bSChunyan Zhang .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | 5392f765c17SChunyan Zhang SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | 5402f765c17SChunyan Zhang SDHCI_QUIRK_MISSING_CAPS, 541fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 5426a526f66SChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT | 5436a526f66SChunyan Zhang SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 544fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 545fb8bd90fSChunyan Zhang }; 546fb8bd90fSChunyan Zhang 547fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 548fb8bd90fSChunyan Zhang { 549fb8bd90fSChunyan Zhang struct sdhci_host *host; 550fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 551f4498549SBaolin Wang struct mmc_hsq *hsq; 552fb8bd90fSChunyan Zhang struct clk *clk; 553fb8bd90fSChunyan Zhang int ret = 0; 554fb8bd90fSChunyan Zhang 555fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 556fb8bd90fSChunyan Zhang if (IS_ERR(host)) 557fb8bd90fSChunyan Zhang return PTR_ERR(host); 558fb8bd90fSChunyan Zhang 559fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 560fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 561fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 562494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 563494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 564eef9e0a6SBaolin Wang /* 565eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage 566eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator 567eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control 568eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage. 569eef9e0a6SBaolin Wang */ 570eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch = 571eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch; 572fb8bd90fSChunyan Zhang 573fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 574a049b5aeSUlf Hansson MMC_CAP_WAIT_WHILE_BUSY; 575a049b5aeSUlf Hansson 576fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 577fb8bd90fSChunyan Zhang if (ret) 578fb8bd90fSChunyan Zhang goto pltfm_free; 579fb8bd90fSChunyan Zhang 58061ab64e2SBaolin Wang if (!mmc_card_is_removable(host->mmc)) 58161ab64e2SBaolin Wang host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic; 58261ab64e2SBaolin Wang else 58361ab64e2SBaolin Wang host->always_defer_done = true; 58461ab64e2SBaolin Wang 585fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 5865f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node); 587fb8bd90fSChunyan Zhang 58829ca763fSBaolin Wang sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev); 58929ca763fSBaolin Wang if (!IS_ERR(sprd_host->pinctrl)) { 59029ca763fSBaolin Wang sprd_host->pins_uhs = 59129ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs"); 59229ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_uhs)) { 59329ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_uhs); 59429ca763fSBaolin Wang goto pltfm_free; 59529ca763fSBaolin Wang } 59629ca763fSBaolin Wang 59729ca763fSBaolin Wang sprd_host->pins_default = 59829ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "default"); 59929ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_default)) { 60029ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_default); 60129ca763fSBaolin Wang goto pltfm_free; 60229ca763fSBaolin Wang } 60329ca763fSBaolin Wang } 60429ca763fSBaolin Wang 605fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 606fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 607fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 608fb8bd90fSChunyan Zhang goto pltfm_free; 609fb8bd90fSChunyan Zhang } 610fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 611fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 612fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 613fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 614fb8bd90fSChunyan Zhang 615fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 616fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 617fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 618fb8bd90fSChunyan Zhang goto pltfm_free; 619fb8bd90fSChunyan Zhang } 620fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 621fb8bd90fSChunyan Zhang 622ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 623ebd88a38SBaolin Wang if (!IS_ERR(clk)) 624ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 625ebd88a38SBaolin Wang 626fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 627fb8bd90fSChunyan Zhang if (ret) 628fb8bd90fSChunyan Zhang goto pltfm_free; 629fb8bd90fSChunyan Zhang 6301d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 631fb8bd90fSChunyan Zhang if (ret) 632fb8bd90fSChunyan Zhang goto clk_disable; 633fb8bd90fSChunyan Zhang 634ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 635ebd88a38SBaolin Wang if (ret) 636ebd88a38SBaolin Wang goto clk_disable2; 637ebd88a38SBaolin Wang 638fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 639fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 640fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 641fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 642fb8bd90fSChunyan Zhang 643fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 644fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 645fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 646fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 647fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 648fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 649fb8bd90fSChunyan Zhang 650fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 651fb8bd90fSChunyan Zhang 6522f765c17SChunyan Zhang /* 6532f765c17SChunyan Zhang * Supply the existing CAPS, but clear the UHS-I modes. This 6542f765c17SChunyan Zhang * will allow these modes to be specified only by device 6552f765c17SChunyan Zhang * tree properties through mmc_of_parse(). 6562f765c17SChunyan Zhang */ 6572f765c17SChunyan Zhang host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); 6582f765c17SChunyan Zhang host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); 6592f765c17SChunyan Zhang host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 6602f765c17SChunyan Zhang SDHCI_SUPPORT_DDR50); 6612f765c17SChunyan Zhang 662fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 663fb8bd90fSChunyan Zhang if (ret) 664fb8bd90fSChunyan Zhang goto pm_runtime_disable; 665fb8bd90fSChunyan Zhang 666fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 667fb8bd90fSChunyan Zhang 668f4498549SBaolin Wang hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL); 669f4498549SBaolin Wang if (!hsq) { 670f4498549SBaolin Wang ret = -ENOMEM; 671f4498549SBaolin Wang goto err_cleanup_host; 672f4498549SBaolin Wang } 673f4498549SBaolin Wang 674f4498549SBaolin Wang ret = mmc_hsq_init(hsq, host->mmc); 675f4498549SBaolin Wang if (ret) 676f4498549SBaolin Wang goto err_cleanup_host; 677f4498549SBaolin Wang 678fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 679fb8bd90fSChunyan Zhang if (ret) 680fb8bd90fSChunyan Zhang goto err_cleanup_host; 681fb8bd90fSChunyan Zhang 682fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 683fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 684fb8bd90fSChunyan Zhang 685fb8bd90fSChunyan Zhang return 0; 686fb8bd90fSChunyan Zhang 687fb8bd90fSChunyan Zhang err_cleanup_host: 688fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 689fb8bd90fSChunyan Zhang 690fb8bd90fSChunyan Zhang pm_runtime_disable: 691fc62113bSBaolin Wang pm_runtime_put_noidle(&pdev->dev); 692fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 693fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 694fb8bd90fSChunyan Zhang 695ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 696ebd88a38SBaolin Wang 697ebd88a38SBaolin Wang clk_disable2: 698fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 699fb8bd90fSChunyan Zhang 700fb8bd90fSChunyan Zhang clk_disable: 701fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 702fb8bd90fSChunyan Zhang 703fb8bd90fSChunyan Zhang pltfm_free: 704fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 705fb8bd90fSChunyan Zhang return ret; 706fb8bd90fSChunyan Zhang } 707fb8bd90fSChunyan Zhang 708fb8bd90fSChunyan Zhang static int sdhci_sprd_remove(struct platform_device *pdev) 709fb8bd90fSChunyan Zhang { 710fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 711fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 712fb8bd90fSChunyan Zhang 713c9c256a8SChristophe JAILLET sdhci_remove_host(host, 0); 714c9c256a8SChristophe JAILLET 715fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 716fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 717ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 718fb8bd90fSChunyan Zhang 719c9c256a8SChristophe JAILLET sdhci_pltfm_free(pdev); 720fb8bd90fSChunyan Zhang 721fb8bd90fSChunyan Zhang return 0; 722fb8bd90fSChunyan Zhang } 723fb8bd90fSChunyan Zhang 724fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 725fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 726fb8bd90fSChunyan Zhang { } 727fb8bd90fSChunyan Zhang }; 728fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 729fb8bd90fSChunyan Zhang 730fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 731fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 732fb8bd90fSChunyan Zhang { 733fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 734fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 735fb8bd90fSChunyan Zhang 736f4498549SBaolin Wang mmc_hsq_suspend(host->mmc); 737fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 738fb8bd90fSChunyan Zhang 739fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 740fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 741ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 742fb8bd90fSChunyan Zhang 743fb8bd90fSChunyan Zhang return 0; 744fb8bd90fSChunyan Zhang } 745fb8bd90fSChunyan Zhang 746fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 747fb8bd90fSChunyan Zhang { 748fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 749fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 750fb8bd90fSChunyan Zhang int ret; 751fb8bd90fSChunyan Zhang 752ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 753fb8bd90fSChunyan Zhang if (ret) 754fb8bd90fSChunyan Zhang return ret; 755fb8bd90fSChunyan Zhang 756ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 757ebd88a38SBaolin Wang if (ret) 758ebd88a38SBaolin Wang goto clk_2x_disable; 759ebd88a38SBaolin Wang 760fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 761ebd88a38SBaolin Wang if (ret) 762ebd88a38SBaolin Wang goto clk_disable; 763fb8bd90fSChunyan Zhang 764c6303c5dSBaolin Wang sdhci_runtime_resume_host(host, 1); 765f4498549SBaolin Wang mmc_hsq_resume(host->mmc); 766f4498549SBaolin Wang 767fb8bd90fSChunyan Zhang return 0; 768ebd88a38SBaolin Wang 769ebd88a38SBaolin Wang clk_disable: 770ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 771ebd88a38SBaolin Wang 772ebd88a38SBaolin Wang clk_2x_disable: 773ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 774ebd88a38SBaolin Wang 775ebd88a38SBaolin Wang return ret; 776fb8bd90fSChunyan Zhang } 777fb8bd90fSChunyan Zhang #endif 778fb8bd90fSChunyan Zhang 779fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 780fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 781fb8bd90fSChunyan Zhang pm_runtime_force_resume) 782fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 783fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 784fb8bd90fSChunyan Zhang }; 785fb8bd90fSChunyan Zhang 786fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 787fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 788fb8bd90fSChunyan Zhang .remove = sdhci_sprd_remove, 789fb8bd90fSChunyan Zhang .driver = { 790fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 791d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 792a96e6523SKrzysztof Kozlowski .of_match_table = sdhci_sprd_of_match, 793fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 794fb8bd90fSChunyan Zhang }, 795fb8bd90fSChunyan Zhang }; 796fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 797fb8bd90fSChunyan Zhang 798fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 799fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 800fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 801