1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 11fb8bd90fSChunyan Zhang #include <linux/module.h> 12fb8bd90fSChunyan Zhang #include <linux/of.h> 13fb8bd90fSChunyan Zhang #include <linux/of_device.h> 14fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 15fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 16fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 17fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 18fb8bd90fSChunyan Zhang #include <linux/slab.h> 19fb8bd90fSChunyan Zhang 20fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 21fb8bd90fSChunyan Zhang 22fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 23fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24fb8bd90fSChunyan Zhang 2587a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200 2687a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27)) 2787a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21) 2887a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16) 2987a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00 3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3 3187a395c2SBaolin Wang 32fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 33fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 34fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 35fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 36fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 37fb8bd90fSChunyan Zhang 38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 39fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 41fb8bd90fSChunyan Zhang 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 43fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 44fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 45fb8bd90fSChunyan Zhang 46fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 47fb8bd90fSChunyan Zhang 48fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 49fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 50fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 51494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007 52fb8bd90fSChunyan Zhang 53fb8bd90fSChunyan Zhang /* 54fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 55fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 56fb8bd90fSChunyan Zhang * if this bit is cleared. 57fb8bd90fSChunyan Zhang * 1 : normal work 58fb8bd90fSChunyan Zhang * 0 : hardware reset 59fb8bd90fSChunyan Zhang */ 60fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 61fb8bd90fSChunyan Zhang 62fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 63fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 64fb8bd90fSChunyan Zhang 65fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 6687a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000 67fb8bd90fSChunyan Zhang 68fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 69fb8bd90fSChunyan Zhang u32 version; 70fb8bd90fSChunyan Zhang struct clk *clk_sdio; 71fb8bd90fSChunyan Zhang struct clk *clk_enable; 72ebd88a38SBaolin Wang struct clk *clk_2x_enable; 73fb8bd90fSChunyan Zhang u32 base_rate; 74fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 75fb8bd90fSChunyan Zhang }; 76fb8bd90fSChunyan Zhang 77fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 78fb8bd90fSChunyan Zhang 79fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 80fb8bd90fSChunyan Zhang { 81fb8bd90fSChunyan Zhang u16 val; 82fb8bd90fSChunyan Zhang 83fb8bd90fSChunyan Zhang /* set dll backup mode */ 84fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 85fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 86fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 87fb8bd90fSChunyan Zhang } 88fb8bd90fSChunyan Zhang 89fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 90fb8bd90fSChunyan Zhang { 91fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 92fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 93fb8bd90fSChunyan Zhang 94fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 95fb8bd90fSChunyan Zhang } 96fb8bd90fSChunyan Zhang 97fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 98fb8bd90fSChunyan Zhang { 99fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 100fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 101fb8bd90fSChunyan Zhang return; 102fb8bd90fSChunyan Zhang 103fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 104fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 105fb8bd90fSChunyan Zhang 106fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 107fb8bd90fSChunyan Zhang } 108fb8bd90fSChunyan Zhang 109fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 110fb8bd90fSChunyan Zhang { 111fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 112fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 113fb8bd90fSChunyan Zhang return; 114fb8bd90fSChunyan Zhang 115fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 116fb8bd90fSChunyan Zhang } 117fb8bd90fSChunyan Zhang 118fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 119fb8bd90fSChunyan Zhang { 120fb8bd90fSChunyan Zhang /* 121fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 122fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 123fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 124fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 125fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 126fb8bd90fSChunyan Zhang * around it. 127fb8bd90fSChunyan Zhang */ 128fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 129fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 130fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 131fb8bd90fSChunyan Zhang } 132fb8bd90fSChunyan Zhang 133fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 134fb8bd90fSChunyan Zhang } 135fb8bd90fSChunyan Zhang 136fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 137fb8bd90fSChunyan Zhang { 138fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 139fb8bd90fSChunyan Zhang 140fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 141fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 142fb8bd90fSChunyan Zhang } 143fb8bd90fSChunyan Zhang 144494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host) 145494c11e1SBaolin Wang { 146494c11e1SBaolin Wang u16 ctrl; 147494c11e1SBaolin Wang 148494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 149494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN; 150494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 151494c11e1SBaolin Wang } 152494c11e1SBaolin Wang 153fb8bd90fSChunyan Zhang static inline void 154fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 155fb8bd90fSChunyan Zhang { 156fb8bd90fSChunyan Zhang u32 dll_dly_offset; 157fb8bd90fSChunyan Zhang 158fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 159fb8bd90fSChunyan Zhang if (en) 160fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 161fb8bd90fSChunyan Zhang else 162fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 163fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 164fb8bd90fSChunyan Zhang } 165fb8bd90fSChunyan Zhang 166fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 167fb8bd90fSChunyan Zhang { 168fb8bd90fSChunyan Zhang u32 div; 169fb8bd90fSChunyan Zhang 170fb8bd90fSChunyan Zhang /* select 2x clock source */ 171fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 172fb8bd90fSChunyan Zhang return 0; 173fb8bd90fSChunyan Zhang 174fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 175fb8bd90fSChunyan Zhang 176fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 177fb8bd90fSChunyan Zhang div++; 178fb8bd90fSChunyan Zhang 179fb8bd90fSChunyan Zhang if (div > SDHCI_SPRD_CLK_MAX_DIV) 180fb8bd90fSChunyan Zhang div = SDHCI_SPRD_CLK_MAX_DIV; 181fb8bd90fSChunyan Zhang 182fb8bd90fSChunyan Zhang if (div % 2) 183fb8bd90fSChunyan Zhang div = (div + 1) / 2; 184fb8bd90fSChunyan Zhang else 185fb8bd90fSChunyan Zhang div = div / 2; 186fb8bd90fSChunyan Zhang 187fb8bd90fSChunyan Zhang return div; 188fb8bd90fSChunyan Zhang } 189fb8bd90fSChunyan Zhang 190fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 191fb8bd90fSChunyan Zhang unsigned int clk) 192fb8bd90fSChunyan Zhang { 193fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 194fb8bd90fSChunyan Zhang u32 div, val, mask; 195fb8bd90fSChunyan Zhang 196fb8bd90fSChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 197fb8bd90fSChunyan Zhang 198fb8bd90fSChunyan Zhang clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 199fb8bd90fSChunyan Zhang sdhci_enable_clk(host, clk); 200fb8bd90fSChunyan Zhang 201fb8bd90fSChunyan Zhang /* enable auto gate sdhc_enable_auto_gate */ 202fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 203fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 204fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 205fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 206fb8bd90fSChunyan Zhang val |= mask; 207fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 208fb8bd90fSChunyan Zhang } 209fb8bd90fSChunyan Zhang } 210fb8bd90fSChunyan Zhang 21187a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host) 21287a395c2SBaolin Wang { 21387a395c2SBaolin Wang u32 tmp; 21487a395c2SBaolin Wang 21587a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 21687a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN); 21787a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 21887a395c2SBaolin Wang /* wait 1ms */ 21987a395c2SBaolin Wang usleep_range(1000, 1250); 22087a395c2SBaolin Wang 22187a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 22287a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE | 22387a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL; 22487a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 22587a395c2SBaolin Wang /* wait 1ms */ 22687a395c2SBaolin Wang usleep_range(1000, 1250); 22787a395c2SBaolin Wang 22887a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); 22987a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN; 23087a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG); 23187a395c2SBaolin Wang /* wait 1ms */ 23287a395c2SBaolin Wang usleep_range(1000, 1250); 23387a395c2SBaolin Wang } 23487a395c2SBaolin Wang 235fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 236fb8bd90fSChunyan Zhang { 23787a395c2SBaolin Wang bool en = false, clk_changed = false; 238fb8bd90fSChunyan Zhang 239fb8bd90fSChunyan Zhang if (clock == 0) { 240fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 241fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 242fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 243fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 244fb8bd90fSChunyan Zhang 245fb8bd90fSChunyan Zhang if (clock <= 400000) 246fb8bd90fSChunyan Zhang en = true; 247fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 248fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 24987a395c2SBaolin Wang clk_changed = true; 250fb8bd90fSChunyan Zhang } else { 251fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 252fb8bd90fSChunyan Zhang } 25387a395c2SBaolin Wang 25487a395c2SBaolin Wang /* 25587a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed 25687a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which 25787a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more 25887a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock. 25987a395c2SBaolin Wang */ 26087a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK) 26187a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host); 262fb8bd90fSChunyan Zhang } 263fb8bd90fSChunyan Zhang 264fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 265fb8bd90fSChunyan Zhang { 266fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 267fb8bd90fSChunyan Zhang 268fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 269fb8bd90fSChunyan Zhang } 270fb8bd90fSChunyan Zhang 271fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 272fb8bd90fSChunyan Zhang { 273fb8bd90fSChunyan Zhang return 400000; 274fb8bd90fSChunyan Zhang } 275fb8bd90fSChunyan Zhang 276fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 277fb8bd90fSChunyan Zhang unsigned int timing) 278fb8bd90fSChunyan Zhang { 279fb8bd90fSChunyan Zhang u16 ctrl_2; 280fb8bd90fSChunyan Zhang 281fb8bd90fSChunyan Zhang if (timing == host->timing) 282fb8bd90fSChunyan Zhang return; 283fb8bd90fSChunyan Zhang 284fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 285fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 286fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 287fb8bd90fSChunyan Zhang switch (timing) { 288fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 289fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 290fb8bd90fSChunyan Zhang break; 291fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 292fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 293fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 294fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 295fb8bd90fSChunyan Zhang break; 296fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 297fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 298fb8bd90fSChunyan Zhang break; 299fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 300fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 301fb8bd90fSChunyan Zhang break; 302fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 303fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 304fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 305fb8bd90fSChunyan Zhang break; 306fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 307fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 308fb8bd90fSChunyan Zhang break; 309fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 310fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 311fb8bd90fSChunyan Zhang break; 312fb8bd90fSChunyan Zhang default: 313fb8bd90fSChunyan Zhang break; 314fb8bd90fSChunyan Zhang } 315fb8bd90fSChunyan Zhang 316fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 317fb8bd90fSChunyan Zhang } 318fb8bd90fSChunyan Zhang 319fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 320fb8bd90fSChunyan Zhang { 321fb8bd90fSChunyan Zhang int val; 322fb8bd90fSChunyan Zhang 323fb8bd90fSChunyan Zhang /* 324fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 325fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 326fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 327fb8bd90fSChunyan Zhang * not be cleared. 328fb8bd90fSChunyan Zhang */ 329fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 330fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 331fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 332fb8bd90fSChunyan Zhang /* wait for 10 us */ 333fb8bd90fSChunyan Zhang usleep_range(10, 20); 334fb8bd90fSChunyan Zhang 335fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 336fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 337fb8bd90fSChunyan Zhang usleep_range(300, 500); 338fb8bd90fSChunyan Zhang } 339fb8bd90fSChunyan Zhang 3407486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 3417486831dSBaolin Wang { 3427486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 3437486831dSBaolin Wang return 1 << 31; 3447486831dSBaolin Wang } 3457486831dSBaolin Wang 346fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 347fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 348fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 349fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 350fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 351fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 352fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 353fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 354fb8bd90fSChunyan Zhang .reset = sdhci_reset, 355fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 356fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 3577486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 358fb8bd90fSChunyan Zhang }; 359fb8bd90fSChunyan Zhang 360fb8bd90fSChunyan Zhang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 361fb8bd90fSChunyan Zhang { 362fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 363fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 364fb8bd90fSChunyan Zhang 365fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 366fb8bd90fSChunyan Zhang 367fb8bd90fSChunyan Zhang /* 368fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 369fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 370fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 371fb8bd90fSChunyan Zhang */ 372fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 373fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 374fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 375fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 376fb8bd90fSChunyan Zhang 377fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 378fb8bd90fSChunyan Zhang } 379fb8bd90fSChunyan Zhang 380494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc, 381494c11e1SBaolin Wang struct mmc_ios *ios) 382494c11e1SBaolin Wang { 383494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc); 384494c11e1SBaolin Wang u16 ctrl_2; 385494c11e1SBaolin Wang 386494c11e1SBaolin Wang if (!ios->enhanced_strobe) 387494c11e1SBaolin Wang return; 388494c11e1SBaolin Wang 389494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host); 390494c11e1SBaolin Wang 391494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */ 392494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 393494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 394494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES; 395494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 396494c11e1SBaolin Wang 397494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host); 398494c11e1SBaolin Wang } 399494c11e1SBaolin Wang 400fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 401fb8bd90fSChunyan Zhang .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 402fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 403fb8bd90fSChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 404fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 405fb8bd90fSChunyan Zhang }; 406fb8bd90fSChunyan Zhang 407fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 408fb8bd90fSChunyan Zhang { 409fb8bd90fSChunyan Zhang struct sdhci_host *host; 410fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 411fb8bd90fSChunyan Zhang struct clk *clk; 412fb8bd90fSChunyan Zhang int ret = 0; 413fb8bd90fSChunyan Zhang 414fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 415fb8bd90fSChunyan Zhang if (IS_ERR(host)) 416fb8bd90fSChunyan Zhang return PTR_ERR(host); 417fb8bd90fSChunyan Zhang 418fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 419fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 420fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 421494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe = 422494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe; 423fb8bd90fSChunyan Zhang 424fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 425fb8bd90fSChunyan Zhang MMC_CAP_ERASE | MMC_CAP_CMD23; 426fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 427fb8bd90fSChunyan Zhang if (ret) 428fb8bd90fSChunyan Zhang goto pltfm_free; 429fb8bd90fSChunyan Zhang 430fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 431fb8bd90fSChunyan Zhang 432fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 433fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 434fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 435fb8bd90fSChunyan Zhang goto pltfm_free; 436fb8bd90fSChunyan Zhang } 437fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 438fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 439fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 440fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 441fb8bd90fSChunyan Zhang 442fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 443fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 444fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 445fb8bd90fSChunyan Zhang goto pltfm_free; 446fb8bd90fSChunyan Zhang } 447fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 448fb8bd90fSChunyan Zhang 449ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 450ebd88a38SBaolin Wang if (!IS_ERR(clk)) 451ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 452ebd88a38SBaolin Wang 453fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 454fb8bd90fSChunyan Zhang if (ret) 455fb8bd90fSChunyan Zhang goto pltfm_free; 456fb8bd90fSChunyan Zhang 4571d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 458fb8bd90fSChunyan Zhang if (ret) 459fb8bd90fSChunyan Zhang goto clk_disable; 460fb8bd90fSChunyan Zhang 461ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 462ebd88a38SBaolin Wang if (ret) 463ebd88a38SBaolin Wang goto clk_disable2; 464ebd88a38SBaolin Wang 465fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 466fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 467fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 468fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 469fb8bd90fSChunyan Zhang 470fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 471fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 472fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 473fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 474fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 475fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 476fb8bd90fSChunyan Zhang 477fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 478fb8bd90fSChunyan Zhang 479fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 480fb8bd90fSChunyan Zhang if (ret) 481fb8bd90fSChunyan Zhang goto pm_runtime_disable; 482fb8bd90fSChunyan Zhang 483fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 484fb8bd90fSChunyan Zhang 485fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 486fb8bd90fSChunyan Zhang if (ret) 487fb8bd90fSChunyan Zhang goto err_cleanup_host; 488fb8bd90fSChunyan Zhang 489fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 490fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 491fb8bd90fSChunyan Zhang 492fb8bd90fSChunyan Zhang return 0; 493fb8bd90fSChunyan Zhang 494fb8bd90fSChunyan Zhang err_cleanup_host: 495fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 496fb8bd90fSChunyan Zhang 497fb8bd90fSChunyan Zhang pm_runtime_disable: 498fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 499fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 500fb8bd90fSChunyan Zhang 501ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 502ebd88a38SBaolin Wang 503ebd88a38SBaolin Wang clk_disable2: 504fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 505fb8bd90fSChunyan Zhang 506fb8bd90fSChunyan Zhang clk_disable: 507fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 508fb8bd90fSChunyan Zhang 509fb8bd90fSChunyan Zhang pltfm_free: 510fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 511fb8bd90fSChunyan Zhang return ret; 512fb8bd90fSChunyan Zhang } 513fb8bd90fSChunyan Zhang 514fb8bd90fSChunyan Zhang static int sdhci_sprd_remove(struct platform_device *pdev) 515fb8bd90fSChunyan Zhang { 516fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 517fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 518fb8bd90fSChunyan Zhang struct mmc_host *mmc = host->mmc; 519fb8bd90fSChunyan Zhang 520fb8bd90fSChunyan Zhang mmc_remove_host(mmc); 521fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 522fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 523ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 524fb8bd90fSChunyan Zhang 525fb8bd90fSChunyan Zhang mmc_free_host(mmc); 526fb8bd90fSChunyan Zhang 527fb8bd90fSChunyan Zhang return 0; 528fb8bd90fSChunyan Zhang } 529fb8bd90fSChunyan Zhang 530fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 531fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 532fb8bd90fSChunyan Zhang { } 533fb8bd90fSChunyan Zhang }; 534fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 535fb8bd90fSChunyan Zhang 536fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 537fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 538fb8bd90fSChunyan Zhang { 539fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 540fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 541fb8bd90fSChunyan Zhang 542fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 543fb8bd90fSChunyan Zhang 544fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 545fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 546ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 547fb8bd90fSChunyan Zhang 548fb8bd90fSChunyan Zhang return 0; 549fb8bd90fSChunyan Zhang } 550fb8bd90fSChunyan Zhang 551fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 552fb8bd90fSChunyan Zhang { 553fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 554fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 555fb8bd90fSChunyan Zhang int ret; 556fb8bd90fSChunyan Zhang 557ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 558fb8bd90fSChunyan Zhang if (ret) 559fb8bd90fSChunyan Zhang return ret; 560fb8bd90fSChunyan Zhang 561ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 562ebd88a38SBaolin Wang if (ret) 563ebd88a38SBaolin Wang goto clk_2x_disable; 564ebd88a38SBaolin Wang 565fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 566ebd88a38SBaolin Wang if (ret) 567ebd88a38SBaolin Wang goto clk_disable; 568fb8bd90fSChunyan Zhang 569fb8bd90fSChunyan Zhang sdhci_runtime_resume_host(host); 570fb8bd90fSChunyan Zhang return 0; 571ebd88a38SBaolin Wang 572ebd88a38SBaolin Wang clk_disable: 573ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 574ebd88a38SBaolin Wang 575ebd88a38SBaolin Wang clk_2x_disable: 576ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 577ebd88a38SBaolin Wang 578ebd88a38SBaolin Wang return ret; 579fb8bd90fSChunyan Zhang } 580fb8bd90fSChunyan Zhang #endif 581fb8bd90fSChunyan Zhang 582fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 583fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 584fb8bd90fSChunyan Zhang pm_runtime_force_resume) 585fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 586fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 587fb8bd90fSChunyan Zhang }; 588fb8bd90fSChunyan Zhang 589fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 590fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 591fb8bd90fSChunyan Zhang .remove = sdhci_sprd_remove, 592fb8bd90fSChunyan Zhang .driver = { 593fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 594fb8bd90fSChunyan Zhang .of_match_table = of_match_ptr(sdhci_sprd_of_match), 595fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 596fb8bd90fSChunyan Zhang }, 597fb8bd90fSChunyan Zhang }; 598fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 599fb8bd90fSChunyan Zhang 600fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 601fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 602fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 603