1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0 2fb8bd90fSChunyan Zhang // 3fb8bd90fSChunyan Zhang // Secure Digital Host Controller 4fb8bd90fSChunyan Zhang // 5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc. 6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com> 7fb8bd90fSChunyan Zhang 8fb8bd90fSChunyan Zhang #include <linux/delay.h> 9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h> 10fb8bd90fSChunyan Zhang #include <linux/highmem.h> 11fb8bd90fSChunyan Zhang #include <linux/module.h> 12fb8bd90fSChunyan Zhang #include <linux/of.h> 13fb8bd90fSChunyan Zhang #include <linux/of_device.h> 14fb8bd90fSChunyan Zhang #include <linux/of_gpio.h> 15fb8bd90fSChunyan Zhang #include <linux/platform_device.h> 16fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h> 17fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h> 18fb8bd90fSChunyan Zhang #include <linux/slab.h> 19fb8bd90fSChunyan Zhang 20fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h" 21fb8bd90fSChunyan Zhang 22fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */ 23fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16) 24fb8bd90fSChunyan Zhang 25fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208 26fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5) 27fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13) 28fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21) 29fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29) 30fb8bd90fSChunyan Zhang 31fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250 32fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25) 33fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24) 34fb8bd90fSChunyan Zhang 35fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C 36fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0) 37fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1) 38fb8bd90fSChunyan Zhang 39fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B 40fb8bd90fSChunyan Zhang 41fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */ 42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005 43fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006 44fb8bd90fSChunyan Zhang 45fb8bd90fSChunyan Zhang /* 46fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is 47fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work 48fb8bd90fSChunyan Zhang * if this bit is cleared. 49fb8bd90fSChunyan Zhang * 1 : normal work 50fb8bd90fSChunyan Zhang * 0 : hardware reset 51fb8bd90fSChunyan Zhang */ 52fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3) 53fb8bd90fSChunyan Zhang 54fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF 55fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023 56fb8bd90fSChunyan Zhang 57fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000 58fb8bd90fSChunyan Zhang 59fb8bd90fSChunyan Zhang struct sdhci_sprd_host { 60fb8bd90fSChunyan Zhang u32 version; 61fb8bd90fSChunyan Zhang struct clk *clk_sdio; 62fb8bd90fSChunyan Zhang struct clk *clk_enable; 63ebd88a38SBaolin Wang struct clk *clk_2x_enable; 64fb8bd90fSChunyan Zhang u32 base_rate; 65fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */ 66fb8bd90fSChunyan Zhang }; 67fb8bd90fSChunyan Zhang 68fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host)) 69fb8bd90fSChunyan Zhang 70fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host) 71fb8bd90fSChunyan Zhang { 72fb8bd90fSChunyan Zhang u16 val; 73fb8bd90fSChunyan Zhang 74fb8bd90fSChunyan Zhang /* set dll backup mode */ 75fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); 76fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL; 77fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE); 78fb8bd90fSChunyan Zhang } 79fb8bd90fSChunyan Zhang 80fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg) 81fb8bd90fSChunyan Zhang { 82fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 83fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR; 84fb8bd90fSChunyan Zhang 85fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg); 86fb8bd90fSChunyan Zhang } 87fb8bd90fSChunyan Zhang 88fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg) 89fb8bd90fSChunyan Zhang { 90fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */ 91fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT)) 92fb8bd90fSChunyan Zhang return; 93fb8bd90fSChunyan Zhang 94fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE)) 95fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK; 96fb8bd90fSChunyan Zhang 97fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg); 98fb8bd90fSChunyan Zhang } 99fb8bd90fSChunyan Zhang 100fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg) 101fb8bd90fSChunyan Zhang { 102fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */ 103fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT)) 104fb8bd90fSChunyan Zhang return; 105fb8bd90fSChunyan Zhang 106fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg); 107fb8bd90fSChunyan Zhang } 108fb8bd90fSChunyan Zhang 109fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg) 110fb8bd90fSChunyan Zhang { 111fb8bd90fSChunyan Zhang /* 112fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the 113fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly 114fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which 115fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing 116fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work 117fb8bd90fSChunyan Zhang * around it. 118fb8bd90fSChunyan Zhang */ 119fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) { 120fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD) 121fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 122fb8bd90fSChunyan Zhang } 123fb8bd90fSChunyan Zhang 124fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg); 125fb8bd90fSChunyan Zhang } 126fb8bd90fSChunyan Zhang 127fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host) 128fb8bd90fSChunyan Zhang { 129fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 130fb8bd90fSChunyan Zhang 131fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN; 132fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 133fb8bd90fSChunyan Zhang } 134fb8bd90fSChunyan Zhang 135fb8bd90fSChunyan Zhang static inline void 136fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en) 137fb8bd90fSChunyan Zhang { 138fb8bd90fSChunyan Zhang u32 dll_dly_offset; 139fb8bd90fSChunyan Zhang 140fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 141fb8bd90fSChunyan Zhang if (en) 142fb8bd90fSChunyan Zhang dll_dly_offset |= mask; 143fb8bd90fSChunyan Zhang else 144fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask; 145fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); 146fb8bd90fSChunyan Zhang } 147fb8bd90fSChunyan Zhang 148fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) 149fb8bd90fSChunyan Zhang { 150fb8bd90fSChunyan Zhang u32 div; 151fb8bd90fSChunyan Zhang 152fb8bd90fSChunyan Zhang /* select 2x clock source */ 153fb8bd90fSChunyan Zhang if (base_clk <= clk * 2) 154fb8bd90fSChunyan Zhang return 0; 155fb8bd90fSChunyan Zhang 156fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2)); 157fb8bd90fSChunyan Zhang 158fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2)) 159fb8bd90fSChunyan Zhang div++; 160fb8bd90fSChunyan Zhang 161fb8bd90fSChunyan Zhang if (div > SDHCI_SPRD_CLK_MAX_DIV) 162fb8bd90fSChunyan Zhang div = SDHCI_SPRD_CLK_MAX_DIV; 163fb8bd90fSChunyan Zhang 164fb8bd90fSChunyan Zhang if (div % 2) 165fb8bd90fSChunyan Zhang div = (div + 1) / 2; 166fb8bd90fSChunyan Zhang else 167fb8bd90fSChunyan Zhang div = div / 2; 168fb8bd90fSChunyan Zhang 169fb8bd90fSChunyan Zhang return div; 170fb8bd90fSChunyan Zhang } 171fb8bd90fSChunyan Zhang 172fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host, 173fb8bd90fSChunyan Zhang unsigned int clk) 174fb8bd90fSChunyan Zhang { 175fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 176fb8bd90fSChunyan Zhang u32 div, val, mask; 177fb8bd90fSChunyan Zhang 178fb8bd90fSChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk); 179fb8bd90fSChunyan Zhang 180fb8bd90fSChunyan Zhang clk |= ((div & 0x300) >> 2) | ((div & 0xFF) << 8); 181fb8bd90fSChunyan Zhang sdhci_enable_clk(host, clk); 182fb8bd90fSChunyan Zhang 183fb8bd90fSChunyan Zhang /* enable auto gate sdhc_enable_auto_gate */ 184fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); 185fb8bd90fSChunyan Zhang mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | 186fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN; 187fb8bd90fSChunyan Zhang if (mask != (val & mask)) { 188fb8bd90fSChunyan Zhang val |= mask; 189fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI); 190fb8bd90fSChunyan Zhang } 191fb8bd90fSChunyan Zhang } 192fb8bd90fSChunyan Zhang 193fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock) 194fb8bd90fSChunyan Zhang { 195fb8bd90fSChunyan Zhang bool en = false; 196fb8bd90fSChunyan Zhang 197fb8bd90fSChunyan Zhang if (clock == 0) { 198fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 199fb8bd90fSChunyan Zhang } else if (clock != host->clock) { 200fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host); 201fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 202fb8bd90fSChunyan Zhang 203fb8bd90fSChunyan Zhang if (clock <= 400000) 204fb8bd90fSChunyan Zhang en = true; 205fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV | 206fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en); 207fb8bd90fSChunyan Zhang } else { 208fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock); 209fb8bd90fSChunyan Zhang } 210fb8bd90fSChunyan Zhang } 211fb8bd90fSChunyan Zhang 212fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host) 213fb8bd90fSChunyan Zhang { 214fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 215fb8bd90fSChunyan Zhang 216fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX); 217fb8bd90fSChunyan Zhang } 218fb8bd90fSChunyan Zhang 219fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host) 220fb8bd90fSChunyan Zhang { 221fb8bd90fSChunyan Zhang return 400000; 222fb8bd90fSChunyan Zhang } 223fb8bd90fSChunyan Zhang 224fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host, 225fb8bd90fSChunyan Zhang unsigned int timing) 226fb8bd90fSChunyan Zhang { 227fb8bd90fSChunyan Zhang u16 ctrl_2; 228fb8bd90fSChunyan Zhang 229fb8bd90fSChunyan Zhang if (timing == host->timing) 230fb8bd90fSChunyan Zhang return; 231fb8bd90fSChunyan Zhang 232fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 233fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */ 234fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 235fb8bd90fSChunyan Zhang switch (timing) { 236fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12: 237fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 238fb8bd90fSChunyan Zhang break; 239fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS: 240fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS: 241fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25: 242fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 243fb8bd90fSChunyan Zhang break; 244fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50: 245fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 246fb8bd90fSChunyan Zhang break; 247fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104: 248fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 249fb8bd90fSChunyan Zhang break; 250fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50: 251fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52: 252fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 253fb8bd90fSChunyan Zhang break; 254fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200: 255fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200; 256fb8bd90fSChunyan Zhang break; 257fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400: 258fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400; 259fb8bd90fSChunyan Zhang break; 260fb8bd90fSChunyan Zhang default: 261fb8bd90fSChunyan Zhang break; 262fb8bd90fSChunyan Zhang } 263fb8bd90fSChunyan Zhang 264fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 265fb8bd90fSChunyan Zhang } 266fb8bd90fSChunyan Zhang 267fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host) 268fb8bd90fSChunyan Zhang { 269fb8bd90fSChunyan Zhang int val; 270fb8bd90fSChunyan Zhang 271fb8bd90fSChunyan Zhang /* 272fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to 273fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for 274fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can 275fb8bd90fSChunyan Zhang * not be cleared. 276fb8bd90fSChunyan Zhang */ 277fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET); 278fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD; 279fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 280fb8bd90fSChunyan Zhang /* wait for 10 us */ 281fb8bd90fSChunyan Zhang usleep_range(10, 20); 282fb8bd90fSChunyan Zhang 283fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD; 284fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET); 285fb8bd90fSChunyan Zhang usleep_range(300, 500); 286fb8bd90fSChunyan Zhang } 287fb8bd90fSChunyan Zhang 2887486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host) 2897486831dSBaolin Wang { 2907486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */ 2917486831dSBaolin Wang return 1 << 31; 2927486831dSBaolin Wang } 2937486831dSBaolin Wang 294fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = { 295fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl, 296fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel, 297fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb, 298fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock, 299fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock, 300fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock, 301fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width, 302fb8bd90fSChunyan Zhang .reset = sdhci_reset, 303fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling, 304fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset, 3057486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count, 306fb8bd90fSChunyan Zhang }; 307fb8bd90fSChunyan Zhang 308fb8bd90fSChunyan Zhang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq) 309fb8bd90fSChunyan Zhang { 310fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc); 311fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 312fb8bd90fSChunyan Zhang 313fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23; 314fb8bd90fSChunyan Zhang 315fb8bd90fSChunyan Zhang /* 316fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit 317fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of 318fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller. 319fb8bd90fSChunyan Zhang */ 320fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 && 321fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) && 322fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23)) 323fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23; 324fb8bd90fSChunyan Zhang 325fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq); 326fb8bd90fSChunyan Zhang } 327fb8bd90fSChunyan Zhang 328fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = { 329fb8bd90fSChunyan Zhang .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK, 330fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 331fb8bd90fSChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT, 332fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops, 333fb8bd90fSChunyan Zhang }; 334fb8bd90fSChunyan Zhang 335fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev) 336fb8bd90fSChunyan Zhang { 337fb8bd90fSChunyan Zhang struct sdhci_host *host; 338fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host; 339fb8bd90fSChunyan Zhang struct clk *clk; 340fb8bd90fSChunyan Zhang int ret = 0; 341fb8bd90fSChunyan Zhang 342fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host)); 343fb8bd90fSChunyan Zhang if (IS_ERR(host)) 344fb8bd90fSChunyan Zhang return PTR_ERR(host); 345fb8bd90fSChunyan Zhang 346fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64); 347fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask; 348fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request; 349fb8bd90fSChunyan Zhang 350fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 351fb8bd90fSChunyan Zhang MMC_CAP_ERASE | MMC_CAP_CMD23; 352fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc); 353fb8bd90fSChunyan Zhang if (ret) 354fb8bd90fSChunyan Zhang goto pltfm_free; 355fb8bd90fSChunyan Zhang 356fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host); 357fb8bd90fSChunyan Zhang 358fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio"); 359fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 360fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 361fb8bd90fSChunyan Zhang goto pltfm_free; 362fb8bd90fSChunyan Zhang } 363fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk; 364fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio); 365fb8bd90fSChunyan Zhang if (!sprd_host->base_rate) 366fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE; 367fb8bd90fSChunyan Zhang 368fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable"); 369fb8bd90fSChunyan Zhang if (IS_ERR(clk)) { 370fb8bd90fSChunyan Zhang ret = PTR_ERR(clk); 371fb8bd90fSChunyan Zhang goto pltfm_free; 372fb8bd90fSChunyan Zhang } 373fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk; 374fb8bd90fSChunyan Zhang 375ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable"); 376ebd88a38SBaolin Wang if (!IS_ERR(clk)) 377ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk; 378ebd88a38SBaolin Wang 379fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 380fb8bd90fSChunyan Zhang if (ret) 381fb8bd90fSChunyan Zhang goto pltfm_free; 382fb8bd90fSChunyan Zhang 3831d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 384fb8bd90fSChunyan Zhang if (ret) 385fb8bd90fSChunyan Zhang goto clk_disable; 386fb8bd90fSChunyan Zhang 387ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 388ebd88a38SBaolin Wang if (ret) 389ebd88a38SBaolin Wang goto clk_disable2; 390ebd88a38SBaolin Wang 391fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host); 392fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION); 393fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >> 394fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT); 395fb8bd90fSChunyan Zhang 396fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev); 397fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev); 398fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev); 399fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 400fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev); 401fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1); 402fb8bd90fSChunyan Zhang 403fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host); 404fb8bd90fSChunyan Zhang 405fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host); 406fb8bd90fSChunyan Zhang if (ret) 407fb8bd90fSChunyan Zhang goto pm_runtime_disable; 408fb8bd90fSChunyan Zhang 409fb8bd90fSChunyan Zhang sprd_host->flags = host->flags; 410fb8bd90fSChunyan Zhang 411fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host); 412fb8bd90fSChunyan Zhang if (ret) 413fb8bd90fSChunyan Zhang goto err_cleanup_host; 414fb8bd90fSChunyan Zhang 415fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev); 416fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev); 417fb8bd90fSChunyan Zhang 418fb8bd90fSChunyan Zhang return 0; 419fb8bd90fSChunyan Zhang 420fb8bd90fSChunyan Zhang err_cleanup_host: 421fb8bd90fSChunyan Zhang sdhci_cleanup_host(host); 422fb8bd90fSChunyan Zhang 423fb8bd90fSChunyan Zhang pm_runtime_disable: 424fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev); 425fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev); 426fb8bd90fSChunyan Zhang 427ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 428ebd88a38SBaolin Wang 429ebd88a38SBaolin Wang clk_disable2: 430fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 431fb8bd90fSChunyan Zhang 432fb8bd90fSChunyan Zhang clk_disable: 433fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 434fb8bd90fSChunyan Zhang 435fb8bd90fSChunyan Zhang pltfm_free: 436fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev); 437fb8bd90fSChunyan Zhang return ret; 438fb8bd90fSChunyan Zhang } 439fb8bd90fSChunyan Zhang 440fb8bd90fSChunyan Zhang static int sdhci_sprd_remove(struct platform_device *pdev) 441fb8bd90fSChunyan Zhang { 442fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev); 443fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 444fb8bd90fSChunyan Zhang struct mmc_host *mmc = host->mmc; 445fb8bd90fSChunyan Zhang 446fb8bd90fSChunyan Zhang mmc_remove_host(mmc); 447fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 448fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 449ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 450fb8bd90fSChunyan Zhang 451fb8bd90fSChunyan Zhang mmc_free_host(mmc); 452fb8bd90fSChunyan Zhang 453fb8bd90fSChunyan Zhang return 0; 454fb8bd90fSChunyan Zhang } 455fb8bd90fSChunyan Zhang 456fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = { 457fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", }, 458fb8bd90fSChunyan Zhang { } 459fb8bd90fSChunyan Zhang }; 460fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match); 461fb8bd90fSChunyan Zhang 462fb8bd90fSChunyan Zhang #ifdef CONFIG_PM 463fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev) 464fb8bd90fSChunyan Zhang { 465fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 466fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 467fb8bd90fSChunyan Zhang 468fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host); 469fb8bd90fSChunyan Zhang 470fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio); 471fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable); 472ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 473fb8bd90fSChunyan Zhang 474fb8bd90fSChunyan Zhang return 0; 475fb8bd90fSChunyan Zhang } 476fb8bd90fSChunyan Zhang 477fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev) 478fb8bd90fSChunyan Zhang { 479fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev); 480fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host); 481fb8bd90fSChunyan Zhang int ret; 482fb8bd90fSChunyan Zhang 483ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable); 484fb8bd90fSChunyan Zhang if (ret) 485fb8bd90fSChunyan Zhang return ret; 486fb8bd90fSChunyan Zhang 487ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable); 488ebd88a38SBaolin Wang if (ret) 489ebd88a38SBaolin Wang goto clk_2x_disable; 490ebd88a38SBaolin Wang 491fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio); 492ebd88a38SBaolin Wang if (ret) 493ebd88a38SBaolin Wang goto clk_disable; 494fb8bd90fSChunyan Zhang 495fb8bd90fSChunyan Zhang sdhci_runtime_resume_host(host); 496fb8bd90fSChunyan Zhang return 0; 497ebd88a38SBaolin Wang 498ebd88a38SBaolin Wang clk_disable: 499ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable); 500ebd88a38SBaolin Wang 501ebd88a38SBaolin Wang clk_2x_disable: 502ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable); 503ebd88a38SBaolin Wang 504ebd88a38SBaolin Wang return ret; 505fb8bd90fSChunyan Zhang } 506fb8bd90fSChunyan Zhang #endif 507fb8bd90fSChunyan Zhang 508fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = { 509fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 510fb8bd90fSChunyan Zhang pm_runtime_force_resume) 511fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend, 512fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL) 513fb8bd90fSChunyan Zhang }; 514fb8bd90fSChunyan Zhang 515fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = { 516fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe, 517fb8bd90fSChunyan Zhang .remove = sdhci_sprd_remove, 518fb8bd90fSChunyan Zhang .driver = { 519fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11", 520fb8bd90fSChunyan Zhang .of_match_table = of_match_ptr(sdhci_sprd_of_match), 521fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops, 522fb8bd90fSChunyan Zhang }, 523fb8bd90fSChunyan Zhang }; 524fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver); 525fb8bd90fSChunyan Zhang 526fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver"); 527fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2"); 528fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11"); 529