1fb8bd90fSChunyan Zhang // SPDX-License-Identifier: GPL-2.0
2fb8bd90fSChunyan Zhang //
3fb8bd90fSChunyan Zhang // Secure Digital Host Controller
4fb8bd90fSChunyan Zhang //
5fb8bd90fSChunyan Zhang // Copyright (C) 2018 Spreadtrum, Inc.
6fb8bd90fSChunyan Zhang // Author: Chunyan Zhang <chunyan.zhang@unisoc.com>
7fb8bd90fSChunyan Zhang
8fb8bd90fSChunyan Zhang #include <linux/delay.h>
9fb8bd90fSChunyan Zhang #include <linux/dma-mapping.h>
10fb8bd90fSChunyan Zhang #include <linux/highmem.h>
117f00917aSZhenxiong Lai #include <linux/iopoll.h>
12d83d251bSWenchao Chen #include <linux/mmc/host.h>
13d83d251bSWenchao Chen #include <linux/mmc/mmc.h>
14fb8bd90fSChunyan Zhang #include <linux/module.h>
15fb8bd90fSChunyan Zhang #include <linux/of.h>
16fb8bd90fSChunyan Zhang #include <linux/of_gpio.h>
1729ca763fSBaolin Wang #include <linux/pinctrl/consumer.h>
18fb8bd90fSChunyan Zhang #include <linux/platform_device.h>
19fb8bd90fSChunyan Zhang #include <linux/pm_runtime.h>
20fb8bd90fSChunyan Zhang #include <linux/regulator/consumer.h>
21fb8bd90fSChunyan Zhang #include <linux/slab.h>
22fb8bd90fSChunyan Zhang
23fb8bd90fSChunyan Zhang #include "sdhci-pltfm.h"
24f4498549SBaolin Wang #include "mmc_hsq.h"
25fb8bd90fSChunyan Zhang
26fb8bd90fSChunyan Zhang /* SDHCI_ARGUMENT2 register high 16bit */
27fb8bd90fSChunyan Zhang #define SDHCI_SPRD_ARG2_STUFF GENMASK(31, 16)
28fb8bd90fSChunyan Zhang
2987a395c2SBaolin Wang #define SDHCI_SPRD_REG_32_DLL_CFG 0x200
3087a395c2SBaolin Wang #define SDHCI_SPRD_DLL_ALL_CPST_EN (BIT(18) | BIT(24) | BIT(25) | BIT(26) | BIT(27))
3187a395c2SBaolin Wang #define SDHCI_SPRD_DLL_EN BIT(21)
3287a395c2SBaolin Wang #define SDHCI_SPRD_DLL_SEARCH_MODE BIT(16)
3387a395c2SBaolin Wang #define SDHCI_SPRD_DLL_INIT_COUNT 0xc00
3487a395c2SBaolin Wang #define SDHCI_SPRD_DLL_PHASE_INTERNAL 0x3
3587a395c2SBaolin Wang
365f2f4e0dSBaolin Wang #define SDHCI_SPRD_REG_32_DLL_DLY 0x204
375f2f4e0dSBaolin Wang
38fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_DLL_DLY_OFFSET 0x208
39fb8bd90fSChunyan Zhang #define SDHCIBSPRD_IT_WR_DLY_INV BIT(5)
40fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_CMD_DLY_INV BIT(13)
41fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_POSRD_DLY_INV BIT(21)
42fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_NEGRD_DLY_INV BIT(29)
43fb8bd90fSChunyan Zhang
447f00917aSZhenxiong Lai #define SDHCI_SPRD_REG_32_DLL_STS0 0x210
457f00917aSZhenxiong Lai #define SDHCI_SPRD_DLL_LOCKED BIT(18)
467f00917aSZhenxiong Lai
47fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_32_BUSY_POSI 0x250
48fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN BIT(25)
49fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN BIT(24)
50fb8bd90fSChunyan Zhang
51fb8bd90fSChunyan Zhang #define SDHCI_SPRD_REG_DEBOUNCE 0x28C
52fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_BAK BIT(0)
53fb8bd90fSChunyan Zhang #define SDHCI_SPRD_BIT_DLL_VAL BIT(1)
54fb8bd90fSChunyan Zhang
55fb8bd90fSChunyan Zhang #define SDHCI_SPRD_INT_SIGNAL_MASK 0x1B7F410B
56fb8bd90fSChunyan Zhang
57fb8bd90fSChunyan Zhang /* SDHCI_HOST_CONTROL2 */
58fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS200 0x0005
59fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CTRL_HS400 0x0006
60494c11e1SBaolin Wang #define SDHCI_SPRD_CTRL_HS400ES 0x0007
61fb8bd90fSChunyan Zhang
62fb8bd90fSChunyan Zhang /*
63fb8bd90fSChunyan Zhang * According to the standard specification, BIT(3) of SDHCI_SOFTWARE_RESET is
64fb8bd90fSChunyan Zhang * reserved, and only used on Spreadtrum's design, the hardware cannot work
65fb8bd90fSChunyan Zhang * if this bit is cleared.
66fb8bd90fSChunyan Zhang * 1 : normal work
67fb8bd90fSChunyan Zhang * 0 : hardware reset
68fb8bd90fSChunyan Zhang */
69fb8bd90fSChunyan Zhang #define SDHCI_HW_RESET_CARD BIT(3)
70fb8bd90fSChunyan Zhang
71fb8bd90fSChunyan Zhang #define SDHCI_SPRD_MAX_CUR 0xFFFFFF
72fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_MAX_DIV 1023
73fb8bd90fSChunyan Zhang
74fb8bd90fSChunyan Zhang #define SDHCI_SPRD_CLK_DEF_RATE 26000000
7587a395c2SBaolin Wang #define SDHCI_SPRD_PHY_DLL_CLK 52000000
76fb8bd90fSChunyan Zhang
77d83d251bSWenchao Chen #define SDHCI_SPRD_MAX_RANGE 0xff
78d83d251bSWenchao Chen #define SDHCI_SPRD_CMD_DLY_MASK GENMASK(15, 8)
79d83d251bSWenchao Chen #define SDHCI_SPRD_POSRD_DLY_MASK GENMASK(23, 16)
80d83d251bSWenchao Chen #define SDHCI_SPRD_CPST_EN GENMASK(27, 24)
81d83d251bSWenchao Chen
82fb8bd90fSChunyan Zhang struct sdhci_sprd_host {
83fb8bd90fSChunyan Zhang u32 version;
84fb8bd90fSChunyan Zhang struct clk *clk_sdio;
85fb8bd90fSChunyan Zhang struct clk *clk_enable;
86ebd88a38SBaolin Wang struct clk *clk_2x_enable;
8729ca763fSBaolin Wang struct pinctrl *pinctrl;
8829ca763fSBaolin Wang struct pinctrl_state *pins_uhs;
8929ca763fSBaolin Wang struct pinctrl_state *pins_default;
90fb8bd90fSChunyan Zhang u32 base_rate;
91fb8bd90fSChunyan Zhang int flags; /* backup of host attribute */
925f2f4e0dSBaolin Wang u32 phy_delay[MMC_TIMING_MMC_HS400 + 2];
935f2f4e0dSBaolin Wang };
945f2f4e0dSBaolin Wang
95d83d251bSWenchao Chen enum sdhci_sprd_tuning_type {
96d83d251bSWenchao Chen SDHCI_SPRD_TUNING_SD_HS_CMD,
97d83d251bSWenchao Chen SDHCI_SPRD_TUNING_SD_HS_DATA,
98d83d251bSWenchao Chen };
99d83d251bSWenchao Chen
1005f2f4e0dSBaolin Wang struct sdhci_sprd_phy_cfg {
1015f2f4e0dSBaolin Wang const char *property;
1025f2f4e0dSBaolin Wang u8 timing;
1035f2f4e0dSBaolin Wang };
1045f2f4e0dSBaolin Wang
1055f2f4e0dSBaolin Wang static const struct sdhci_sprd_phy_cfg sdhci_sprd_phy_cfgs[] = {
1065f2f4e0dSBaolin Wang { "sprd,phy-delay-legacy", MMC_TIMING_LEGACY, },
1075f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-highspeed", MMC_TIMING_SD_HS, },
1085f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr50", MMC_TIMING_UHS_SDR50, },
1095f2f4e0dSBaolin Wang { "sprd,phy-delay-sd-uhs-sdr104", MMC_TIMING_UHS_SDR104, },
1105f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-highspeed", MMC_TIMING_MMC_HS, },
1115f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-ddr52", MMC_TIMING_MMC_DDR52, },
1125f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs200", MMC_TIMING_MMC_HS200, },
1135f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400", MMC_TIMING_MMC_HS400, },
1145f2f4e0dSBaolin Wang { "sprd,phy-delay-mmc-hs400es", MMC_TIMING_MMC_HS400 + 1, },
115fb8bd90fSChunyan Zhang };
116fb8bd90fSChunyan Zhang
117fb8bd90fSChunyan Zhang #define TO_SPRD_HOST(host) sdhci_pltfm_priv(sdhci_priv(host))
118fb8bd90fSChunyan Zhang
sdhci_sprd_init_config(struct sdhci_host * host)119fb8bd90fSChunyan Zhang static void sdhci_sprd_init_config(struct sdhci_host *host)
120fb8bd90fSChunyan Zhang {
121fb8bd90fSChunyan Zhang u16 val;
122fb8bd90fSChunyan Zhang
123fb8bd90fSChunyan Zhang /* set dll backup mode */
124fb8bd90fSChunyan Zhang val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE);
125fb8bd90fSChunyan Zhang val |= SDHCI_SPRD_BIT_DLL_BAK | SDHCI_SPRD_BIT_DLL_VAL;
126fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_DEBOUNCE);
127fb8bd90fSChunyan Zhang }
128fb8bd90fSChunyan Zhang
sdhci_sprd_readl(struct sdhci_host * host,int reg)129fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_readl(struct sdhci_host *host, int reg)
130fb8bd90fSChunyan Zhang {
131fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT))
132fb8bd90fSChunyan Zhang return SDHCI_SPRD_MAX_CUR;
133fb8bd90fSChunyan Zhang
134fb8bd90fSChunyan Zhang return readl_relaxed(host->ioaddr + reg);
135fb8bd90fSChunyan Zhang }
136fb8bd90fSChunyan Zhang
sdhci_sprd_writel(struct sdhci_host * host,u32 val,int reg)137fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writel(struct sdhci_host *host, u32 val, int reg)
138fb8bd90fSChunyan Zhang {
139fb8bd90fSChunyan Zhang /* SDHCI_MAX_CURRENT is reserved on Spreadtrum's platform */
140fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_MAX_CURRENT))
141fb8bd90fSChunyan Zhang return;
142fb8bd90fSChunyan Zhang
143fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SIGNAL_ENABLE || reg == SDHCI_INT_ENABLE))
144fb8bd90fSChunyan Zhang val = val & SDHCI_SPRD_INT_SIGNAL_MASK;
145fb8bd90fSChunyan Zhang
146fb8bd90fSChunyan Zhang writel_relaxed(val, host->ioaddr + reg);
147fb8bd90fSChunyan Zhang }
148fb8bd90fSChunyan Zhang
sdhci_sprd_writew(struct sdhci_host * host,u16 val,int reg)149fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writew(struct sdhci_host *host, u16 val, int reg)
150fb8bd90fSChunyan Zhang {
151fb8bd90fSChunyan Zhang /* SDHCI_BLOCK_COUNT is Read Only on Spreadtrum's platform */
152fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_BLOCK_COUNT))
153fb8bd90fSChunyan Zhang return;
154fb8bd90fSChunyan Zhang
155fb8bd90fSChunyan Zhang writew_relaxed(val, host->ioaddr + reg);
156fb8bd90fSChunyan Zhang }
157fb8bd90fSChunyan Zhang
sdhci_sprd_writeb(struct sdhci_host * host,u8 val,int reg)158fb8bd90fSChunyan Zhang static inline void sdhci_sprd_writeb(struct sdhci_host *host, u8 val, int reg)
159fb8bd90fSChunyan Zhang {
160fb8bd90fSChunyan Zhang /*
161fb8bd90fSChunyan Zhang * Since BIT(3) of SDHCI_SOFTWARE_RESET is reserved according to the
162fb8bd90fSChunyan Zhang * standard specification, sdhci_reset() write this register directly
163fb8bd90fSChunyan Zhang * without checking other reserved bits, that will clear BIT(3) which
164fb8bd90fSChunyan Zhang * is defined as hardware reset on Spreadtrum's platform and clearing
165fb8bd90fSChunyan Zhang * it by mistake will lead the card not work. So here we need to work
166fb8bd90fSChunyan Zhang * around it.
167fb8bd90fSChunyan Zhang */
168fb8bd90fSChunyan Zhang if (unlikely(reg == SDHCI_SOFTWARE_RESET)) {
169fb8bd90fSChunyan Zhang if (readb_relaxed(host->ioaddr + reg) & SDHCI_HW_RESET_CARD)
170fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD;
171fb8bd90fSChunyan Zhang }
172fb8bd90fSChunyan Zhang
173fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + reg);
174fb8bd90fSChunyan Zhang }
175fb8bd90fSChunyan Zhang
sdhci_sprd_sd_clk_off(struct sdhci_host * host)176fb8bd90fSChunyan Zhang static inline void sdhci_sprd_sd_clk_off(struct sdhci_host *host)
177fb8bd90fSChunyan Zhang {
178fb8bd90fSChunyan Zhang u16 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
179fb8bd90fSChunyan Zhang
180fb8bd90fSChunyan Zhang ctrl &= ~SDHCI_CLOCK_CARD_EN;
181fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
182fb8bd90fSChunyan Zhang }
183fb8bd90fSChunyan Zhang
sdhci_sprd_sd_clk_on(struct sdhci_host * host)184494c11e1SBaolin Wang static inline void sdhci_sprd_sd_clk_on(struct sdhci_host *host)
185494c11e1SBaolin Wang {
186494c11e1SBaolin Wang u16 ctrl;
187494c11e1SBaolin Wang
188494c11e1SBaolin Wang ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
189494c11e1SBaolin Wang ctrl |= SDHCI_CLOCK_CARD_EN;
190494c11e1SBaolin Wang sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL);
191494c11e1SBaolin Wang }
192494c11e1SBaolin Wang
193fb8bd90fSChunyan Zhang static inline void
sdhci_sprd_set_dll_invert(struct sdhci_host * host,u32 mask,bool en)194fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(struct sdhci_host *host, u32 mask, bool en)
195fb8bd90fSChunyan Zhang {
196fb8bd90fSChunyan Zhang u32 dll_dly_offset;
197fb8bd90fSChunyan Zhang
198fb8bd90fSChunyan Zhang dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
199fb8bd90fSChunyan Zhang if (en)
200fb8bd90fSChunyan Zhang dll_dly_offset |= mask;
201fb8bd90fSChunyan Zhang else
202fb8bd90fSChunyan Zhang dll_dly_offset &= ~mask;
203fb8bd90fSChunyan Zhang sdhci_writel(host, dll_dly_offset, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET);
204fb8bd90fSChunyan Zhang }
205fb8bd90fSChunyan Zhang
sdhci_sprd_calc_div(u32 base_clk,u32 clk)206fb8bd90fSChunyan Zhang static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk)
207fb8bd90fSChunyan Zhang {
208fb8bd90fSChunyan Zhang u32 div;
209fb8bd90fSChunyan Zhang
210fb8bd90fSChunyan Zhang /* select 2x clock source */
211fb8bd90fSChunyan Zhang if (base_clk <= clk * 2)
212fb8bd90fSChunyan Zhang return 0;
213fb8bd90fSChunyan Zhang
214fb8bd90fSChunyan Zhang div = (u32) (base_clk / (clk * 2));
215fb8bd90fSChunyan Zhang
216fb8bd90fSChunyan Zhang if ((base_clk / div) > (clk * 2))
217fb8bd90fSChunyan Zhang div++;
218fb8bd90fSChunyan Zhang
219fb8bd90fSChunyan Zhang if (div % 2)
220fb8bd90fSChunyan Zhang div = (div + 1) / 2;
221fb8bd90fSChunyan Zhang else
222fb8bd90fSChunyan Zhang div = div / 2;
223fb8bd90fSChunyan Zhang
224d252e9b1SWenchao Chen if (div > SDHCI_SPRD_CLK_MAX_DIV)
225d252e9b1SWenchao Chen div = SDHCI_SPRD_CLK_MAX_DIV;
226d252e9b1SWenchao Chen
227fb8bd90fSChunyan Zhang return div;
228fb8bd90fSChunyan Zhang }
229fb8bd90fSChunyan Zhang
_sdhci_sprd_set_clock(struct sdhci_host * host,unsigned int clk)230fb8bd90fSChunyan Zhang static inline void _sdhci_sprd_set_clock(struct sdhci_host *host,
231fb8bd90fSChunyan Zhang unsigned int clk)
232fb8bd90fSChunyan Zhang {
233fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
234fb8bd90fSChunyan Zhang u32 div, val, mask;
235fb8bd90fSChunyan Zhang
236efdaf275SChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
237fb8bd90fSChunyan Zhang
238efdaf275SChunyan Zhang div = sdhci_sprd_calc_div(sprd_host->base_rate, clk);
239efdaf275SChunyan Zhang div = ((div & 0x300) >> 2) | ((div & 0xFF) << 8);
240efdaf275SChunyan Zhang sdhci_enable_clk(host, div);
241fb8bd90fSChunyan Zhang
242*2e22a909SWenchao Chen val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI);
243*2e22a909SWenchao Chen mask = SDHCI_SPRD_BIT_OUTR_CLK_AUTO_EN | SDHCI_SPRD_BIT_INNR_CLK_AUTO_EN;
244ff874dbcSWenchao Chen /* Enable CLK_AUTO when the clock is greater than 400K. */
245ff874dbcSWenchao Chen if (clk > 400000) {
246fb8bd90fSChunyan Zhang if (mask != (val & mask)) {
247fb8bd90fSChunyan Zhang val |= mask;
248fb8bd90fSChunyan Zhang sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
249fb8bd90fSChunyan Zhang }
250*2e22a909SWenchao Chen } else {
251*2e22a909SWenchao Chen if (val & mask) {
252*2e22a909SWenchao Chen val &= ~mask;
253*2e22a909SWenchao Chen sdhci_writel(host, val, SDHCI_SPRD_REG_32_BUSY_POSI);
254*2e22a909SWenchao Chen }
255fb8bd90fSChunyan Zhang }
256ff874dbcSWenchao Chen }
257fb8bd90fSChunyan Zhang
sdhci_sprd_enable_phy_dll(struct sdhci_host * host)25887a395c2SBaolin Wang static void sdhci_sprd_enable_phy_dll(struct sdhci_host *host)
25987a395c2SBaolin Wang {
26087a395c2SBaolin Wang u32 tmp;
26187a395c2SBaolin Wang
26287a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
26387a395c2SBaolin Wang tmp &= ~(SDHCI_SPRD_DLL_EN | SDHCI_SPRD_DLL_ALL_CPST_EN);
26487a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
26587a395c2SBaolin Wang /* wait 1ms */
26687a395c2SBaolin Wang usleep_range(1000, 1250);
26787a395c2SBaolin Wang
26887a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
26987a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_ALL_CPST_EN | SDHCI_SPRD_DLL_SEARCH_MODE |
27087a395c2SBaolin Wang SDHCI_SPRD_DLL_INIT_COUNT | SDHCI_SPRD_DLL_PHASE_INTERNAL;
27187a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
27287a395c2SBaolin Wang /* wait 1ms */
27387a395c2SBaolin Wang usleep_range(1000, 1250);
27487a395c2SBaolin Wang
27587a395c2SBaolin Wang tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
27687a395c2SBaolin Wang tmp |= SDHCI_SPRD_DLL_EN;
27787a395c2SBaolin Wang sdhci_writel(host, tmp, SDHCI_SPRD_REG_32_DLL_CFG);
27887a395c2SBaolin Wang /* wait 1ms */
27987a395c2SBaolin Wang usleep_range(1000, 1250);
2807f00917aSZhenxiong Lai
2817f00917aSZhenxiong Lai if (read_poll_timeout(sdhci_readl, tmp, (tmp & SDHCI_SPRD_DLL_LOCKED),
2827f00917aSZhenxiong Lai 2000, USEC_PER_SEC, false, host, SDHCI_SPRD_REG_32_DLL_STS0)) {
2837f00917aSZhenxiong Lai pr_err("%s: DLL locked fail!\n", mmc_hostname(host->mmc));
2847f00917aSZhenxiong Lai pr_info("%s: DLL_STS0 : 0x%x, DLL_CFG : 0x%x\n",
2857f00917aSZhenxiong Lai mmc_hostname(host->mmc),
2867f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_STS0),
2877f00917aSZhenxiong Lai sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG));
2887f00917aSZhenxiong Lai }
28987a395c2SBaolin Wang }
29087a395c2SBaolin Wang
sdhci_sprd_set_clock(struct sdhci_host * host,unsigned int clock)291fb8bd90fSChunyan Zhang static void sdhci_sprd_set_clock(struct sdhci_host *host, unsigned int clock)
292fb8bd90fSChunyan Zhang {
29387a395c2SBaolin Wang bool en = false, clk_changed = false;
294fb8bd90fSChunyan Zhang
295fb8bd90fSChunyan Zhang if (clock == 0) {
296fb8bd90fSChunyan Zhang sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
297fb8bd90fSChunyan Zhang } else if (clock != host->clock) {
298fb8bd90fSChunyan Zhang sdhci_sprd_sd_clk_off(host);
299fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock);
300fb8bd90fSChunyan Zhang
301fb8bd90fSChunyan Zhang if (clock <= 400000)
302fb8bd90fSChunyan Zhang en = true;
303fb8bd90fSChunyan Zhang sdhci_sprd_set_dll_invert(host, SDHCI_SPRD_BIT_CMD_DLY_INV |
304fb8bd90fSChunyan Zhang SDHCI_SPRD_BIT_POSRD_DLY_INV, en);
30587a395c2SBaolin Wang clk_changed = true;
306fb8bd90fSChunyan Zhang } else {
307fb8bd90fSChunyan Zhang _sdhci_sprd_set_clock(host, clock);
308fb8bd90fSChunyan Zhang }
30987a395c2SBaolin Wang
31087a395c2SBaolin Wang /*
31187a395c2SBaolin Wang * According to the Spreadtrum SD host specification, when we changed
31287a395c2SBaolin Wang * the clock to be more than 52M, we should enable the PHY DLL which
31387a395c2SBaolin Wang * is used to track the clock frequency to make the clock work more
31487a395c2SBaolin Wang * stable. Otherwise deviation may occur of the higher clock.
31587a395c2SBaolin Wang */
31687a395c2SBaolin Wang if (clk_changed && clock > SDHCI_SPRD_PHY_DLL_CLK)
31787a395c2SBaolin Wang sdhci_sprd_enable_phy_dll(host);
318fb8bd90fSChunyan Zhang }
319fb8bd90fSChunyan Zhang
sdhci_sprd_get_max_clock(struct sdhci_host * host)320fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_max_clock(struct sdhci_host *host)
321fb8bd90fSChunyan Zhang {
322fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
323fb8bd90fSChunyan Zhang
324fb8bd90fSChunyan Zhang return clk_round_rate(sprd_host->clk_sdio, ULONG_MAX);
325fb8bd90fSChunyan Zhang }
326fb8bd90fSChunyan Zhang
sdhci_sprd_get_min_clock(struct sdhci_host * host)327fb8bd90fSChunyan Zhang static unsigned int sdhci_sprd_get_min_clock(struct sdhci_host *host)
328fb8bd90fSChunyan Zhang {
3296e141772SWenchao Chen return 100000;
330fb8bd90fSChunyan Zhang }
331fb8bd90fSChunyan Zhang
sdhci_sprd_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)332fb8bd90fSChunyan Zhang static void sdhci_sprd_set_uhs_signaling(struct sdhci_host *host,
333fb8bd90fSChunyan Zhang unsigned int timing)
334fb8bd90fSChunyan Zhang {
3355f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
3365f2f4e0dSBaolin Wang struct mmc_host *mmc = host->mmc;
3375f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay;
338fb8bd90fSChunyan Zhang u16 ctrl_2;
339fb8bd90fSChunyan Zhang
340fb8bd90fSChunyan Zhang if (timing == host->timing)
341fb8bd90fSChunyan Zhang return;
342fb8bd90fSChunyan Zhang
343fb8bd90fSChunyan Zhang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
344fb8bd90fSChunyan Zhang /* Select Bus Speed Mode for host */
345fb8bd90fSChunyan Zhang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
346fb8bd90fSChunyan Zhang switch (timing) {
347fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR12:
348fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
349fb8bd90fSChunyan Zhang break;
350fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS:
351fb8bd90fSChunyan Zhang case MMC_TIMING_SD_HS:
352fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR25:
353fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
354fb8bd90fSChunyan Zhang break;
355fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR50:
356fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
357fb8bd90fSChunyan Zhang break;
358fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_SDR104:
359fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
360fb8bd90fSChunyan Zhang break;
361fb8bd90fSChunyan Zhang case MMC_TIMING_UHS_DDR50:
362fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_DDR52:
363fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
364fb8bd90fSChunyan Zhang break;
365fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS200:
366fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS200;
367fb8bd90fSChunyan Zhang break;
368fb8bd90fSChunyan Zhang case MMC_TIMING_MMC_HS400:
369fb8bd90fSChunyan Zhang ctrl_2 |= SDHCI_SPRD_CTRL_HS400;
370fb8bd90fSChunyan Zhang break;
371fb8bd90fSChunyan Zhang default:
372fb8bd90fSChunyan Zhang break;
373fb8bd90fSChunyan Zhang }
374fb8bd90fSChunyan Zhang
375fb8bd90fSChunyan Zhang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
3765f2f4e0dSBaolin Wang
3775f2f4e0dSBaolin Wang if (!mmc->ios.enhanced_strobe)
3785f2f4e0dSBaolin Wang sdhci_writel(host, p[timing], SDHCI_SPRD_REG_32_DLL_DLY);
379fb8bd90fSChunyan Zhang }
380fb8bd90fSChunyan Zhang
sdhci_sprd_hw_reset(struct sdhci_host * host)381fb8bd90fSChunyan Zhang static void sdhci_sprd_hw_reset(struct sdhci_host *host)
382fb8bd90fSChunyan Zhang {
383fb8bd90fSChunyan Zhang int val;
384fb8bd90fSChunyan Zhang
385fb8bd90fSChunyan Zhang /*
386fb8bd90fSChunyan Zhang * Note: don't use sdhci_writeb() API here since it is redirected to
387fb8bd90fSChunyan Zhang * sdhci_sprd_writeb() in which we have a workaround for
388fb8bd90fSChunyan Zhang * SDHCI_SOFTWARE_RESET which would make bit SDHCI_HW_RESET_CARD can
389fb8bd90fSChunyan Zhang * not be cleared.
390fb8bd90fSChunyan Zhang */
391fb8bd90fSChunyan Zhang val = readb_relaxed(host->ioaddr + SDHCI_SOFTWARE_RESET);
392fb8bd90fSChunyan Zhang val &= ~SDHCI_HW_RESET_CARD;
393fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
394fb8bd90fSChunyan Zhang /* wait for 10 us */
395fb8bd90fSChunyan Zhang usleep_range(10, 20);
396fb8bd90fSChunyan Zhang
397fb8bd90fSChunyan Zhang val |= SDHCI_HW_RESET_CARD;
398fb8bd90fSChunyan Zhang writeb_relaxed(val, host->ioaddr + SDHCI_SOFTWARE_RESET);
399fb8bd90fSChunyan Zhang usleep_range(300, 500);
400fb8bd90fSChunyan Zhang }
401fb8bd90fSChunyan Zhang
sdhci_sprd_get_max_timeout_count(struct sdhci_host * host)4027486831dSBaolin Wang static unsigned int sdhci_sprd_get_max_timeout_count(struct sdhci_host *host)
4037486831dSBaolin Wang {
4047486831dSBaolin Wang /* The Spredtrum controller actual maximum timeout count is 1 << 31 */
4057486831dSBaolin Wang return 1 << 31;
4067486831dSBaolin Wang }
4077486831dSBaolin Wang
sdhci_sprd_get_ro(struct sdhci_host * host)4084eae8cbdSChunyan Zhang static unsigned int sdhci_sprd_get_ro(struct sdhci_host *host)
4094eae8cbdSChunyan Zhang {
4104eae8cbdSChunyan Zhang return 0;
4114eae8cbdSChunyan Zhang }
4124eae8cbdSChunyan Zhang
sdhci_sprd_request_done(struct sdhci_host * host,struct mmc_request * mrq)413f4498549SBaolin Wang static void sdhci_sprd_request_done(struct sdhci_host *host,
414f4498549SBaolin Wang struct mmc_request *mrq)
415f4498549SBaolin Wang {
416f4498549SBaolin Wang /* Validate if the request was from software queue firstly. */
417f4498549SBaolin Wang if (mmc_hsq_finalize_request(host->mmc, mrq))
418f4498549SBaolin Wang return;
419f4498549SBaolin Wang
420f4498549SBaolin Wang mmc_request_done(host->mmc, mrq);
421f4498549SBaolin Wang }
422f4498549SBaolin Wang
sdhci_sprd_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)423cb42d0dcSWenchao Chen static void sdhci_sprd_set_power(struct sdhci_host *host, unsigned char mode,
424cb42d0dcSWenchao Chen unsigned short vdd)
425cb42d0dcSWenchao Chen {
426cb42d0dcSWenchao Chen struct mmc_host *mmc = host->mmc;
427cb42d0dcSWenchao Chen
428cb42d0dcSWenchao Chen switch (mode) {
429cb42d0dcSWenchao Chen case MMC_POWER_OFF:
430cb42d0dcSWenchao Chen mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, 0);
431cb42d0dcSWenchao Chen
432cb42d0dcSWenchao Chen mmc_regulator_disable_vqmmc(mmc);
433cb42d0dcSWenchao Chen break;
434cb42d0dcSWenchao Chen case MMC_POWER_ON:
435cb42d0dcSWenchao Chen mmc_regulator_enable_vqmmc(mmc);
436cb42d0dcSWenchao Chen break;
437cb42d0dcSWenchao Chen case MMC_POWER_UP:
438cb42d0dcSWenchao Chen mmc_regulator_set_ocr(host->mmc, mmc->supply.vmmc, vdd);
439cb42d0dcSWenchao Chen break;
440cb42d0dcSWenchao Chen }
441cb42d0dcSWenchao Chen }
442cb42d0dcSWenchao Chen
443fb8bd90fSChunyan Zhang static struct sdhci_ops sdhci_sprd_ops = {
444fb8bd90fSChunyan Zhang .read_l = sdhci_sprd_readl,
445fb8bd90fSChunyan Zhang .write_l = sdhci_sprd_writel,
44696147082SKrzysztof Kozlowski .write_w = sdhci_sprd_writew,
447fb8bd90fSChunyan Zhang .write_b = sdhci_sprd_writeb,
448fb8bd90fSChunyan Zhang .set_clock = sdhci_sprd_set_clock,
449cb42d0dcSWenchao Chen .set_power = sdhci_sprd_set_power,
450fb8bd90fSChunyan Zhang .get_max_clock = sdhci_sprd_get_max_clock,
451fb8bd90fSChunyan Zhang .get_min_clock = sdhci_sprd_get_min_clock,
452fb8bd90fSChunyan Zhang .set_bus_width = sdhci_set_bus_width,
453fb8bd90fSChunyan Zhang .reset = sdhci_reset,
454fb8bd90fSChunyan Zhang .set_uhs_signaling = sdhci_sprd_set_uhs_signaling,
455fb8bd90fSChunyan Zhang .hw_reset = sdhci_sprd_hw_reset,
4567486831dSBaolin Wang .get_max_timeout_count = sdhci_sprd_get_max_timeout_count,
4574eae8cbdSChunyan Zhang .get_ro = sdhci_sprd_get_ro,
458f4498549SBaolin Wang .request_done = sdhci_sprd_request_done,
459fb8bd90fSChunyan Zhang };
460fb8bd90fSChunyan Zhang
sdhci_sprd_check_auto_cmd23(struct mmc_host * mmc,struct mmc_request * mrq)46161ab64e2SBaolin Wang static void sdhci_sprd_check_auto_cmd23(struct mmc_host *mmc,
46261ab64e2SBaolin Wang struct mmc_request *mrq)
463fb8bd90fSChunyan Zhang {
464fb8bd90fSChunyan Zhang struct sdhci_host *host = mmc_priv(mmc);
465fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
466fb8bd90fSChunyan Zhang
467fb8bd90fSChunyan Zhang host->flags |= sprd_host->flags & SDHCI_AUTO_CMD23;
468fb8bd90fSChunyan Zhang
469fb8bd90fSChunyan Zhang /*
470fb8bd90fSChunyan Zhang * From version 4.10 onward, ARGUMENT2 register is also as 32-bit
471fb8bd90fSChunyan Zhang * block count register which doesn't support stuff bits of
472fb8bd90fSChunyan Zhang * CMD23 argument on Spreadtrum's sd host controller.
473fb8bd90fSChunyan Zhang */
474fb8bd90fSChunyan Zhang if (host->version >= SDHCI_SPEC_410 &&
475fb8bd90fSChunyan Zhang mrq->sbc && (mrq->sbc->arg & SDHCI_SPRD_ARG2_STUFF) &&
476fb8bd90fSChunyan Zhang (host->flags & SDHCI_AUTO_CMD23))
477fb8bd90fSChunyan Zhang host->flags &= ~SDHCI_AUTO_CMD23;
47861ab64e2SBaolin Wang }
47961ab64e2SBaolin Wang
sdhci_sprd_request(struct mmc_host * mmc,struct mmc_request * mrq)48061ab64e2SBaolin Wang static void sdhci_sprd_request(struct mmc_host *mmc, struct mmc_request *mrq)
48161ab64e2SBaolin Wang {
48261ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq);
483fb8bd90fSChunyan Zhang
484fb8bd90fSChunyan Zhang sdhci_request(mmc, mrq);
485fb8bd90fSChunyan Zhang }
486fb8bd90fSChunyan Zhang
sdhci_sprd_request_atomic(struct mmc_host * mmc,struct mmc_request * mrq)48761ab64e2SBaolin Wang static int sdhci_sprd_request_atomic(struct mmc_host *mmc,
48861ab64e2SBaolin Wang struct mmc_request *mrq)
48961ab64e2SBaolin Wang {
49061ab64e2SBaolin Wang sdhci_sprd_check_auto_cmd23(mmc, mrq);
49161ab64e2SBaolin Wang
49261ab64e2SBaolin Wang return sdhci_request_atomic(mmc, mrq);
49361ab64e2SBaolin Wang }
49461ab64e2SBaolin Wang
sdhci_sprd_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)495eef9e0a6SBaolin Wang static int sdhci_sprd_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
496eef9e0a6SBaolin Wang {
49729ca763fSBaolin Wang struct sdhci_host *host = mmc_priv(mmc);
49829ca763fSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
499eef9e0a6SBaolin Wang int ret;
500eef9e0a6SBaolin Wang
501eef9e0a6SBaolin Wang if (!IS_ERR(mmc->supply.vqmmc)) {
502eef9e0a6SBaolin Wang ret = mmc_regulator_set_vqmmc(mmc, ios);
5039cbe0fc8SMarek Vasut if (ret < 0) {
504eef9e0a6SBaolin Wang pr_err("%s: Switching signalling voltage failed\n",
505eef9e0a6SBaolin Wang mmc_hostname(mmc));
506eef9e0a6SBaolin Wang return ret;
507eef9e0a6SBaolin Wang }
508eef9e0a6SBaolin Wang }
509eef9e0a6SBaolin Wang
51029ca763fSBaolin Wang if (IS_ERR(sprd_host->pinctrl))
511dd30dcfaSWenchao Chen goto reset;
51229ca763fSBaolin Wang
51329ca763fSBaolin Wang switch (ios->signal_voltage) {
51429ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_180:
51529ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl,
51629ca763fSBaolin Wang sprd_host->pins_uhs);
51729ca763fSBaolin Wang if (ret) {
51829ca763fSBaolin Wang pr_err("%s: failed to select uhs pin state\n",
51929ca763fSBaolin Wang mmc_hostname(mmc));
52029ca763fSBaolin Wang return ret;
52129ca763fSBaolin Wang }
52229ca763fSBaolin Wang break;
52329ca763fSBaolin Wang
52429ca763fSBaolin Wang default:
525df561f66SGustavo A. R. Silva fallthrough;
52629ca763fSBaolin Wang case MMC_SIGNAL_VOLTAGE_330:
52729ca763fSBaolin Wang ret = pinctrl_select_state(sprd_host->pinctrl,
52829ca763fSBaolin Wang sprd_host->pins_default);
52929ca763fSBaolin Wang if (ret) {
53029ca763fSBaolin Wang pr_err("%s: failed to select default pin state\n",
53129ca763fSBaolin Wang mmc_hostname(mmc));
53229ca763fSBaolin Wang return ret;
53329ca763fSBaolin Wang }
53429ca763fSBaolin Wang break;
53529ca763fSBaolin Wang }
53629ca763fSBaolin Wang
53729ca763fSBaolin Wang /* Wait for 300 ~ 500 us for pin state stable */
53829ca763fSBaolin Wang usleep_range(300, 500);
539dd30dcfaSWenchao Chen
540dd30dcfaSWenchao Chen reset:
54129ca763fSBaolin Wang sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
54229ca763fSBaolin Wang
543eef9e0a6SBaolin Wang return 0;
544eef9e0a6SBaolin Wang }
545eef9e0a6SBaolin Wang
sdhci_sprd_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)546494c11e1SBaolin Wang static void sdhci_sprd_hs400_enhanced_strobe(struct mmc_host *mmc,
547494c11e1SBaolin Wang struct mmc_ios *ios)
548494c11e1SBaolin Wang {
549494c11e1SBaolin Wang struct sdhci_host *host = mmc_priv(mmc);
5505f2f4e0dSBaolin Wang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
5515f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay;
552494c11e1SBaolin Wang u16 ctrl_2;
553494c11e1SBaolin Wang
554494c11e1SBaolin Wang if (!ios->enhanced_strobe)
555494c11e1SBaolin Wang return;
556494c11e1SBaolin Wang
557494c11e1SBaolin Wang sdhci_sprd_sd_clk_off(host);
558494c11e1SBaolin Wang
559494c11e1SBaolin Wang /* Set HS400 enhanced strobe mode */
560494c11e1SBaolin Wang ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
561494c11e1SBaolin Wang ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
562494c11e1SBaolin Wang ctrl_2 |= SDHCI_SPRD_CTRL_HS400ES;
563494c11e1SBaolin Wang sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
564494c11e1SBaolin Wang
565494c11e1SBaolin Wang sdhci_sprd_sd_clk_on(host);
5665f2f4e0dSBaolin Wang
5675f2f4e0dSBaolin Wang /* Set the PHY DLL delay value for HS400 enhanced strobe mode */
5685f2f4e0dSBaolin Wang sdhci_writel(host, p[MMC_TIMING_MMC_HS400 + 1],
5695f2f4e0dSBaolin Wang SDHCI_SPRD_REG_32_DLL_DLY);
5705f2f4e0dSBaolin Wang }
5715f2f4e0dSBaolin Wang
mmc_send_tuning_cmd(struct mmc_card * card)572d83d251bSWenchao Chen static int mmc_send_tuning_cmd(struct mmc_card *card)
573d83d251bSWenchao Chen {
574d83d251bSWenchao Chen return mmc_send_status(card, NULL);
575d83d251bSWenchao Chen }
576d83d251bSWenchao Chen
mmc_send_tuning_data(struct mmc_card * card)577d83d251bSWenchao Chen static int mmc_send_tuning_data(struct mmc_card *card)
578d83d251bSWenchao Chen {
579d83d251bSWenchao Chen u8 *status;
580d83d251bSWenchao Chen int ret;
581d83d251bSWenchao Chen
582d83d251bSWenchao Chen status = kmalloc(64, GFP_KERNEL);
583d83d251bSWenchao Chen if (!status)
584d83d251bSWenchao Chen return -ENOMEM;
585d83d251bSWenchao Chen
586d83d251bSWenchao Chen ret = mmc_sd_switch(card, 0, 0, 0, status);
587d83d251bSWenchao Chen
588d83d251bSWenchao Chen kfree(status);
589d83d251bSWenchao Chen
590d83d251bSWenchao Chen return ret;
591d83d251bSWenchao Chen }
592d83d251bSWenchao Chen
sdhci_sprd_get_best_clk_sample(struct mmc_host * mmc,u8 * value)593d83d251bSWenchao Chen static int sdhci_sprd_get_best_clk_sample(struct mmc_host *mmc, u8 *value)
594d83d251bSWenchao Chen {
595d83d251bSWenchao Chen int range_end = SDHCI_SPRD_MAX_RANGE;
596d83d251bSWenchao Chen int range_length = 0;
597d83d251bSWenchao Chen int middle_range = 0;
598d83d251bSWenchao Chen int count = 0;
599d83d251bSWenchao Chen int i;
600d83d251bSWenchao Chen
601d83d251bSWenchao Chen for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) {
602d83d251bSWenchao Chen if (value[i]) {
603d83d251bSWenchao Chen pr_debug("%s: tuning ok: %d\n", mmc_hostname(mmc), i);
604d83d251bSWenchao Chen count++;
605d83d251bSWenchao Chen } else {
606d83d251bSWenchao Chen pr_debug("%s: tuning fail: %d\n", mmc_hostname(mmc), i);
607d83d251bSWenchao Chen if (range_length < count) {
608d83d251bSWenchao Chen range_length = count;
609d83d251bSWenchao Chen range_end = i - 1;
610d83d251bSWenchao Chen count = 0;
611d83d251bSWenchao Chen }
612d83d251bSWenchao Chen }
613d83d251bSWenchao Chen }
614d83d251bSWenchao Chen
615d83d251bSWenchao Chen if (!count)
616d83d251bSWenchao Chen return -EIO;
617d83d251bSWenchao Chen
618d83d251bSWenchao Chen if (count > range_length) {
619d83d251bSWenchao Chen range_length = count;
620d83d251bSWenchao Chen range_end = i - 1;
621d83d251bSWenchao Chen }
622d83d251bSWenchao Chen
623d83d251bSWenchao Chen middle_range = range_end - (range_length - 1) / 2;
624d83d251bSWenchao Chen
625d83d251bSWenchao Chen return middle_range;
626d83d251bSWenchao Chen }
627d83d251bSWenchao Chen
sdhci_sprd_tuning(struct mmc_host * mmc,struct mmc_card * card,enum sdhci_sprd_tuning_type type)628d83d251bSWenchao Chen static int sdhci_sprd_tuning(struct mmc_host *mmc, struct mmc_card *card,
629d83d251bSWenchao Chen enum sdhci_sprd_tuning_type type)
630d83d251bSWenchao Chen {
631d83d251bSWenchao Chen struct sdhci_host *host = mmc_priv(mmc);
632d83d251bSWenchao Chen struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
633d83d251bSWenchao Chen u32 *p = sprd_host->phy_delay;
634d83d251bSWenchao Chen u32 dll_cfg, dll_dly;
635d83d251bSWenchao Chen int best_clk_sample;
636d83d251bSWenchao Chen int err = 0;
637d83d251bSWenchao Chen u8 *value;
638d83d251bSWenchao Chen int i;
639d83d251bSWenchao Chen
640d83d251bSWenchao Chen value = kmalloc(SDHCI_SPRD_MAX_RANGE + 1, GFP_KERNEL);
641d83d251bSWenchao Chen if (!value)
642d83d251bSWenchao Chen return -ENOMEM;
643d83d251bSWenchao Chen
644d83d251bSWenchao Chen sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
645d83d251bSWenchao Chen
646d83d251bSWenchao Chen dll_cfg = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG);
647d83d251bSWenchao Chen dll_cfg &= ~SDHCI_SPRD_CPST_EN;
648d83d251bSWenchao Chen sdhci_writel(host, dll_cfg, SDHCI_SPRD_REG_32_DLL_CFG);
649d83d251bSWenchao Chen
650d83d251bSWenchao Chen dll_dly = p[mmc->ios.timing];
651d83d251bSWenchao Chen
652d83d251bSWenchao Chen for (i = 0; i <= SDHCI_SPRD_MAX_RANGE; i++) {
653d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) {
654d83d251bSWenchao Chen dll_dly &= ~SDHCI_SPRD_CMD_DLY_MASK;
655d83d251bSWenchao Chen dll_dly |= ((i << 8) & SDHCI_SPRD_CMD_DLY_MASK);
656d83d251bSWenchao Chen } else {
657d83d251bSWenchao Chen dll_dly &= ~SDHCI_SPRD_POSRD_DLY_MASK;
658d83d251bSWenchao Chen dll_dly |= ((i << 16) & SDHCI_SPRD_POSRD_DLY_MASK);
659d83d251bSWenchao Chen }
660d83d251bSWenchao Chen
661d83d251bSWenchao Chen sdhci_writel(host, dll_dly, SDHCI_SPRD_REG_32_DLL_DLY);
662d83d251bSWenchao Chen
663d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD)
664d83d251bSWenchao Chen value[i] = !mmc_send_tuning_cmd(card);
665d83d251bSWenchao Chen else
666d83d251bSWenchao Chen value[i] = !mmc_send_tuning_data(card);
667d83d251bSWenchao Chen }
668d83d251bSWenchao Chen
669d83d251bSWenchao Chen best_clk_sample = sdhci_sprd_get_best_clk_sample(mmc, value);
670d83d251bSWenchao Chen if (best_clk_sample < 0) {
671d83d251bSWenchao Chen dev_err(mmc_dev(host->mmc), "all tuning phase fail!\n");
672168054caSDan Carpenter err = best_clk_sample;
673d83d251bSWenchao Chen goto out;
674d83d251bSWenchao Chen }
675d83d251bSWenchao Chen
676d83d251bSWenchao Chen if (type == SDHCI_SPRD_TUNING_SD_HS_CMD) {
677d83d251bSWenchao Chen p[mmc->ios.timing] &= ~SDHCI_SPRD_CMD_DLY_MASK;
678d83d251bSWenchao Chen p[mmc->ios.timing] |= ((best_clk_sample << 8) & SDHCI_SPRD_CMD_DLY_MASK);
679d83d251bSWenchao Chen } else {
680d83d251bSWenchao Chen p[mmc->ios.timing] &= ~(SDHCI_SPRD_POSRD_DLY_MASK);
681d83d251bSWenchao Chen p[mmc->ios.timing] |= ((best_clk_sample << 16) & SDHCI_SPRD_POSRD_DLY_MASK);
682d83d251bSWenchao Chen }
683d83d251bSWenchao Chen
684d83d251bSWenchao Chen pr_debug("%s: the best clk sample %d, delay value 0x%08x\n",
685d83d251bSWenchao Chen mmc_hostname(host->mmc), best_clk_sample, p[mmc->ios.timing]);
686d83d251bSWenchao Chen
687d83d251bSWenchao Chen out:
688d83d251bSWenchao Chen sdhci_writel(host, p[mmc->ios.timing], SDHCI_SPRD_REG_32_DLL_DLY);
689d83d251bSWenchao Chen
690d83d251bSWenchao Chen kfree(value);
691d83d251bSWenchao Chen
692d83d251bSWenchao Chen return err;
693d83d251bSWenchao Chen }
694d83d251bSWenchao Chen
sdhci_sprd_prepare_sd_hs_cmd_tuning(struct mmc_host * mmc,struct mmc_card * card)695d83d251bSWenchao Chen static int sdhci_sprd_prepare_sd_hs_cmd_tuning(struct mmc_host *mmc, struct mmc_card *card)
696d83d251bSWenchao Chen {
697d83d251bSWenchao Chen return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_CMD);
698d83d251bSWenchao Chen }
699d83d251bSWenchao Chen
sdhci_sprd_execute_sd_hs_data_tuning(struct mmc_host * mmc,struct mmc_card * card)700d83d251bSWenchao Chen static int sdhci_sprd_execute_sd_hs_data_tuning(struct mmc_host *mmc, struct mmc_card *card)
701d83d251bSWenchao Chen {
702d83d251bSWenchao Chen return sdhci_sprd_tuning(mmc, card, SDHCI_SPRD_TUNING_SD_HS_DATA);
703d83d251bSWenchao Chen }
704d83d251bSWenchao Chen
sdhci_sprd_phy_param_parse(struct sdhci_sprd_host * sprd_host,struct device_node * np)7055f2f4e0dSBaolin Wang static void sdhci_sprd_phy_param_parse(struct sdhci_sprd_host *sprd_host,
7065f2f4e0dSBaolin Wang struct device_node *np)
7075f2f4e0dSBaolin Wang {
7085f2f4e0dSBaolin Wang u32 *p = sprd_host->phy_delay;
7095f2f4e0dSBaolin Wang int ret, i, index;
7105f2f4e0dSBaolin Wang u32 val[4];
7115f2f4e0dSBaolin Wang
7125f2f4e0dSBaolin Wang for (i = 0; i < ARRAY_SIZE(sdhci_sprd_phy_cfgs); i++) {
7135f2f4e0dSBaolin Wang ret = of_property_read_u32_array(np,
7145f2f4e0dSBaolin Wang sdhci_sprd_phy_cfgs[i].property, val, 4);
7155f2f4e0dSBaolin Wang if (ret)
7165f2f4e0dSBaolin Wang continue;
7175f2f4e0dSBaolin Wang
7185f2f4e0dSBaolin Wang index = sdhci_sprd_phy_cfgs[i].timing;
7195f2f4e0dSBaolin Wang p[index] = val[0] | (val[1] << 8) | (val[2] << 16) | (val[3] << 24);
7205f2f4e0dSBaolin Wang }
721494c11e1SBaolin Wang }
722494c11e1SBaolin Wang
723fb8bd90fSChunyan Zhang static const struct sdhci_pltfm_data sdhci_sprd_pdata = {
7244324e54bSChunyan Zhang .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
725924ea310SAdrian Hunter SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
726fb8bd90fSChunyan Zhang .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
7276a526f66SChunyan Zhang SDHCI_QUIRK2_USE_32BIT_BLK_CNT |
7286a526f66SChunyan Zhang SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
729fb8bd90fSChunyan Zhang .ops = &sdhci_sprd_ops,
730fb8bd90fSChunyan Zhang };
731fb8bd90fSChunyan Zhang
sdhci_sprd_probe(struct platform_device * pdev)732fb8bd90fSChunyan Zhang static int sdhci_sprd_probe(struct platform_device *pdev)
733fb8bd90fSChunyan Zhang {
734fb8bd90fSChunyan Zhang struct sdhci_host *host;
735fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host;
736f4498549SBaolin Wang struct mmc_hsq *hsq;
737fb8bd90fSChunyan Zhang struct clk *clk;
738fb8bd90fSChunyan Zhang int ret = 0;
739fb8bd90fSChunyan Zhang
740fb8bd90fSChunyan Zhang host = sdhci_pltfm_init(pdev, &sdhci_sprd_pdata, sizeof(*sprd_host));
741fb8bd90fSChunyan Zhang if (IS_ERR(host))
742fb8bd90fSChunyan Zhang return PTR_ERR(host);
743fb8bd90fSChunyan Zhang
744fb8bd90fSChunyan Zhang host->dma_mask = DMA_BIT_MASK(64);
745fb8bd90fSChunyan Zhang pdev->dev.dma_mask = &host->dma_mask;
746fb8bd90fSChunyan Zhang host->mmc_host_ops.request = sdhci_sprd_request;
747494c11e1SBaolin Wang host->mmc_host_ops.hs400_enhanced_strobe =
748494c11e1SBaolin Wang sdhci_sprd_hs400_enhanced_strobe;
749d83d251bSWenchao Chen host->mmc_host_ops.prepare_sd_hs_tuning =
750d83d251bSWenchao Chen sdhci_sprd_prepare_sd_hs_cmd_tuning;
751d83d251bSWenchao Chen host->mmc_host_ops.execute_sd_hs_tuning =
752d83d251bSWenchao Chen sdhci_sprd_execute_sd_hs_data_tuning;
753d83d251bSWenchao Chen
754eef9e0a6SBaolin Wang /*
755eef9e0a6SBaolin Wang * We can not use the standard ops to change and detect the voltage
756eef9e0a6SBaolin Wang * signal for Spreadtrum SD host controller, since our voltage regulator
757eef9e0a6SBaolin Wang * for I/O is fixed in hardware, that means we do not need control
758eef9e0a6SBaolin Wang * the standard SD host controller to change the I/O voltage.
759eef9e0a6SBaolin Wang */
760eef9e0a6SBaolin Wang host->mmc_host_ops.start_signal_voltage_switch =
761eef9e0a6SBaolin Wang sdhci_sprd_voltage_switch;
762fb8bd90fSChunyan Zhang
763fb8bd90fSChunyan Zhang host->mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
764a049b5aeSUlf Hansson MMC_CAP_WAIT_WHILE_BUSY;
765a049b5aeSUlf Hansson
766fb8bd90fSChunyan Zhang ret = mmc_of_parse(host->mmc);
767fb8bd90fSChunyan Zhang if (ret)
768fb8bd90fSChunyan Zhang goto pltfm_free;
769fb8bd90fSChunyan Zhang
77061ab64e2SBaolin Wang if (!mmc_card_is_removable(host->mmc))
77161ab64e2SBaolin Wang host->mmc_host_ops.request_atomic = sdhci_sprd_request_atomic;
77261ab64e2SBaolin Wang else
77361ab64e2SBaolin Wang host->always_defer_done = true;
77461ab64e2SBaolin Wang
775fb8bd90fSChunyan Zhang sprd_host = TO_SPRD_HOST(host);
7765f2f4e0dSBaolin Wang sdhci_sprd_phy_param_parse(sprd_host, pdev->dev.of_node);
777fb8bd90fSChunyan Zhang
77829ca763fSBaolin Wang sprd_host->pinctrl = devm_pinctrl_get(&pdev->dev);
77929ca763fSBaolin Wang if (!IS_ERR(sprd_host->pinctrl)) {
78029ca763fSBaolin Wang sprd_host->pins_uhs =
78129ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "state_uhs");
78229ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_uhs)) {
78329ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_uhs);
78429ca763fSBaolin Wang goto pltfm_free;
78529ca763fSBaolin Wang }
78629ca763fSBaolin Wang
78729ca763fSBaolin Wang sprd_host->pins_default =
78829ca763fSBaolin Wang pinctrl_lookup_state(sprd_host->pinctrl, "default");
78929ca763fSBaolin Wang if (IS_ERR(sprd_host->pins_default)) {
79029ca763fSBaolin Wang ret = PTR_ERR(sprd_host->pins_default);
79129ca763fSBaolin Wang goto pltfm_free;
79229ca763fSBaolin Wang }
79329ca763fSBaolin Wang }
79429ca763fSBaolin Wang
795fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "sdio");
796fb8bd90fSChunyan Zhang if (IS_ERR(clk)) {
797fb8bd90fSChunyan Zhang ret = PTR_ERR(clk);
798fb8bd90fSChunyan Zhang goto pltfm_free;
799fb8bd90fSChunyan Zhang }
800fb8bd90fSChunyan Zhang sprd_host->clk_sdio = clk;
801fb8bd90fSChunyan Zhang sprd_host->base_rate = clk_get_rate(sprd_host->clk_sdio);
802fb8bd90fSChunyan Zhang if (!sprd_host->base_rate)
803fb8bd90fSChunyan Zhang sprd_host->base_rate = SDHCI_SPRD_CLK_DEF_RATE;
804fb8bd90fSChunyan Zhang
805fb8bd90fSChunyan Zhang clk = devm_clk_get(&pdev->dev, "enable");
806fb8bd90fSChunyan Zhang if (IS_ERR(clk)) {
807fb8bd90fSChunyan Zhang ret = PTR_ERR(clk);
808fb8bd90fSChunyan Zhang goto pltfm_free;
809fb8bd90fSChunyan Zhang }
810fb8bd90fSChunyan Zhang sprd_host->clk_enable = clk;
811fb8bd90fSChunyan Zhang
812ebd88a38SBaolin Wang clk = devm_clk_get(&pdev->dev, "2x_enable");
813ebd88a38SBaolin Wang if (!IS_ERR(clk))
814ebd88a38SBaolin Wang sprd_host->clk_2x_enable = clk;
815ebd88a38SBaolin Wang
816fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio);
817fb8bd90fSChunyan Zhang if (ret)
818fb8bd90fSChunyan Zhang goto pltfm_free;
819fb8bd90fSChunyan Zhang
8201d94717dSBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable);
821fb8bd90fSChunyan Zhang if (ret)
822fb8bd90fSChunyan Zhang goto clk_disable;
823fb8bd90fSChunyan Zhang
824ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable);
825ebd88a38SBaolin Wang if (ret)
826ebd88a38SBaolin Wang goto clk_disable2;
827ebd88a38SBaolin Wang
828fb8bd90fSChunyan Zhang sdhci_sprd_init_config(host);
829fb8bd90fSChunyan Zhang host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
830fb8bd90fSChunyan Zhang sprd_host->version = ((host->version & SDHCI_VENDOR_VER_MASK) >>
831fb8bd90fSChunyan Zhang SDHCI_VENDOR_VER_SHIFT);
832fb8bd90fSChunyan Zhang
833fb8bd90fSChunyan Zhang pm_runtime_get_noresume(&pdev->dev);
834fb8bd90fSChunyan Zhang pm_runtime_set_active(&pdev->dev);
835fb8bd90fSChunyan Zhang pm_runtime_enable(&pdev->dev);
836fb8bd90fSChunyan Zhang pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
837fb8bd90fSChunyan Zhang pm_runtime_use_autosuspend(&pdev->dev);
838fb8bd90fSChunyan Zhang pm_suspend_ignore_children(&pdev->dev, 1);
839fb8bd90fSChunyan Zhang
840fb8bd90fSChunyan Zhang sdhci_enable_v4_mode(host);
841fb8bd90fSChunyan Zhang
8422f765c17SChunyan Zhang /*
8432f765c17SChunyan Zhang * Supply the existing CAPS, but clear the UHS-I modes. This
8442f765c17SChunyan Zhang * will allow these modes to be specified only by device
8452f765c17SChunyan Zhang * tree properties through mmc_of_parse().
8462f765c17SChunyan Zhang */
847924ea310SAdrian Hunter sdhci_read_caps(host);
8482f765c17SChunyan Zhang host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
8492f765c17SChunyan Zhang SDHCI_SUPPORT_DDR50);
8502f765c17SChunyan Zhang
851cb42d0dcSWenchao Chen ret = mmc_regulator_get_supply(host->mmc);
852cb42d0dcSWenchao Chen if (ret)
853cb42d0dcSWenchao Chen goto pm_runtime_disable;
854cb42d0dcSWenchao Chen
855fb8bd90fSChunyan Zhang ret = sdhci_setup_host(host);
856fb8bd90fSChunyan Zhang if (ret)
857fb8bd90fSChunyan Zhang goto pm_runtime_disable;
858fb8bd90fSChunyan Zhang
859fb8bd90fSChunyan Zhang sprd_host->flags = host->flags;
860fb8bd90fSChunyan Zhang
861f4498549SBaolin Wang hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
862f4498549SBaolin Wang if (!hsq) {
863f4498549SBaolin Wang ret = -ENOMEM;
864f4498549SBaolin Wang goto err_cleanup_host;
865f4498549SBaolin Wang }
866f4498549SBaolin Wang
867f4498549SBaolin Wang ret = mmc_hsq_init(hsq, host->mmc);
868f4498549SBaolin Wang if (ret)
869f4498549SBaolin Wang goto err_cleanup_host;
870f4498549SBaolin Wang
871fb8bd90fSChunyan Zhang ret = __sdhci_add_host(host);
872fb8bd90fSChunyan Zhang if (ret)
873fb8bd90fSChunyan Zhang goto err_cleanup_host;
874fb8bd90fSChunyan Zhang
875fb8bd90fSChunyan Zhang pm_runtime_mark_last_busy(&pdev->dev);
876fb8bd90fSChunyan Zhang pm_runtime_put_autosuspend(&pdev->dev);
877fb8bd90fSChunyan Zhang
878fb8bd90fSChunyan Zhang return 0;
879fb8bd90fSChunyan Zhang
880fb8bd90fSChunyan Zhang err_cleanup_host:
881fb8bd90fSChunyan Zhang sdhci_cleanup_host(host);
882fb8bd90fSChunyan Zhang
883fb8bd90fSChunyan Zhang pm_runtime_disable:
884fc62113bSBaolin Wang pm_runtime_put_noidle(&pdev->dev);
885fb8bd90fSChunyan Zhang pm_runtime_disable(&pdev->dev);
886fb8bd90fSChunyan Zhang pm_runtime_set_suspended(&pdev->dev);
887fb8bd90fSChunyan Zhang
888ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable);
889ebd88a38SBaolin Wang
890ebd88a38SBaolin Wang clk_disable2:
891fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable);
892fb8bd90fSChunyan Zhang
893fb8bd90fSChunyan Zhang clk_disable:
894fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio);
895fb8bd90fSChunyan Zhang
896fb8bd90fSChunyan Zhang pltfm_free:
897fb8bd90fSChunyan Zhang sdhci_pltfm_free(pdev);
898fb8bd90fSChunyan Zhang return ret;
899fb8bd90fSChunyan Zhang }
900fb8bd90fSChunyan Zhang
sdhci_sprd_remove(struct platform_device * pdev)901c618ba0fSYangtao Li static void sdhci_sprd_remove(struct platform_device *pdev)
902fb8bd90fSChunyan Zhang {
903fb8bd90fSChunyan Zhang struct sdhci_host *host = platform_get_drvdata(pdev);
904fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
905fb8bd90fSChunyan Zhang
906c9c256a8SChristophe JAILLET sdhci_remove_host(host, 0);
907c9c256a8SChristophe JAILLET
908fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio);
909fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable);
910ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable);
911fb8bd90fSChunyan Zhang
912c9c256a8SChristophe JAILLET sdhci_pltfm_free(pdev);
913fb8bd90fSChunyan Zhang }
914fb8bd90fSChunyan Zhang
915fb8bd90fSChunyan Zhang static const struct of_device_id sdhci_sprd_of_match[] = {
916fb8bd90fSChunyan Zhang { .compatible = "sprd,sdhci-r11", },
917fb8bd90fSChunyan Zhang { }
918fb8bd90fSChunyan Zhang };
919fb8bd90fSChunyan Zhang MODULE_DEVICE_TABLE(of, sdhci_sprd_of_match);
920fb8bd90fSChunyan Zhang
921fb8bd90fSChunyan Zhang #ifdef CONFIG_PM
sdhci_sprd_runtime_suspend(struct device * dev)922fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_suspend(struct device *dev)
923fb8bd90fSChunyan Zhang {
924fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev);
925fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
926fb8bd90fSChunyan Zhang
927f4498549SBaolin Wang mmc_hsq_suspend(host->mmc);
928fb8bd90fSChunyan Zhang sdhci_runtime_suspend_host(host);
929fb8bd90fSChunyan Zhang
930fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_sdio);
931fb8bd90fSChunyan Zhang clk_disable_unprepare(sprd_host->clk_enable);
932ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable);
933fb8bd90fSChunyan Zhang
934fb8bd90fSChunyan Zhang return 0;
935fb8bd90fSChunyan Zhang }
936fb8bd90fSChunyan Zhang
sdhci_sprd_runtime_resume(struct device * dev)937fb8bd90fSChunyan Zhang static int sdhci_sprd_runtime_resume(struct device *dev)
938fb8bd90fSChunyan Zhang {
939fb8bd90fSChunyan Zhang struct sdhci_host *host = dev_get_drvdata(dev);
940fb8bd90fSChunyan Zhang struct sdhci_sprd_host *sprd_host = TO_SPRD_HOST(host);
941fb8bd90fSChunyan Zhang int ret;
942fb8bd90fSChunyan Zhang
943ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_2x_enable);
944fb8bd90fSChunyan Zhang if (ret)
945fb8bd90fSChunyan Zhang return ret;
946fb8bd90fSChunyan Zhang
947ebd88a38SBaolin Wang ret = clk_prepare_enable(sprd_host->clk_enable);
948ebd88a38SBaolin Wang if (ret)
949ebd88a38SBaolin Wang goto clk_2x_disable;
950ebd88a38SBaolin Wang
951fb8bd90fSChunyan Zhang ret = clk_prepare_enable(sprd_host->clk_sdio);
952ebd88a38SBaolin Wang if (ret)
953ebd88a38SBaolin Wang goto clk_disable;
954fb8bd90fSChunyan Zhang
955c6303c5dSBaolin Wang sdhci_runtime_resume_host(host, 1);
956f4498549SBaolin Wang mmc_hsq_resume(host->mmc);
957f4498549SBaolin Wang
958fb8bd90fSChunyan Zhang return 0;
959ebd88a38SBaolin Wang
960ebd88a38SBaolin Wang clk_disable:
961ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_enable);
962ebd88a38SBaolin Wang
963ebd88a38SBaolin Wang clk_2x_disable:
964ebd88a38SBaolin Wang clk_disable_unprepare(sprd_host->clk_2x_enable);
965ebd88a38SBaolin Wang
966ebd88a38SBaolin Wang return ret;
967fb8bd90fSChunyan Zhang }
968fb8bd90fSChunyan Zhang #endif
969fb8bd90fSChunyan Zhang
970fb8bd90fSChunyan Zhang static const struct dev_pm_ops sdhci_sprd_pm_ops = {
971fb8bd90fSChunyan Zhang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
972fb8bd90fSChunyan Zhang pm_runtime_force_resume)
973fb8bd90fSChunyan Zhang SET_RUNTIME_PM_OPS(sdhci_sprd_runtime_suspend,
974fb8bd90fSChunyan Zhang sdhci_sprd_runtime_resume, NULL)
975fb8bd90fSChunyan Zhang };
976fb8bd90fSChunyan Zhang
977fb8bd90fSChunyan Zhang static struct platform_driver sdhci_sprd_driver = {
978fb8bd90fSChunyan Zhang .probe = sdhci_sprd_probe,
979c618ba0fSYangtao Li .remove_new = sdhci_sprd_remove,
980fb8bd90fSChunyan Zhang .driver = {
981fb8bd90fSChunyan Zhang .name = "sdhci_sprd_r11",
982d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
983a96e6523SKrzysztof Kozlowski .of_match_table = sdhci_sprd_of_match,
984fb8bd90fSChunyan Zhang .pm = &sdhci_sprd_pm_ops,
985fb8bd90fSChunyan Zhang },
986fb8bd90fSChunyan Zhang };
987fb8bd90fSChunyan Zhang module_platform_driver(sdhci_sprd_driver);
988fb8bd90fSChunyan Zhang
989fb8bd90fSChunyan Zhang MODULE_DESCRIPTION("Spreadtrum sdio host controller r11 driver");
990fb8bd90fSChunyan Zhang MODULE_LICENSE("GPL v2");
991fb8bd90fSChunyan Zhang MODULE_ALIAS("platform:sdhci-sprd-r11");
992