1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/iopoll.h> 17 #include "sdhci.h" 18 #include "sdhci-pci.h" 19 #include "cqhci.h" 20 21 /* Genesys Logic extra registers */ 22 #define SDHCI_GLI_9750_WT 0x800 23 #define SDHCI_GLI_9750_WT_EN BIT(0) 24 #define GLI_9750_WT_EN_ON 0x1 25 #define GLI_9750_WT_EN_OFF 0x0 26 27 #define SDHCI_GLI_9750_CFG2 0x848 28 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 29 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 30 31 #define SDHCI_GLI_9750_DRIVING 0x860 32 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 33 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 34 #define GLI_9750_DRIVING_1_VALUE 0xFFF 35 #define GLI_9750_DRIVING_2_VALUE 0x3 36 #define SDHCI_GLI_9750_SEL_1 BIT(29) 37 #define SDHCI_GLI_9750_SEL_2 BIT(31) 38 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 39 40 #define SDHCI_GLI_9750_PLL 0x864 41 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 42 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 43 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 44 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 45 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 46 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 47 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 48 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 49 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 50 51 #define SDHCI_GLI_9750_PLLSSC 0x86C 52 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 53 54 #define SDHCI_GLI_9750_SW_CTRL 0x874 55 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 56 #define GLI_9750_SW_CTRL_4_VALUE 0x3 57 58 #define SDHCI_GLI_9750_MISC 0x878 59 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 60 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 61 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 62 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 63 #define GLI_9750_MISC_RX_INV_ON 0x1 64 #define GLI_9750_MISC_RX_INV_OFF 0x0 65 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 66 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 67 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 68 69 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 70 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 71 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 72 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 73 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 74 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 75 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 76 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 77 78 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 79 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 80 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 81 82 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 83 84 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 85 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 86 87 #define PCIE_GLI_9763E_VHS 0x884 88 #define GLI_9763E_VHS_REV GENMASK(19, 16) 89 #define GLI_9763E_VHS_REV_R 0x0 90 #define GLI_9763E_VHS_REV_M 0x1 91 #define GLI_9763E_VHS_REV_W 0x2 92 #define PCIE_GLI_9763E_MB 0x888 93 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 94 #define GLI_9763E_MB_ERP_ON BIT(7) 95 #define PCIE_GLI_9763E_SCR 0x8E0 96 #define GLI_9763E_SCR_AXI_REQ BIT(9) 97 98 #define PCIE_GLI_9763E_CFG 0x8A0 99 #define GLI_9763E_CFG_LPSN_DIS BIT(12) 100 101 #define PCIE_GLI_9763E_CFG2 0x8A4 102 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 103 #define GLI_9763E_CFG2_L1DLY_MID 0x54 104 105 #define PCIE_GLI_9763E_MMC_CTRL 0x960 106 #define GLI_9763E_HS400_SLOW BIT(3) 107 108 #define PCIE_GLI_9763E_CLKRXDLY 0x934 109 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 110 #define GLI_9763E_HS400_RXDLY_5 0x5 111 112 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 113 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 114 SDHCI_TRNS_BLK_CNT_EN | \ 115 SDHCI_TRNS_DMA) 116 117 #define PCI_GLI_9755_WT 0x800 118 #define PCI_GLI_9755_WT_EN BIT(0) 119 #define GLI_9755_WT_EN_ON 0x1 120 #define GLI_9755_WT_EN_OFF 0x0 121 122 #define PCI_GLI_9755_PECONF 0x44 123 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 124 #define PCI_GLI_9755_DMACLK BIT(29) 125 #define PCI_GLI_9755_INVERT_CD BIT(30) 126 #define PCI_GLI_9755_INVERT_WP BIT(31) 127 128 #define PCI_GLI_9755_CFG2 0x48 129 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 130 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 131 132 #define PCI_GLI_9755_PLL 0x64 133 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 134 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 135 #define PCI_GLI_9755_PLL_DIR BIT(15) 136 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 137 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 138 139 #define PCI_GLI_9755_PLLSSC 0x68 140 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 141 142 #define PCI_GLI_9755_SerDes 0x70 143 #define PCI_GLI_9755_SCP_DIS BIT(19) 144 145 #define PCI_GLI_9755_MISC 0x78 146 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 147 148 #define PCI_GLI_9755_PM_CTRL 0xFC 149 #define PCI_GLI_9755_PM_STATE GENMASK(1, 0) 150 151 #define GLI_MAX_TUNING_LOOP 40 152 153 /* Genesys Logic chipset */ 154 static inline void gl9750_wt_on(struct sdhci_host *host) 155 { 156 u32 wt_value; 157 u32 wt_enable; 158 159 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 160 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 161 162 if (wt_enable == GLI_9750_WT_EN_ON) 163 return; 164 165 wt_value &= ~SDHCI_GLI_9750_WT_EN; 166 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 167 168 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 169 } 170 171 static inline void gl9750_wt_off(struct sdhci_host *host) 172 { 173 u32 wt_value; 174 u32 wt_enable; 175 176 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 177 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 178 179 if (wt_enable == GLI_9750_WT_EN_OFF) 180 return; 181 182 wt_value &= ~SDHCI_GLI_9750_WT_EN; 183 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 184 185 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 186 } 187 188 static void gli_set_9750(struct sdhci_host *host) 189 { 190 u32 driving_value; 191 u32 pll_value; 192 u32 sw_ctrl_value; 193 u32 misc_value; 194 u32 parameter_value; 195 u32 control_value; 196 u16 ctrl2; 197 198 gl9750_wt_on(host); 199 200 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 201 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 202 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 203 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 204 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 205 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 206 207 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 208 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 209 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 210 GLI_9750_DRIVING_1_VALUE); 211 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 212 GLI_9750_DRIVING_2_VALUE); 213 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 214 driving_value |= SDHCI_GLI_9750_SEL_2; 215 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 216 217 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 218 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 219 GLI_9750_SW_CTRL_4_VALUE); 220 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 221 222 /* reset the tuning flow after reinit and before starting tuning */ 223 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 224 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 225 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 226 GLI_9750_PLL_TX2_INV_VALUE); 227 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 228 GLI_9750_PLL_TX2_DLY_VALUE); 229 230 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 231 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 232 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 233 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 234 GLI_9750_MISC_TX1_INV_VALUE); 235 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 236 GLI_9750_MISC_RX_INV_VALUE); 237 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 238 GLI_9750_MISC_TX1_DLY_VALUE); 239 240 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 241 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 242 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 243 244 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 245 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 246 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 247 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 248 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 249 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 250 251 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 252 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 253 254 /* disable tuned clk */ 255 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 256 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 257 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 258 259 /* enable tuning parameters control */ 260 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 261 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 262 GLI_9750_TUNING_CONTROL_EN_ON); 263 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 264 265 /* write tuning parameters */ 266 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 267 268 /* disable tuning parameters control */ 269 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 270 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 271 GLI_9750_TUNING_CONTROL_EN_OFF); 272 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 273 274 /* clear tuned clk */ 275 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 276 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 277 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 278 279 gl9750_wt_off(host); 280 } 281 282 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 283 { 284 u32 misc_value; 285 286 gl9750_wt_on(host); 287 288 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 289 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 290 if (b) { 291 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 292 GLI_9750_MISC_RX_INV_ON); 293 } else { 294 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 295 GLI_9750_MISC_RX_INV_OFF); 296 } 297 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 298 299 gl9750_wt_off(host); 300 } 301 302 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 303 { 304 int i; 305 int rx_inv; 306 307 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 308 gli_set_9750_rx_inv(host, !!rx_inv); 309 sdhci_start_tuning(host); 310 311 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 312 u16 ctrl; 313 314 sdhci_send_tuning(host, opcode); 315 316 if (!host->tuning_done) { 317 sdhci_abort_tuning(host, opcode); 318 break; 319 } 320 321 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 322 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 323 if (ctrl & SDHCI_CTRL_TUNED_CLK) 324 return 0; /* Success! */ 325 break; 326 } 327 } 328 } 329 if (!host->tuning_done) { 330 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 331 mmc_hostname(host->mmc)); 332 return -ETIMEDOUT; 333 } 334 335 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 336 mmc_hostname(host->mmc)); 337 sdhci_reset_tuning(host); 338 339 return -EAGAIN; 340 } 341 342 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 343 { 344 host->mmc->retune_period = 0; 345 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 346 host->mmc->retune_period = host->tuning_count; 347 348 gli_set_9750(host); 349 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 350 sdhci_end_tuning(host); 351 352 return 0; 353 } 354 355 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 356 { 357 u32 pll; 358 359 gl9750_wt_on(host); 360 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 361 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 362 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 363 gl9750_wt_off(host); 364 } 365 366 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 367 { 368 u32 pll; 369 370 gl9750_wt_on(host); 371 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 372 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 373 SDHCI_GLI_9750_PLL_PDIV | 374 SDHCI_GLI_9750_PLL_DIR); 375 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 376 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 377 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 378 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 379 gl9750_wt_off(host); 380 381 /* wait for pll stable */ 382 mdelay(1); 383 } 384 385 static bool gl9750_ssc_enable(struct sdhci_host *host) 386 { 387 u32 misc; 388 u8 off; 389 390 gl9750_wt_on(host); 391 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 392 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 393 gl9750_wt_off(host); 394 395 return !off; 396 } 397 398 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 399 { 400 u32 pll; 401 u32 ssc; 402 403 gl9750_wt_on(host); 404 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 405 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 406 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 407 SDHCI_GLI_9750_PLLSSC_EN); 408 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 409 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 410 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 411 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 412 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 413 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 414 gl9750_wt_off(host); 415 } 416 417 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 418 { 419 bool enable = gl9750_ssc_enable(host); 420 421 /* set pll to 205MHz and ssc */ 422 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 423 gl9750_set_pll(host, 0x1, 0x246, 0x0); 424 } 425 426 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 427 { 428 bool enable = gl9750_ssc_enable(host); 429 430 /* set pll to 100MHz and ssc */ 431 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 432 gl9750_set_pll(host, 0x1, 0x244, 0x1); 433 } 434 435 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 436 { 437 bool enable = gl9750_ssc_enable(host); 438 439 /* set pll to 50MHz and ssc */ 440 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 441 gl9750_set_pll(host, 0x1, 0x244, 0x3); 442 } 443 444 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 445 { 446 struct mmc_ios *ios = &host->mmc->ios; 447 u16 clk; 448 449 host->mmc->actual_clock = 0; 450 451 gl9750_disable_ssc_pll(host); 452 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 453 454 if (clock == 0) 455 return; 456 457 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 458 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 459 host->mmc->actual_clock = 205000000; 460 gl9750_set_ssc_pll_205mhz(host); 461 } else if (clock == 100000000) { 462 gl9750_set_ssc_pll_100mhz(host); 463 } else if (clock == 50000000) { 464 gl9750_set_ssc_pll_50mhz(host); 465 } 466 467 sdhci_enable_clk(host, clk); 468 } 469 470 static void gl9750_hw_setting(struct sdhci_host *host) 471 { 472 u32 value; 473 474 gl9750_wt_on(host); 475 476 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 477 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 478 /* set ASPM L1 entry delay to 7.9us */ 479 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 480 GLI_9750_CFG2_L1DLY_VALUE); 481 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 482 483 gl9750_wt_off(host); 484 } 485 486 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 487 { 488 int ret; 489 490 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 491 PCI_IRQ_MSI | PCI_IRQ_MSIX); 492 if (ret < 0) { 493 pr_warn("%s: enable PCI MSI failed, error=%d\n", 494 mmc_hostname(slot->host->mmc), ret); 495 return; 496 } 497 498 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 499 } 500 501 static inline void gl9755_wt_on(struct pci_dev *pdev) 502 { 503 u32 wt_value; 504 u32 wt_enable; 505 506 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 507 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 508 509 if (wt_enable == GLI_9755_WT_EN_ON) 510 return; 511 512 wt_value &= ~PCI_GLI_9755_WT_EN; 513 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 514 515 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 516 } 517 518 static inline void gl9755_wt_off(struct pci_dev *pdev) 519 { 520 u32 wt_value; 521 u32 wt_enable; 522 523 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 524 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 525 526 if (wt_enable == GLI_9755_WT_EN_OFF) 527 return; 528 529 wt_value &= ~PCI_GLI_9755_WT_EN; 530 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 531 532 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 533 } 534 535 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 536 { 537 u32 pll; 538 539 gl9755_wt_on(pdev); 540 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 541 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 542 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 543 gl9755_wt_off(pdev); 544 } 545 546 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 547 { 548 u32 pll; 549 550 gl9755_wt_on(pdev); 551 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 552 pll &= ~(PCI_GLI_9755_PLL_LDIV | 553 PCI_GLI_9755_PLL_PDIV | 554 PCI_GLI_9755_PLL_DIR); 555 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 556 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 557 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 558 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 559 gl9755_wt_off(pdev); 560 561 /* wait for pll stable */ 562 mdelay(1); 563 } 564 565 static bool gl9755_ssc_enable(struct pci_dev *pdev) 566 { 567 u32 misc; 568 u8 off; 569 570 gl9755_wt_on(pdev); 571 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 572 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 573 gl9755_wt_off(pdev); 574 575 return !off; 576 } 577 578 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 579 { 580 u32 pll; 581 u32 ssc; 582 583 gl9755_wt_on(pdev); 584 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 585 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 586 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 587 PCI_GLI_9755_PLLSSC_EN); 588 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 589 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 590 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 591 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 592 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 593 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 594 gl9755_wt_off(pdev); 595 } 596 597 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 598 { 599 bool enable = gl9755_ssc_enable(pdev); 600 601 /* set pll to 205MHz and ssc */ 602 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 603 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 604 } 605 606 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 607 { 608 bool enable = gl9755_ssc_enable(pdev); 609 610 /* set pll to 100MHz and ssc */ 611 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 612 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 613 } 614 615 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 616 { 617 bool enable = gl9755_ssc_enable(pdev); 618 619 /* set pll to 50MHz and ssc */ 620 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 621 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 622 } 623 624 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 625 { 626 struct sdhci_pci_slot *slot = sdhci_priv(host); 627 struct mmc_ios *ios = &host->mmc->ios; 628 struct pci_dev *pdev; 629 u16 clk; 630 631 pdev = slot->chip->pdev; 632 host->mmc->actual_clock = 0; 633 634 gl9755_disable_ssc_pll(pdev); 635 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 636 637 if (clock == 0) 638 return; 639 640 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 641 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 642 host->mmc->actual_clock = 205000000; 643 gl9755_set_ssc_pll_205mhz(pdev); 644 } else if (clock == 100000000) { 645 gl9755_set_ssc_pll_100mhz(pdev); 646 } else if (clock == 50000000) { 647 gl9755_set_ssc_pll_50mhz(pdev); 648 } 649 650 sdhci_enable_clk(host, clk); 651 } 652 653 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 654 { 655 struct pci_dev *pdev = slot->chip->pdev; 656 u32 value; 657 658 gl9755_wt_on(pdev); 659 660 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 661 /* 662 * Apple ARM64 platforms using these chips may have 663 * inverted CD/WP detection. 664 */ 665 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 666 value |= PCI_GLI_9755_INVERT_CD; 667 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 668 value |= PCI_GLI_9755_INVERT_WP; 669 value &= ~PCI_GLI_9755_LFCLK; 670 value &= ~PCI_GLI_9755_DMACLK; 671 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 672 673 /* enable short circuit protection */ 674 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 675 value &= ~PCI_GLI_9755_SCP_DIS; 676 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 677 678 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 679 value &= ~PCI_GLI_9755_CFG2_L1DLY; 680 /* set ASPM L1 entry delay to 7.9us */ 681 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 682 GLI_9755_CFG2_L1DLY_VALUE); 683 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 684 685 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 686 pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); 687 value |= PCI_GLI_9755_PM_STATE; 688 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 689 value &= ~PCI_GLI_9755_PM_STATE; 690 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 691 692 gl9755_wt_off(pdev); 693 } 694 695 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 696 { 697 struct sdhci_host *host = slot->host; 698 699 gl9750_hw_setting(host); 700 gli_pcie_enable_msi(slot); 701 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 702 sdhci_enable_v4_mode(host); 703 704 return 0; 705 } 706 707 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 708 { 709 struct sdhci_host *host = slot->host; 710 711 gl9755_hw_setting(slot); 712 gli_pcie_enable_msi(slot); 713 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 714 sdhci_enable_v4_mode(host); 715 716 return 0; 717 } 718 719 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 720 { 721 /* 722 * According to Section 3.6.1 signal voltage switch procedure in 723 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 724 * follows: 725 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 726 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 727 * period. 728 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 729 * step (12). 730 * 731 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 732 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 733 * 734 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 735 * slightly longer than 5ms before the control register reports that 736 * 1.8V is ready, and far longer still before the card will actually 737 * work reliably. 738 */ 739 usleep_range(100000, 110000); 740 } 741 742 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 743 { 744 sdhci_reset(host, mask); 745 gli_set_9750(host); 746 } 747 748 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 749 { 750 u32 value; 751 752 value = readl(host->ioaddr + reg); 753 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 754 value |= 0xc8; 755 756 return value; 757 } 758 759 #ifdef CONFIG_PM_SLEEP 760 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 761 { 762 struct sdhci_pci_slot *slot = chip->slots[0]; 763 764 pci_free_irq_vectors(slot->chip->pdev); 765 gli_pcie_enable_msi(slot); 766 767 return sdhci_pci_resume_host(chip); 768 } 769 770 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip) 771 { 772 struct sdhci_pci_slot *slot = chip->slots[0]; 773 int ret; 774 775 ret = sdhci_pci_gli_resume(chip); 776 if (ret) 777 return ret; 778 779 return cqhci_resume(slot->host->mmc); 780 } 781 782 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip) 783 { 784 struct sdhci_pci_slot *slot = chip->slots[0]; 785 int ret; 786 787 ret = cqhci_suspend(slot->host->mmc); 788 if (ret) 789 return ret; 790 791 return sdhci_suspend_host(slot->host); 792 } 793 #endif 794 795 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 796 struct mmc_ios *ios) 797 { 798 struct sdhci_host *host = mmc_priv(mmc); 799 u32 val; 800 801 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 802 if (ios->enhanced_strobe) 803 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 804 else 805 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 806 807 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 808 } 809 810 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 811 unsigned int timing) 812 { 813 u16 ctrl_2; 814 815 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 816 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 817 if (timing == MMC_TIMING_MMC_HS200) 818 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 819 else if (timing == MMC_TIMING_MMC_HS) 820 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 821 else if (timing == MMC_TIMING_MMC_DDR52) 822 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 823 else if (timing == MMC_TIMING_MMC_HS400) 824 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 825 826 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 827 } 828 829 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 830 { 831 sdhci_dumpregs(mmc_priv(mmc)); 832 } 833 834 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 835 { 836 struct cqhci_host *cq_host = mmc->cqe_private; 837 u32 value; 838 839 value = cqhci_readl(cq_host, CQHCI_CFG); 840 value |= CQHCI_ENABLE; 841 cqhci_writel(cq_host, value, CQHCI_CFG); 842 } 843 844 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 845 { 846 struct sdhci_host *host = mmc_priv(mmc); 847 848 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 849 sdhci_cqe_enable(mmc); 850 } 851 852 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 853 { 854 int cmd_error = 0; 855 int data_error = 0; 856 857 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 858 return intmask; 859 860 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 861 862 return 0; 863 } 864 865 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 866 { 867 struct sdhci_host *host = mmc_priv(mmc); 868 struct cqhci_host *cq_host = mmc->cqe_private; 869 u32 value; 870 871 value = cqhci_readl(cq_host, CQHCI_CFG); 872 value &= ~CQHCI_ENABLE; 873 cqhci_writel(cq_host, value, CQHCI_CFG); 874 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 875 } 876 877 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 878 .enable = sdhci_gl9763e_cqe_enable, 879 .disable = sdhci_cqe_disable, 880 .dumpregs = sdhci_gl9763e_dumpregs, 881 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 882 .post_disable = sdhci_gl9763e_cqe_post_disable, 883 }; 884 885 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 886 { 887 struct device *dev = &slot->chip->pdev->dev; 888 struct sdhci_host *host = slot->host; 889 struct cqhci_host *cq_host; 890 bool dma64; 891 int ret; 892 893 ret = sdhci_setup_host(host); 894 if (ret) 895 return ret; 896 897 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 898 if (!cq_host) { 899 ret = -ENOMEM; 900 goto cleanup; 901 } 902 903 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 904 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 905 906 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 907 if (dma64) 908 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 909 910 ret = cqhci_init(cq_host, host->mmc, dma64); 911 if (ret) 912 goto cleanup; 913 914 ret = __sdhci_add_host(host); 915 if (ret) 916 goto cleanup; 917 918 return 0; 919 920 cleanup: 921 sdhci_cleanup_host(host); 922 return ret; 923 } 924 925 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask) 926 { 927 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 928 host->mmc->cqe_private) 929 cqhci_deactivate(host->mmc); 930 sdhci_reset(host, mask); 931 } 932 933 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 934 { 935 struct pci_dev *pdev = slot->chip->pdev; 936 u32 value; 937 938 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 939 value &= ~GLI_9763E_VHS_REV; 940 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 941 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 942 943 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 944 value |= GLI_9763E_SCR_AXI_REQ; 945 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 946 947 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 948 value &= ~GLI_9763E_HS400_SLOW; 949 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 950 951 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 952 value &= ~GLI_9763E_CFG2_L1DLY; 953 /* set ASPM L1 entry delay to 21us */ 954 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 955 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 956 957 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 958 value &= ~GLI_9763E_HS400_RXDLY; 959 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 960 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 961 962 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 963 value &= ~GLI_9763E_VHS_REV; 964 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 965 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 966 } 967 968 #ifdef CONFIG_PM 969 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable) 970 { 971 struct pci_dev *pdev = slot->chip->pdev; 972 u32 value; 973 974 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 975 value &= ~GLI_9763E_VHS_REV; 976 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 977 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 978 979 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value); 980 981 if (enable) 982 value &= ~GLI_9763E_CFG_LPSN_DIS; 983 else 984 value |= GLI_9763E_CFG_LPSN_DIS; 985 986 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value); 987 988 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 989 value &= ~GLI_9763E_VHS_REV; 990 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 991 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 992 } 993 994 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 995 { 996 struct sdhci_pci_slot *slot = chip->slots[0]; 997 struct sdhci_host *host = slot->host; 998 u16 clock; 999 1000 /* Enable LPM negotiation to allow entering L1 state */ 1001 gl9763e_set_low_power_negotiation(slot, true); 1002 1003 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1004 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 1005 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1006 1007 return 0; 1008 } 1009 1010 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 1011 { 1012 struct sdhci_pci_slot *slot = chip->slots[0]; 1013 struct sdhci_host *host = slot->host; 1014 u16 clock; 1015 1016 if (host->mmc->ios.power_mode != MMC_POWER_ON) 1017 return 0; 1018 1019 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1020 1021 clock |= SDHCI_CLOCK_PLL_EN; 1022 clock &= ~SDHCI_CLOCK_INT_STABLE; 1023 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1024 1025 /* Wait max 150 ms */ 1026 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 1027 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 1028 pr_err("%s: PLL clock never stabilised.\n", 1029 mmc_hostname(host->mmc)); 1030 sdhci_dumpregs(host); 1031 } 1032 1033 clock |= SDHCI_CLOCK_CARD_EN; 1034 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1035 1036 /* Disable LPM negotiation to avoid entering L1 state. */ 1037 gl9763e_set_low_power_negotiation(slot, false); 1038 1039 return 0; 1040 } 1041 #endif 1042 1043 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 1044 { 1045 struct pci_dev *pdev = slot->chip->pdev; 1046 struct sdhci_host *host = slot->host; 1047 u32 value; 1048 1049 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1050 MMC_CAP_1_8V_DDR | 1051 MMC_CAP_NONREMOVABLE; 1052 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1053 MMC_CAP2_HS400_1_8V | 1054 MMC_CAP2_HS400_ES | 1055 MMC_CAP2_NO_SDIO | 1056 MMC_CAP2_NO_SD; 1057 1058 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1059 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 1060 if (value & GLI_9763E_MB_ERP_ON) 1061 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1062 1063 gli_pcie_enable_msi(slot); 1064 host->mmc_host_ops.hs400_enhanced_strobe = 1065 gl9763e_hs400_enhanced_strobe; 1066 gli_set_gl9763e(slot); 1067 sdhci_enable_v4_mode(host); 1068 1069 return 0; 1070 } 1071 1072 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 1073 1074 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 1075 { 1076 u32 val = readl(host->ioaddr + (reg & ~3)); 1077 u16 word; 1078 1079 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 1080 return word; 1081 } 1082 1083 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 1084 { 1085 u32 val = readl(host->ioaddr + (reg & ~3)); 1086 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 1087 1088 return byte; 1089 } 1090 1091 static const struct sdhci_ops sdhci_gl9755_ops = { 1092 .read_w = sdhci_gli_readw, 1093 .read_b = sdhci_gli_readb, 1094 .set_clock = sdhci_gl9755_set_clock, 1095 .enable_dma = sdhci_pci_enable_dma, 1096 .set_bus_width = sdhci_set_bus_width, 1097 .reset = sdhci_reset, 1098 .set_uhs_signaling = sdhci_set_uhs_signaling, 1099 .voltage_switch = sdhci_gli_voltage_switch, 1100 }; 1101 1102 const struct sdhci_pci_fixes sdhci_gl9755 = { 1103 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1104 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1105 .probe_slot = gli_probe_slot_gl9755, 1106 .ops = &sdhci_gl9755_ops, 1107 #ifdef CONFIG_PM_SLEEP 1108 .resume = sdhci_pci_gli_resume, 1109 #endif 1110 }; 1111 1112 static const struct sdhci_ops sdhci_gl9750_ops = { 1113 .read_w = sdhci_gli_readw, 1114 .read_b = sdhci_gli_readb, 1115 .read_l = sdhci_gl9750_readl, 1116 .set_clock = sdhci_gl9750_set_clock, 1117 .enable_dma = sdhci_pci_enable_dma, 1118 .set_bus_width = sdhci_set_bus_width, 1119 .reset = sdhci_gl9750_reset, 1120 .set_uhs_signaling = sdhci_set_uhs_signaling, 1121 .voltage_switch = sdhci_gli_voltage_switch, 1122 .platform_execute_tuning = gl9750_execute_tuning, 1123 }; 1124 1125 const struct sdhci_pci_fixes sdhci_gl9750 = { 1126 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1127 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1128 .probe_slot = gli_probe_slot_gl9750, 1129 .ops = &sdhci_gl9750_ops, 1130 #ifdef CONFIG_PM_SLEEP 1131 .resume = sdhci_pci_gli_resume, 1132 #endif 1133 }; 1134 1135 static const struct sdhci_ops sdhci_gl9763e_ops = { 1136 .set_clock = sdhci_set_clock, 1137 .enable_dma = sdhci_pci_enable_dma, 1138 .set_bus_width = sdhci_set_bus_width, 1139 .reset = sdhci_gl9763e_reset, 1140 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 1141 .voltage_switch = sdhci_gli_voltage_switch, 1142 .irq = sdhci_gl9763e_cqhci_irq, 1143 }; 1144 1145 const struct sdhci_pci_fixes sdhci_gl9763e = { 1146 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1147 .probe_slot = gli_probe_slot_gl9763e, 1148 .ops = &sdhci_gl9763e_ops, 1149 #ifdef CONFIG_PM_SLEEP 1150 .resume = sdhci_cqhci_gli_resume, 1151 .suspend = sdhci_cqhci_gli_suspend, 1152 #endif 1153 #ifdef CONFIG_PM 1154 .runtime_suspend = gl9763e_runtime_suspend, 1155 .runtime_resume = gl9763e_runtime_resume, 1156 .allow_runtime_pm = true, 1157 #endif 1158 .add_host = gl9763e_add_host, 1159 }; 1160