1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/iopoll.h> 17 #include "sdhci.h" 18 #include "sdhci-pci.h" 19 #include "cqhci.h" 20 21 /* Genesys Logic extra registers */ 22 #define SDHCI_GLI_9750_WT 0x800 23 #define SDHCI_GLI_9750_WT_EN BIT(0) 24 #define GLI_9750_WT_EN_ON 0x1 25 #define GLI_9750_WT_EN_OFF 0x0 26 27 #define SDHCI_GLI_9750_CFG2 0x848 28 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 29 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 30 31 #define SDHCI_GLI_9750_DRIVING 0x860 32 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 33 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 34 #define GLI_9750_DRIVING_1_VALUE 0xFFF 35 #define GLI_9750_DRIVING_2_VALUE 0x3 36 #define SDHCI_GLI_9750_SEL_1 BIT(29) 37 #define SDHCI_GLI_9750_SEL_2 BIT(31) 38 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 39 40 #define SDHCI_GLI_9750_PLL 0x864 41 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 42 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 43 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 44 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 45 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 46 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 47 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 48 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 49 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 50 51 #define SDHCI_GLI_9750_PLLSSC 0x86C 52 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 53 54 #define SDHCI_GLI_9750_SW_CTRL 0x874 55 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 56 #define GLI_9750_SW_CTRL_4_VALUE 0x3 57 58 #define SDHCI_GLI_9750_MISC 0x878 59 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 60 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 61 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 62 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 63 #define GLI_9750_MISC_RX_INV_ON 0x1 64 #define GLI_9750_MISC_RX_INV_OFF 0x0 65 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 66 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 67 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 68 69 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 70 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 71 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 72 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 73 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 74 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 75 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 76 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 77 78 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 79 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 80 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 81 82 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 83 84 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 85 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 86 87 #define PCIE_GLI_9763E_VHS 0x884 88 #define GLI_9763E_VHS_REV GENMASK(19, 16) 89 #define GLI_9763E_VHS_REV_R 0x0 90 #define GLI_9763E_VHS_REV_M 0x1 91 #define GLI_9763E_VHS_REV_W 0x2 92 #define PCIE_GLI_9763E_MB 0x888 93 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 94 #define GLI_9763E_MB_ERP_ON BIT(7) 95 #define PCIE_GLI_9763E_SCR 0x8E0 96 #define GLI_9763E_SCR_AXI_REQ BIT(9) 97 98 #define PCIE_GLI_9763E_CFG2 0x8A4 99 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 100 #define GLI_9763E_CFG2_L1DLY_MID 0x54 101 102 #define PCIE_GLI_9763E_MMC_CTRL 0x960 103 #define GLI_9763E_HS400_SLOW BIT(3) 104 105 #define PCIE_GLI_9763E_CLKRXDLY 0x934 106 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 107 #define GLI_9763E_HS400_RXDLY_5 0x5 108 109 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 110 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 111 SDHCI_TRNS_BLK_CNT_EN | \ 112 SDHCI_TRNS_DMA) 113 114 #define PCI_GLI_9755_WT 0x800 115 #define PCI_GLI_9755_WT_EN BIT(0) 116 #define GLI_9755_WT_EN_ON 0x1 117 #define GLI_9755_WT_EN_OFF 0x0 118 119 #define PCI_GLI_9755_PECONF 0x44 120 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 121 #define PCI_GLI_9755_DMACLK BIT(29) 122 #define PCI_GLI_9755_INVERT_CD BIT(30) 123 #define PCI_GLI_9755_INVERT_WP BIT(31) 124 125 #define PCI_GLI_9755_CFG2 0x48 126 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 127 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 128 129 #define PCI_GLI_9755_PLL 0x64 130 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 131 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 132 #define PCI_GLI_9755_PLL_DIR BIT(15) 133 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 134 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 135 136 #define PCI_GLI_9755_PLLSSC 0x68 137 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 138 139 #define PCI_GLI_9755_SerDes 0x70 140 #define PCI_GLI_9755_SCP_DIS BIT(19) 141 142 #define PCI_GLI_9755_MISC 0x78 143 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 144 145 #define GLI_MAX_TUNING_LOOP 40 146 147 /* Genesys Logic chipset */ 148 static inline void gl9750_wt_on(struct sdhci_host *host) 149 { 150 u32 wt_value; 151 u32 wt_enable; 152 153 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 154 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 155 156 if (wt_enable == GLI_9750_WT_EN_ON) 157 return; 158 159 wt_value &= ~SDHCI_GLI_9750_WT_EN; 160 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 161 162 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 163 } 164 165 static inline void gl9750_wt_off(struct sdhci_host *host) 166 { 167 u32 wt_value; 168 u32 wt_enable; 169 170 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 171 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 172 173 if (wt_enable == GLI_9750_WT_EN_OFF) 174 return; 175 176 wt_value &= ~SDHCI_GLI_9750_WT_EN; 177 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 178 179 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 180 } 181 182 static void gli_set_9750(struct sdhci_host *host) 183 { 184 u32 driving_value; 185 u32 pll_value; 186 u32 sw_ctrl_value; 187 u32 misc_value; 188 u32 parameter_value; 189 u32 control_value; 190 u16 ctrl2; 191 192 gl9750_wt_on(host); 193 194 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 195 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 196 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 197 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 198 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 199 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 200 201 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 202 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 203 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 204 GLI_9750_DRIVING_1_VALUE); 205 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 206 GLI_9750_DRIVING_2_VALUE); 207 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 208 driving_value |= SDHCI_GLI_9750_SEL_2; 209 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 210 211 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 212 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 213 GLI_9750_SW_CTRL_4_VALUE); 214 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 215 216 /* reset the tuning flow after reinit and before starting tuning */ 217 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 218 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 219 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 220 GLI_9750_PLL_TX2_INV_VALUE); 221 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 222 GLI_9750_PLL_TX2_DLY_VALUE); 223 224 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 225 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 226 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 227 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 228 GLI_9750_MISC_TX1_INV_VALUE); 229 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 230 GLI_9750_MISC_RX_INV_VALUE); 231 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 232 GLI_9750_MISC_TX1_DLY_VALUE); 233 234 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 235 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 236 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 237 238 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 239 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 240 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 241 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 242 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 243 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 244 245 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 246 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 247 248 /* disable tuned clk */ 249 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 250 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 251 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 252 253 /* enable tuning parameters control */ 254 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 255 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 256 GLI_9750_TUNING_CONTROL_EN_ON); 257 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 258 259 /* write tuning parameters */ 260 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 261 262 /* disable tuning parameters control */ 263 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 264 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 265 GLI_9750_TUNING_CONTROL_EN_OFF); 266 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 267 268 /* clear tuned clk */ 269 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 270 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 271 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 272 273 gl9750_wt_off(host); 274 } 275 276 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 277 { 278 u32 misc_value; 279 280 gl9750_wt_on(host); 281 282 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 283 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 284 if (b) { 285 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 286 GLI_9750_MISC_RX_INV_ON); 287 } else { 288 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 289 GLI_9750_MISC_RX_INV_OFF); 290 } 291 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 292 293 gl9750_wt_off(host); 294 } 295 296 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 297 { 298 int i; 299 int rx_inv; 300 301 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 302 gli_set_9750_rx_inv(host, !!rx_inv); 303 sdhci_start_tuning(host); 304 305 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 306 u16 ctrl; 307 308 sdhci_send_tuning(host, opcode); 309 310 if (!host->tuning_done) { 311 sdhci_abort_tuning(host, opcode); 312 break; 313 } 314 315 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 316 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 317 if (ctrl & SDHCI_CTRL_TUNED_CLK) 318 return 0; /* Success! */ 319 break; 320 } 321 } 322 } 323 if (!host->tuning_done) { 324 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 325 mmc_hostname(host->mmc)); 326 return -ETIMEDOUT; 327 } 328 329 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 330 mmc_hostname(host->mmc)); 331 sdhci_reset_tuning(host); 332 333 return -EAGAIN; 334 } 335 336 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 337 { 338 host->mmc->retune_period = 0; 339 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 340 host->mmc->retune_period = host->tuning_count; 341 342 gli_set_9750(host); 343 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 344 sdhci_end_tuning(host); 345 346 return 0; 347 } 348 349 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 350 { 351 u32 pll; 352 353 gl9750_wt_on(host); 354 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 355 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 356 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 357 gl9750_wt_off(host); 358 } 359 360 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 361 { 362 u32 pll; 363 364 gl9750_wt_on(host); 365 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 366 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 367 SDHCI_GLI_9750_PLL_PDIV | 368 SDHCI_GLI_9750_PLL_DIR); 369 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 370 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 371 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 372 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 373 gl9750_wt_off(host); 374 375 /* wait for pll stable */ 376 mdelay(1); 377 } 378 379 static bool gl9750_ssc_enable(struct sdhci_host *host) 380 { 381 u32 misc; 382 u8 off; 383 384 gl9750_wt_on(host); 385 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 386 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 387 gl9750_wt_off(host); 388 389 return !off; 390 } 391 392 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 393 { 394 u32 pll; 395 u32 ssc; 396 397 gl9750_wt_on(host); 398 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 399 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 400 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 401 SDHCI_GLI_9750_PLLSSC_EN); 402 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 403 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 404 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 405 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 406 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 407 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 408 gl9750_wt_off(host); 409 } 410 411 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 412 { 413 bool enable = gl9750_ssc_enable(host); 414 415 /* set pll to 205MHz and ssc */ 416 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 417 gl9750_set_pll(host, 0x1, 0x246, 0x0); 418 } 419 420 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 421 { 422 bool enable = gl9750_ssc_enable(host); 423 424 /* set pll to 100MHz and ssc */ 425 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 426 gl9750_set_pll(host, 0x1, 0x244, 0x1); 427 } 428 429 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 430 { 431 bool enable = gl9750_ssc_enable(host); 432 433 /* set pll to 50MHz and ssc */ 434 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 435 gl9750_set_pll(host, 0x1, 0x244, 0x3); 436 } 437 438 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 439 { 440 struct mmc_ios *ios = &host->mmc->ios; 441 u16 clk; 442 443 host->mmc->actual_clock = 0; 444 445 gl9750_disable_ssc_pll(host); 446 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 447 448 if (clock == 0) 449 return; 450 451 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 452 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 453 host->mmc->actual_clock = 205000000; 454 gl9750_set_ssc_pll_205mhz(host); 455 } else if (clock == 100000000) { 456 gl9750_set_ssc_pll_100mhz(host); 457 } else if (clock == 50000000) { 458 gl9750_set_ssc_pll_50mhz(host); 459 } 460 461 sdhci_enable_clk(host, clk); 462 } 463 464 static void gl9750_hw_setting(struct sdhci_host *host) 465 { 466 u32 value; 467 468 gl9750_wt_on(host); 469 470 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 471 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 472 /* set ASPM L1 entry delay to 7.9us */ 473 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 474 GLI_9750_CFG2_L1DLY_VALUE); 475 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 476 477 gl9750_wt_off(host); 478 } 479 480 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 481 { 482 int ret; 483 484 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 485 PCI_IRQ_MSI | PCI_IRQ_MSIX); 486 if (ret < 0) { 487 pr_warn("%s: enable PCI MSI failed, error=%d\n", 488 mmc_hostname(slot->host->mmc), ret); 489 return; 490 } 491 492 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 493 } 494 495 static inline void gl9755_wt_on(struct pci_dev *pdev) 496 { 497 u32 wt_value; 498 u32 wt_enable; 499 500 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 501 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 502 503 if (wt_enable == GLI_9755_WT_EN_ON) 504 return; 505 506 wt_value &= ~PCI_GLI_9755_WT_EN; 507 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 508 509 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 510 } 511 512 static inline void gl9755_wt_off(struct pci_dev *pdev) 513 { 514 u32 wt_value; 515 u32 wt_enable; 516 517 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 518 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 519 520 if (wt_enable == GLI_9755_WT_EN_OFF) 521 return; 522 523 wt_value &= ~PCI_GLI_9755_WT_EN; 524 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 525 526 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 527 } 528 529 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 530 { 531 u32 pll; 532 533 gl9755_wt_on(pdev); 534 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 535 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 536 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 537 gl9755_wt_off(pdev); 538 } 539 540 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 541 { 542 u32 pll; 543 544 gl9755_wt_on(pdev); 545 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 546 pll &= ~(PCI_GLI_9755_PLL_LDIV | 547 PCI_GLI_9755_PLL_PDIV | 548 PCI_GLI_9755_PLL_DIR); 549 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 550 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 551 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 552 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 553 gl9755_wt_off(pdev); 554 555 /* wait for pll stable */ 556 mdelay(1); 557 } 558 559 static bool gl9755_ssc_enable(struct pci_dev *pdev) 560 { 561 u32 misc; 562 u8 off; 563 564 gl9755_wt_on(pdev); 565 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 566 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 567 gl9755_wt_off(pdev); 568 569 return !off; 570 } 571 572 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 573 { 574 u32 pll; 575 u32 ssc; 576 577 gl9755_wt_on(pdev); 578 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 579 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 580 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 581 PCI_GLI_9755_PLLSSC_EN); 582 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 583 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 584 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 585 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 586 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 587 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 588 gl9755_wt_off(pdev); 589 } 590 591 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 592 { 593 bool enable = gl9755_ssc_enable(pdev); 594 595 /* set pll to 205MHz and ssc */ 596 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 597 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 598 } 599 600 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 601 { 602 bool enable = gl9755_ssc_enable(pdev); 603 604 /* set pll to 100MHz and ssc */ 605 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 606 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 607 } 608 609 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 610 { 611 bool enable = gl9755_ssc_enable(pdev); 612 613 /* set pll to 50MHz and ssc */ 614 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 615 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 616 } 617 618 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 619 { 620 struct sdhci_pci_slot *slot = sdhci_priv(host); 621 struct mmc_ios *ios = &host->mmc->ios; 622 struct pci_dev *pdev; 623 u16 clk; 624 625 pdev = slot->chip->pdev; 626 host->mmc->actual_clock = 0; 627 628 gl9755_disable_ssc_pll(pdev); 629 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 630 631 if (clock == 0) 632 return; 633 634 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 635 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 636 host->mmc->actual_clock = 205000000; 637 gl9755_set_ssc_pll_205mhz(pdev); 638 } else if (clock == 100000000) { 639 gl9755_set_ssc_pll_100mhz(pdev); 640 } else if (clock == 50000000) { 641 gl9755_set_ssc_pll_50mhz(pdev); 642 } 643 644 sdhci_enable_clk(host, clk); 645 } 646 647 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 648 { 649 struct pci_dev *pdev = slot->chip->pdev; 650 u32 value; 651 652 gl9755_wt_on(pdev); 653 654 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 655 /* 656 * Apple ARM64 platforms using these chips may have 657 * inverted CD/WP detection. 658 */ 659 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 660 value |= PCI_GLI_9755_INVERT_CD; 661 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 662 value |= PCI_GLI_9755_INVERT_WP; 663 value &= ~PCI_GLI_9755_LFCLK; 664 value &= ~PCI_GLI_9755_DMACLK; 665 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 666 667 /* enable short circuit protection */ 668 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 669 value &= ~PCI_GLI_9755_SCP_DIS; 670 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 671 672 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 673 value &= ~PCI_GLI_9755_CFG2_L1DLY; 674 /* set ASPM L1 entry delay to 7.9us */ 675 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 676 GLI_9755_CFG2_L1DLY_VALUE); 677 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 678 679 gl9755_wt_off(pdev); 680 } 681 682 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 683 { 684 struct sdhci_host *host = slot->host; 685 686 gl9750_hw_setting(host); 687 gli_pcie_enable_msi(slot); 688 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 689 sdhci_enable_v4_mode(host); 690 691 return 0; 692 } 693 694 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 695 { 696 struct sdhci_host *host = slot->host; 697 698 gl9755_hw_setting(slot); 699 gli_pcie_enable_msi(slot); 700 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 701 sdhci_enable_v4_mode(host); 702 703 return 0; 704 } 705 706 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 707 { 708 /* 709 * According to Section 3.6.1 signal voltage switch procedure in 710 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 711 * follows: 712 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 713 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 714 * period. 715 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 716 * step (12). 717 * 718 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 719 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 720 * 721 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 722 * slightly longer than 5ms before the control register reports that 723 * 1.8V is ready, and far longer still before the card will actually 724 * work reliably. 725 */ 726 usleep_range(100000, 110000); 727 } 728 729 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 730 { 731 sdhci_reset(host, mask); 732 gli_set_9750(host); 733 } 734 735 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 736 { 737 u32 value; 738 739 value = readl(host->ioaddr + reg); 740 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 741 value |= 0xc8; 742 743 return value; 744 } 745 746 #ifdef CONFIG_PM_SLEEP 747 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 748 { 749 struct sdhci_pci_slot *slot = chip->slots[0]; 750 751 pci_free_irq_vectors(slot->chip->pdev); 752 gli_pcie_enable_msi(slot); 753 754 return sdhci_pci_resume_host(chip); 755 } 756 757 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip) 758 { 759 struct sdhci_pci_slot *slot = chip->slots[0]; 760 int ret; 761 762 ret = sdhci_pci_gli_resume(chip); 763 if (ret) 764 return ret; 765 766 return cqhci_resume(slot->host->mmc); 767 } 768 769 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip) 770 { 771 struct sdhci_pci_slot *slot = chip->slots[0]; 772 int ret; 773 774 ret = cqhci_suspend(slot->host->mmc); 775 if (ret) 776 return ret; 777 778 return sdhci_suspend_host(slot->host); 779 } 780 #endif 781 782 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 783 struct mmc_ios *ios) 784 { 785 struct sdhci_host *host = mmc_priv(mmc); 786 u32 val; 787 788 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 789 if (ios->enhanced_strobe) 790 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 791 else 792 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 793 794 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 795 } 796 797 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 798 unsigned int timing) 799 { 800 u16 ctrl_2; 801 802 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 803 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 804 if (timing == MMC_TIMING_MMC_HS200) 805 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 806 else if (timing == MMC_TIMING_MMC_HS) 807 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 808 else if (timing == MMC_TIMING_MMC_DDR52) 809 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 810 else if (timing == MMC_TIMING_MMC_HS400) 811 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 812 813 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 814 } 815 816 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 817 { 818 sdhci_dumpregs(mmc_priv(mmc)); 819 } 820 821 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 822 { 823 struct cqhci_host *cq_host = mmc->cqe_private; 824 u32 value; 825 826 value = cqhci_readl(cq_host, CQHCI_CFG); 827 value |= CQHCI_ENABLE; 828 cqhci_writel(cq_host, value, CQHCI_CFG); 829 } 830 831 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 832 { 833 struct sdhci_host *host = mmc_priv(mmc); 834 835 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 836 sdhci_cqe_enable(mmc); 837 } 838 839 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 840 { 841 int cmd_error = 0; 842 int data_error = 0; 843 844 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 845 return intmask; 846 847 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 848 849 return 0; 850 } 851 852 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 853 { 854 struct sdhci_host *host = mmc_priv(mmc); 855 struct cqhci_host *cq_host = mmc->cqe_private; 856 u32 value; 857 858 value = cqhci_readl(cq_host, CQHCI_CFG); 859 value &= ~CQHCI_ENABLE; 860 cqhci_writel(cq_host, value, CQHCI_CFG); 861 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 862 } 863 864 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 865 .enable = sdhci_gl9763e_cqe_enable, 866 .disable = sdhci_cqe_disable, 867 .dumpregs = sdhci_gl9763e_dumpregs, 868 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 869 .post_disable = sdhci_gl9763e_cqe_post_disable, 870 }; 871 872 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 873 { 874 struct device *dev = &slot->chip->pdev->dev; 875 struct sdhci_host *host = slot->host; 876 struct cqhci_host *cq_host; 877 bool dma64; 878 int ret; 879 880 ret = sdhci_setup_host(host); 881 if (ret) 882 return ret; 883 884 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 885 if (!cq_host) { 886 ret = -ENOMEM; 887 goto cleanup; 888 } 889 890 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 891 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 892 893 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 894 if (dma64) 895 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 896 897 ret = cqhci_init(cq_host, host->mmc, dma64); 898 if (ret) 899 goto cleanup; 900 901 ret = __sdhci_add_host(host); 902 if (ret) 903 goto cleanup; 904 905 return 0; 906 907 cleanup: 908 sdhci_cleanup_host(host); 909 return ret; 910 } 911 912 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask) 913 { 914 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 915 host->mmc->cqe_private) 916 cqhci_deactivate(host->mmc); 917 sdhci_reset(host, mask); 918 } 919 920 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 921 { 922 struct pci_dev *pdev = slot->chip->pdev; 923 u32 value; 924 925 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 926 value &= ~GLI_9763E_VHS_REV; 927 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 928 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 929 930 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 931 value |= GLI_9763E_SCR_AXI_REQ; 932 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 933 934 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 935 value &= ~GLI_9763E_HS400_SLOW; 936 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 937 938 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 939 value &= ~GLI_9763E_CFG2_L1DLY; 940 /* set ASPM L1 entry delay to 21us */ 941 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 942 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 943 944 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 945 value &= ~GLI_9763E_HS400_RXDLY; 946 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 947 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 948 949 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 950 value &= ~GLI_9763E_VHS_REV; 951 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 952 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 953 } 954 955 #ifdef CONFIG_PM 956 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 957 { 958 struct sdhci_pci_slot *slot = chip->slots[0]; 959 struct sdhci_host *host = slot->host; 960 u16 clock; 961 962 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 963 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 964 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 965 966 return 0; 967 } 968 969 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 970 { 971 struct sdhci_pci_slot *slot = chip->slots[0]; 972 struct sdhci_host *host = slot->host; 973 u16 clock; 974 975 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 976 977 clock |= SDHCI_CLOCK_PLL_EN; 978 clock &= ~SDHCI_CLOCK_INT_STABLE; 979 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 980 981 /* Wait max 150 ms */ 982 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 983 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 984 pr_err("%s: PLL clock never stabilised.\n", 985 mmc_hostname(host->mmc)); 986 sdhci_dumpregs(host); 987 } 988 989 clock |= SDHCI_CLOCK_CARD_EN; 990 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 991 992 return 0; 993 } 994 #endif 995 996 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 997 { 998 struct pci_dev *pdev = slot->chip->pdev; 999 struct sdhci_host *host = slot->host; 1000 u32 value; 1001 1002 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1003 MMC_CAP_1_8V_DDR | 1004 MMC_CAP_NONREMOVABLE; 1005 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1006 MMC_CAP2_HS400_1_8V | 1007 MMC_CAP2_HS400_ES | 1008 MMC_CAP2_NO_SDIO | 1009 MMC_CAP2_NO_SD; 1010 1011 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1012 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 1013 if (value & GLI_9763E_MB_ERP_ON) 1014 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1015 1016 gli_pcie_enable_msi(slot); 1017 host->mmc_host_ops.hs400_enhanced_strobe = 1018 gl9763e_hs400_enhanced_strobe; 1019 gli_set_gl9763e(slot); 1020 sdhci_enable_v4_mode(host); 1021 1022 return 0; 1023 } 1024 1025 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 1026 1027 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 1028 { 1029 u32 val = readl(host->ioaddr + (reg & ~3)); 1030 u16 word; 1031 1032 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 1033 return word; 1034 } 1035 1036 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 1037 { 1038 u32 val = readl(host->ioaddr + (reg & ~3)); 1039 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 1040 1041 return byte; 1042 } 1043 1044 static const struct sdhci_ops sdhci_gl9755_ops = { 1045 .read_w = sdhci_gli_readw, 1046 .read_b = sdhci_gli_readb, 1047 .set_clock = sdhci_gl9755_set_clock, 1048 .enable_dma = sdhci_pci_enable_dma, 1049 .set_bus_width = sdhci_set_bus_width, 1050 .reset = sdhci_reset, 1051 .set_uhs_signaling = sdhci_set_uhs_signaling, 1052 .voltage_switch = sdhci_gli_voltage_switch, 1053 }; 1054 1055 const struct sdhci_pci_fixes sdhci_gl9755 = { 1056 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1057 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1058 .probe_slot = gli_probe_slot_gl9755, 1059 .ops = &sdhci_gl9755_ops, 1060 #ifdef CONFIG_PM_SLEEP 1061 .resume = sdhci_pci_gli_resume, 1062 #endif 1063 }; 1064 1065 static const struct sdhci_ops sdhci_gl9750_ops = { 1066 .read_w = sdhci_gli_readw, 1067 .read_b = sdhci_gli_readb, 1068 .read_l = sdhci_gl9750_readl, 1069 .set_clock = sdhci_gl9750_set_clock, 1070 .enable_dma = sdhci_pci_enable_dma, 1071 .set_bus_width = sdhci_set_bus_width, 1072 .reset = sdhci_gl9750_reset, 1073 .set_uhs_signaling = sdhci_set_uhs_signaling, 1074 .voltage_switch = sdhci_gli_voltage_switch, 1075 .platform_execute_tuning = gl9750_execute_tuning, 1076 }; 1077 1078 const struct sdhci_pci_fixes sdhci_gl9750 = { 1079 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1080 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1081 .probe_slot = gli_probe_slot_gl9750, 1082 .ops = &sdhci_gl9750_ops, 1083 #ifdef CONFIG_PM_SLEEP 1084 .resume = sdhci_pci_gli_resume, 1085 #endif 1086 }; 1087 1088 static const struct sdhci_ops sdhci_gl9763e_ops = { 1089 .set_clock = sdhci_set_clock, 1090 .enable_dma = sdhci_pci_enable_dma, 1091 .set_bus_width = sdhci_set_bus_width, 1092 .reset = sdhci_gl9763e_reset, 1093 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 1094 .voltage_switch = sdhci_gli_voltage_switch, 1095 .irq = sdhci_gl9763e_cqhci_irq, 1096 }; 1097 1098 const struct sdhci_pci_fixes sdhci_gl9763e = { 1099 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1100 .probe_slot = gli_probe_slot_gl9763e, 1101 .ops = &sdhci_gl9763e_ops, 1102 #ifdef CONFIG_PM_SLEEP 1103 .resume = sdhci_cqhci_gli_resume, 1104 .suspend = sdhci_cqhci_gli_suspend, 1105 #endif 1106 #ifdef CONFIG_PM 1107 .runtime_suspend = gl9763e_runtime_suspend, 1108 .runtime_resume = gl9763e_runtime_resume, 1109 .allow_runtime_pm = true, 1110 #endif 1111 .add_host = gl9763e_add_host, 1112 }; 1113