1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/iopoll.h> 17 #include "sdhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pci.h" 20 #include "cqhci.h" 21 22 /* Genesys Logic extra registers */ 23 #define SDHCI_GLI_9750_WT 0x800 24 #define SDHCI_GLI_9750_WT_EN BIT(0) 25 #define GLI_9750_WT_EN_ON 0x1 26 #define GLI_9750_WT_EN_OFF 0x0 27 28 #define SDHCI_GLI_9750_CFG2 0x848 29 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 30 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 31 32 #define SDHCI_GLI_9750_DRIVING 0x860 33 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 34 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 35 #define GLI_9750_DRIVING_1_VALUE 0xFFF 36 #define GLI_9750_DRIVING_2_VALUE 0x3 37 #define SDHCI_GLI_9750_SEL_1 BIT(29) 38 #define SDHCI_GLI_9750_SEL_2 BIT(31) 39 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 40 41 #define SDHCI_GLI_9750_PLL 0x864 42 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 43 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 44 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 45 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 46 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 47 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 48 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 49 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 50 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 51 52 #define SDHCI_GLI_9750_PLLSSC 0x86C 53 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 54 55 #define SDHCI_GLI_9750_SW_CTRL 0x874 56 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 57 #define GLI_9750_SW_CTRL_4_VALUE 0x3 58 59 #define SDHCI_GLI_9750_MISC 0x878 60 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 61 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 62 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 63 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 64 #define GLI_9750_MISC_RX_INV_ON 0x1 65 #define GLI_9750_MISC_RX_INV_OFF 0x0 66 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 67 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 68 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 69 70 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 71 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 72 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 73 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 74 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 75 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 76 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 77 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 78 79 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 80 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 81 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 82 83 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 84 85 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 86 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 87 88 #define PCIE_GLI_9763E_VHS 0x884 89 #define GLI_9763E_VHS_REV GENMASK(19, 16) 90 #define GLI_9763E_VHS_REV_R 0x0 91 #define GLI_9763E_VHS_REV_M 0x1 92 #define GLI_9763E_VHS_REV_W 0x2 93 #define PCIE_GLI_9763E_MB 0x888 94 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 95 #define GLI_9763E_MB_ERP_ON BIT(7) 96 #define PCIE_GLI_9763E_SCR 0x8E0 97 #define GLI_9763E_SCR_AXI_REQ BIT(9) 98 99 #define PCIE_GLI_9763E_CFG 0x8A0 100 #define GLI_9763E_CFG_LPSN_DIS BIT(12) 101 102 #define PCIE_GLI_9763E_CFG2 0x8A4 103 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 104 #define GLI_9763E_CFG2_L1DLY_MID 0x54 105 106 #define PCIE_GLI_9763E_MMC_CTRL 0x960 107 #define GLI_9763E_HS400_SLOW BIT(3) 108 109 #define PCIE_GLI_9763E_CLKRXDLY 0x934 110 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 111 #define GLI_9763E_HS400_RXDLY_5 0x5 112 113 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 114 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 115 SDHCI_TRNS_BLK_CNT_EN | \ 116 SDHCI_TRNS_DMA) 117 118 #define PCI_GLI_9755_WT 0x800 119 #define PCI_GLI_9755_WT_EN BIT(0) 120 #define GLI_9755_WT_EN_ON 0x1 121 #define GLI_9755_WT_EN_OFF 0x0 122 123 #define PCI_GLI_9755_PECONF 0x44 124 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 125 #define PCI_GLI_9755_DMACLK BIT(29) 126 #define PCI_GLI_9755_INVERT_CD BIT(30) 127 #define PCI_GLI_9755_INVERT_WP BIT(31) 128 129 #define PCI_GLI_9755_CFG2 0x48 130 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 131 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 132 133 #define PCI_GLI_9755_PLL 0x64 134 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 135 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 136 #define PCI_GLI_9755_PLL_DIR BIT(15) 137 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 138 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 139 140 #define PCI_GLI_9755_PLLSSC 0x68 141 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 142 143 #define PCI_GLI_9755_SerDes 0x70 144 #define PCI_GLI_9755_SCP_DIS BIT(19) 145 146 #define PCI_GLI_9755_MISC 0x78 147 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 148 149 #define PCI_GLI_9755_PM_CTRL 0xFC 150 #define PCI_GLI_9755_PM_STATE GENMASK(1, 0) 151 152 #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 153 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) 154 155 #define PCIE_GLI_9767_VHS 0x884 156 #define GLI_9767_VHS_REV GENMASK(19, 16) 157 #define GLI_9767_VHS_REV_R 0x0 158 #define GLI_9767_VHS_REV_M 0x1 159 #define GLI_9767_VHS_REV_W 0x2 160 161 #define PCIE_GLI_9767_COM_MAILBOX 0x888 162 #define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1) 163 164 #define PCIE_GLI_9767_CFG 0x8A0 165 #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12) 166 167 #define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8 168 #define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6) 169 #define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10) 170 171 #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0 172 #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0) 173 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12) 174 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7 175 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28) 176 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3 177 178 #define PCIE_GLI_9767_SCR 0x8E0 179 #define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6) 180 #define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7) 181 #define PCIE_GLI_9767_SCR_AXI_REQ BIT(9) 182 #define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10) 183 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16) 184 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17) 185 #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) 186 #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) 187 188 #define PCIE_GLI_9767_SDHC_CAP 0x91C 189 #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) 190 191 #define PCIE_GLI_9767_SD_PLL_CTL 0x938 192 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0) 193 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12) 194 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16) 195 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19) 196 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24) 197 198 #define PCIE_GLI_9767_SD_PLL_CTL2 0x93C 199 #define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16) 200 201 #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940 202 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0) 203 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) 204 205 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 206 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) 207 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 208 209 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 210 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) 211 212 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954 213 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0) 214 215 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 216 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) 217 218 #define GLI_MAX_TUNING_LOOP 40 219 220 /* Genesys Logic chipset */ 221 static inline void gl9750_wt_on(struct sdhci_host *host) 222 { 223 u32 wt_value; 224 u32 wt_enable; 225 226 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 227 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 228 229 if (wt_enable == GLI_9750_WT_EN_ON) 230 return; 231 232 wt_value &= ~SDHCI_GLI_9750_WT_EN; 233 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 234 235 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 236 } 237 238 static inline void gl9750_wt_off(struct sdhci_host *host) 239 { 240 u32 wt_value; 241 u32 wt_enable; 242 243 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 244 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 245 246 if (wt_enable == GLI_9750_WT_EN_OFF) 247 return; 248 249 wt_value &= ~SDHCI_GLI_9750_WT_EN; 250 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 251 252 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 253 } 254 255 static void gli_set_9750(struct sdhci_host *host) 256 { 257 u32 driving_value; 258 u32 pll_value; 259 u32 sw_ctrl_value; 260 u32 misc_value; 261 u32 parameter_value; 262 u32 control_value; 263 u16 ctrl2; 264 265 gl9750_wt_on(host); 266 267 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 268 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 269 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 270 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 271 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 272 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 273 274 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 275 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 276 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 277 GLI_9750_DRIVING_1_VALUE); 278 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 279 GLI_9750_DRIVING_2_VALUE); 280 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 281 driving_value |= SDHCI_GLI_9750_SEL_2; 282 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 283 284 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 285 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 286 GLI_9750_SW_CTRL_4_VALUE); 287 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 288 289 /* reset the tuning flow after reinit and before starting tuning */ 290 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 291 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 292 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 293 GLI_9750_PLL_TX2_INV_VALUE); 294 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 295 GLI_9750_PLL_TX2_DLY_VALUE); 296 297 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 298 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 299 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 300 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 301 GLI_9750_MISC_TX1_INV_VALUE); 302 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 303 GLI_9750_MISC_RX_INV_VALUE); 304 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 305 GLI_9750_MISC_TX1_DLY_VALUE); 306 307 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 308 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 309 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 310 311 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 312 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 313 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 314 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 315 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 316 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 317 318 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 319 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 320 321 /* disable tuned clk */ 322 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 323 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 324 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 325 326 /* enable tuning parameters control */ 327 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 328 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 329 GLI_9750_TUNING_CONTROL_EN_ON); 330 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 331 332 /* write tuning parameters */ 333 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 334 335 /* disable tuning parameters control */ 336 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 337 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 338 GLI_9750_TUNING_CONTROL_EN_OFF); 339 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 340 341 /* clear tuned clk */ 342 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 343 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 344 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 345 346 gl9750_wt_off(host); 347 } 348 349 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 350 { 351 u32 misc_value; 352 353 gl9750_wt_on(host); 354 355 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 356 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 357 if (b) { 358 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 359 GLI_9750_MISC_RX_INV_ON); 360 } else { 361 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 362 GLI_9750_MISC_RX_INV_OFF); 363 } 364 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 365 366 gl9750_wt_off(host); 367 } 368 369 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 370 { 371 int i; 372 int rx_inv; 373 374 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 375 gli_set_9750_rx_inv(host, !!rx_inv); 376 sdhci_start_tuning(host); 377 378 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 379 u16 ctrl; 380 381 sdhci_send_tuning(host, opcode); 382 383 if (!host->tuning_done) { 384 sdhci_abort_tuning(host, opcode); 385 break; 386 } 387 388 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 389 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 390 if (ctrl & SDHCI_CTRL_TUNED_CLK) 391 return 0; /* Success! */ 392 break; 393 } 394 } 395 } 396 if (!host->tuning_done) { 397 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 398 mmc_hostname(host->mmc)); 399 return -ETIMEDOUT; 400 } 401 402 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 403 mmc_hostname(host->mmc)); 404 sdhci_reset_tuning(host); 405 406 return -EAGAIN; 407 } 408 409 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 410 { 411 host->mmc->retune_period = 0; 412 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 413 host->mmc->retune_period = host->tuning_count; 414 415 gli_set_9750(host); 416 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 417 sdhci_end_tuning(host); 418 419 return 0; 420 } 421 422 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 423 { 424 u32 pll; 425 426 gl9750_wt_on(host); 427 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 428 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 429 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 430 gl9750_wt_off(host); 431 } 432 433 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 434 { 435 u32 pll; 436 437 gl9750_wt_on(host); 438 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 439 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 440 SDHCI_GLI_9750_PLL_PDIV | 441 SDHCI_GLI_9750_PLL_DIR); 442 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 443 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 444 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 445 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 446 gl9750_wt_off(host); 447 448 /* wait for pll stable */ 449 mdelay(1); 450 } 451 452 static bool gl9750_ssc_enable(struct sdhci_host *host) 453 { 454 u32 misc; 455 u8 off; 456 457 gl9750_wt_on(host); 458 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 459 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 460 gl9750_wt_off(host); 461 462 return !off; 463 } 464 465 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 466 { 467 u32 pll; 468 u32 ssc; 469 470 gl9750_wt_on(host); 471 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 472 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 473 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 474 SDHCI_GLI_9750_PLLSSC_EN); 475 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 476 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 477 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 478 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 479 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 480 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 481 gl9750_wt_off(host); 482 } 483 484 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 485 { 486 bool enable = gl9750_ssc_enable(host); 487 488 /* set pll to 205MHz and ssc */ 489 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 490 gl9750_set_pll(host, 0x1, 0x246, 0x0); 491 } 492 493 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 494 { 495 bool enable = gl9750_ssc_enable(host); 496 497 /* set pll to 100MHz and ssc */ 498 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 499 gl9750_set_pll(host, 0x1, 0x244, 0x1); 500 } 501 502 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 503 { 504 bool enable = gl9750_ssc_enable(host); 505 506 /* set pll to 50MHz and ssc */ 507 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 508 gl9750_set_pll(host, 0x1, 0x244, 0x3); 509 } 510 511 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 512 { 513 struct mmc_ios *ios = &host->mmc->ios; 514 u16 clk; 515 516 host->mmc->actual_clock = 0; 517 518 gl9750_disable_ssc_pll(host); 519 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 520 521 if (clock == 0) 522 return; 523 524 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 525 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 526 host->mmc->actual_clock = 205000000; 527 gl9750_set_ssc_pll_205mhz(host); 528 } else if (clock == 100000000) { 529 gl9750_set_ssc_pll_100mhz(host); 530 } else if (clock == 50000000) { 531 gl9750_set_ssc_pll_50mhz(host); 532 } 533 534 sdhci_enable_clk(host, clk); 535 } 536 537 static void gl9750_hw_setting(struct sdhci_host *host) 538 { 539 u32 value; 540 541 gl9750_wt_on(host); 542 543 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 544 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 545 /* set ASPM L1 entry delay to 7.9us */ 546 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 547 GLI_9750_CFG2_L1DLY_VALUE); 548 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 549 550 gl9750_wt_off(host); 551 } 552 553 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 554 { 555 int ret; 556 557 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 558 PCI_IRQ_MSI | PCI_IRQ_MSIX); 559 if (ret < 0) { 560 pr_warn("%s: enable PCI MSI failed, error=%d\n", 561 mmc_hostname(slot->host->mmc), ret); 562 return; 563 } 564 565 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 566 } 567 568 static inline void gl9755_wt_on(struct pci_dev *pdev) 569 { 570 u32 wt_value; 571 u32 wt_enable; 572 573 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 574 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 575 576 if (wt_enable == GLI_9755_WT_EN_ON) 577 return; 578 579 wt_value &= ~PCI_GLI_9755_WT_EN; 580 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 581 582 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 583 } 584 585 static inline void gl9755_wt_off(struct pci_dev *pdev) 586 { 587 u32 wt_value; 588 u32 wt_enable; 589 590 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 591 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 592 593 if (wt_enable == GLI_9755_WT_EN_OFF) 594 return; 595 596 wt_value &= ~PCI_GLI_9755_WT_EN; 597 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 598 599 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 600 } 601 602 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 603 { 604 u32 pll; 605 606 gl9755_wt_on(pdev); 607 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 608 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 609 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 610 gl9755_wt_off(pdev); 611 } 612 613 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 614 { 615 u32 pll; 616 617 gl9755_wt_on(pdev); 618 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 619 pll &= ~(PCI_GLI_9755_PLL_LDIV | 620 PCI_GLI_9755_PLL_PDIV | 621 PCI_GLI_9755_PLL_DIR); 622 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 623 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 624 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 625 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 626 gl9755_wt_off(pdev); 627 628 /* wait for pll stable */ 629 mdelay(1); 630 } 631 632 static bool gl9755_ssc_enable(struct pci_dev *pdev) 633 { 634 u32 misc; 635 u8 off; 636 637 gl9755_wt_on(pdev); 638 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 639 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 640 gl9755_wt_off(pdev); 641 642 return !off; 643 } 644 645 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 646 { 647 u32 pll; 648 u32 ssc; 649 650 gl9755_wt_on(pdev); 651 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 652 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 653 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 654 PCI_GLI_9755_PLLSSC_EN); 655 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 656 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 657 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 658 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 659 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 660 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 661 gl9755_wt_off(pdev); 662 } 663 664 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 665 { 666 bool enable = gl9755_ssc_enable(pdev); 667 668 /* set pll to 205MHz and ssc */ 669 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 670 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 671 } 672 673 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 674 { 675 bool enable = gl9755_ssc_enable(pdev); 676 677 /* set pll to 100MHz and ssc */ 678 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 679 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 680 } 681 682 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 683 { 684 bool enable = gl9755_ssc_enable(pdev); 685 686 /* set pll to 50MHz and ssc */ 687 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 688 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 689 } 690 691 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 692 { 693 struct sdhci_pci_slot *slot = sdhci_priv(host); 694 struct mmc_ios *ios = &host->mmc->ios; 695 struct pci_dev *pdev; 696 u16 clk; 697 698 pdev = slot->chip->pdev; 699 host->mmc->actual_clock = 0; 700 701 gl9755_disable_ssc_pll(pdev); 702 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 703 704 if (clock == 0) 705 return; 706 707 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 708 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 709 host->mmc->actual_clock = 205000000; 710 gl9755_set_ssc_pll_205mhz(pdev); 711 } else if (clock == 100000000) { 712 gl9755_set_ssc_pll_100mhz(pdev); 713 } else if (clock == 50000000) { 714 gl9755_set_ssc_pll_50mhz(pdev); 715 } 716 717 sdhci_enable_clk(host, clk); 718 } 719 720 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 721 { 722 struct pci_dev *pdev = slot->chip->pdev; 723 u32 value; 724 725 gl9755_wt_on(pdev); 726 727 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 728 /* 729 * Apple ARM64 platforms using these chips may have 730 * inverted CD/WP detection. 731 */ 732 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 733 value |= PCI_GLI_9755_INVERT_CD; 734 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 735 value |= PCI_GLI_9755_INVERT_WP; 736 value &= ~PCI_GLI_9755_LFCLK; 737 value &= ~PCI_GLI_9755_DMACLK; 738 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 739 740 /* enable short circuit protection */ 741 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 742 value &= ~PCI_GLI_9755_SCP_DIS; 743 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 744 745 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 746 value &= ~PCI_GLI_9755_CFG2_L1DLY; 747 /* set ASPM L1 entry delay to 7.9us */ 748 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 749 GLI_9755_CFG2_L1DLY_VALUE); 750 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 751 752 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 753 pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); 754 value |= PCI_GLI_9755_PM_STATE; 755 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 756 value &= ~PCI_GLI_9755_PM_STATE; 757 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 758 759 gl9755_wt_off(pdev); 760 } 761 762 static inline void gl9767_vhs_read(struct pci_dev *pdev) 763 { 764 u32 vhs_enable; 765 u32 vhs_value; 766 767 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 768 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 769 770 if (vhs_enable == GLI_9767_VHS_REV_R) 771 return; 772 773 vhs_value &= ~GLI_9767_VHS_REV; 774 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R); 775 776 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 777 } 778 779 static inline void gl9767_vhs_write(struct pci_dev *pdev) 780 { 781 u32 vhs_enable; 782 u32 vhs_value; 783 784 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 785 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 786 787 if (vhs_enable == GLI_9767_VHS_REV_W) 788 return; 789 790 vhs_value &= ~GLI_9767_VHS_REV; 791 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W); 792 793 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 794 } 795 796 static bool gl9767_ssc_enable(struct pci_dev *pdev) 797 { 798 u32 value; 799 u8 enable; 800 801 gl9767_vhs_write(pdev); 802 803 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value); 804 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); 805 806 gl9767_vhs_read(pdev); 807 808 return enable; 809 } 810 811 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 812 { 813 u32 pll; 814 u32 ssc; 815 816 gl9767_vhs_write(pdev); 817 818 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 819 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); 820 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING | 821 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 822 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; 823 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) | 824 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); 825 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); 826 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); 827 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 828 829 gl9767_vhs_read(pdev); 830 } 831 832 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 833 { 834 u32 pll; 835 836 gl9767_vhs_write(pdev); 837 838 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 839 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV | 840 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV | 841 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN); 842 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) | 843 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) | 844 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir); 845 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 846 847 gl9767_vhs_read(pdev); 848 849 /* wait for pll stable */ 850 usleep_range(1000, 1100); 851 } 852 853 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev) 854 { 855 bool enable = gl9767_ssc_enable(pdev); 856 857 /* set pll to 205MHz and ssc */ 858 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); 859 gl9767_set_pll(pdev, 0x1, 0x246, 0x0); 860 } 861 862 static void gl9767_disable_ssc_pll(struct pci_dev *pdev) 863 { 864 u32 pll; 865 866 gl9767_vhs_write(pdev); 867 868 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 869 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 870 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 871 872 gl9767_vhs_read(pdev); 873 } 874 875 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) 876 { 877 struct sdhci_pci_slot *slot = sdhci_priv(host); 878 struct mmc_ios *ios = &host->mmc->ios; 879 struct pci_dev *pdev; 880 u32 value; 881 u16 clk; 882 883 pdev = slot->chip->pdev; 884 host->mmc->actual_clock = 0; 885 886 gl9767_vhs_write(pdev); 887 888 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 889 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 890 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 891 892 gl9767_disable_ssc_pll(pdev); 893 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 894 895 if (clock == 0) 896 return; 897 898 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 899 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 900 host->mmc->actual_clock = 205000000; 901 gl9767_set_ssc_pll_205mhz(pdev); 902 } 903 904 sdhci_enable_clk(host, clk); 905 906 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 907 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 908 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 909 910 gl9767_vhs_read(pdev); 911 } 912 913 static void gli_set_9767(struct sdhci_host *host) 914 { 915 u32 value; 916 917 value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE); 918 value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; 919 sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE); 920 } 921 922 static void gl9767_hw_setting(struct sdhci_pci_slot *slot) 923 { 924 struct pci_dev *pdev = slot->chip->pdev; 925 u32 value; 926 927 gl9767_vhs_write(pdev); 928 929 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value); 930 value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 931 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE | 932 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL); 933 934 value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 935 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE, 936 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) | 937 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL, 938 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE); 939 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value); 940 941 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value); 942 value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 | 943 PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 | 944 PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN); 945 946 value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST | 947 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST | 948 PCIE_GLI_9767_SCR_AXI_REQ | 949 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN | 950 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF; 951 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value); 952 953 gl9767_vhs_read(pdev); 954 } 955 956 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) 957 { 958 sdhci_reset(host, mask); 959 gli_set_9767(host); 960 } 961 962 static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 963 { 964 struct sdhci_host *host = mmc_priv(mmc); 965 struct sdhci_pci_slot *slot = sdhci_priv(host); 966 struct pci_dev *pdev; 967 u32 value; 968 int i; 969 970 pdev = slot->chip->pdev; 971 972 if (mmc->ops->get_ro(mmc)) { 973 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 974 return 0; 975 } 976 977 gl9767_vhs_write(pdev); 978 979 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value); 980 value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN); 981 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value); 982 983 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 984 value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME; 985 value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME, 986 PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE); 987 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 988 989 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 990 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE; 991 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value); 992 993 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value); 994 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN; 995 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value); 996 997 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value); 998 value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN; 999 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value); 1000 1001 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1002 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1003 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1004 1005 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1006 value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1007 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1008 1009 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1010 value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1011 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1012 1013 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1014 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE; 1015 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1016 1017 for (i = 0; i < 2; i++) { 1018 usleep_range(10000, 10100); 1019 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1020 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) { 1021 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, 1022 value); 1023 break; 1024 } 1025 } 1026 1027 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value); 1028 if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) { 1029 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1030 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE; 1031 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1032 } else { 1033 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1034 1035 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1036 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1037 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1038 1039 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1040 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1041 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1042 } 1043 1044 gl9767_vhs_read(pdev); 1045 1046 return 0; 1047 } 1048 1049 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 1050 { 1051 struct sdhci_host *host = slot->host; 1052 1053 gl9750_hw_setting(host); 1054 gli_pcie_enable_msi(slot); 1055 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1056 sdhci_enable_v4_mode(host); 1057 1058 return 0; 1059 } 1060 1061 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 1062 { 1063 struct sdhci_host *host = slot->host; 1064 1065 gl9755_hw_setting(slot); 1066 gli_pcie_enable_msi(slot); 1067 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1068 sdhci_enable_v4_mode(host); 1069 1070 return 0; 1071 } 1072 1073 static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot) 1074 { 1075 struct sdhci_host *host = slot->host; 1076 1077 gli_set_9767(host); 1078 gl9767_hw_setting(slot); 1079 gli_pcie_enable_msi(slot); 1080 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1081 host->mmc->caps2 |= MMC_CAP2_SD_EXP; 1082 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; 1083 sdhci_enable_v4_mode(host); 1084 1085 return 0; 1086 } 1087 1088 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 1089 { 1090 /* 1091 * According to Section 3.6.1 signal voltage switch procedure in 1092 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1093 * follows: 1094 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1095 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1096 * period. 1097 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1098 * step (12). 1099 * 1100 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1101 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 1102 * 1103 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 1104 * slightly longer than 5ms before the control register reports that 1105 * 1.8V is ready, and far longer still before the card will actually 1106 * work reliably. 1107 */ 1108 usleep_range(100000, 110000); 1109 } 1110 1111 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host) 1112 { 1113 /* 1114 * According to Section 3.6.1 signal voltage switch procedure in 1115 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1116 * follows: 1117 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1118 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1119 * period. 1120 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1121 * step (12). 1122 * 1123 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1124 * to ensure 1.8V signal enable bit is set by GL9767. 1125 * 1126 */ 1127 usleep_range(5000, 5500); 1128 } 1129 1130 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 1131 { 1132 sdhci_reset(host, mask); 1133 gli_set_9750(host); 1134 } 1135 1136 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 1137 { 1138 u32 value; 1139 1140 value = readl(host->ioaddr + reg); 1141 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 1142 value |= 0xc8; 1143 1144 return value; 1145 } 1146 1147 #ifdef CONFIG_PM_SLEEP 1148 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 1149 { 1150 struct sdhci_pci_slot *slot = chip->slots[0]; 1151 1152 pci_free_irq_vectors(slot->chip->pdev); 1153 gli_pcie_enable_msi(slot); 1154 1155 return sdhci_pci_resume_host(chip); 1156 } 1157 1158 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip) 1159 { 1160 struct sdhci_pci_slot *slot = chip->slots[0]; 1161 int ret; 1162 1163 ret = sdhci_pci_gli_resume(chip); 1164 if (ret) 1165 return ret; 1166 1167 return cqhci_resume(slot->host->mmc); 1168 } 1169 1170 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip) 1171 { 1172 struct sdhci_pci_slot *slot = chip->slots[0]; 1173 int ret; 1174 1175 ret = cqhci_suspend(slot->host->mmc); 1176 if (ret) 1177 return ret; 1178 1179 return sdhci_suspend_host(slot->host); 1180 } 1181 #endif 1182 1183 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 1184 struct mmc_ios *ios) 1185 { 1186 struct sdhci_host *host = mmc_priv(mmc); 1187 u32 val; 1188 1189 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 1190 if (ios->enhanced_strobe) 1191 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 1192 else 1193 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 1194 1195 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 1196 } 1197 1198 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 1199 unsigned int timing) 1200 { 1201 u16 ctrl_2; 1202 1203 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1204 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1205 if (timing == MMC_TIMING_MMC_HS200) 1206 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1207 else if (timing == MMC_TIMING_MMC_HS) 1208 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1209 else if (timing == MMC_TIMING_MMC_DDR52) 1210 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1211 else if (timing == MMC_TIMING_MMC_HS400) 1212 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 1213 1214 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1215 } 1216 1217 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 1218 { 1219 sdhci_dumpregs(mmc_priv(mmc)); 1220 } 1221 1222 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 1223 { 1224 struct cqhci_host *cq_host = mmc->cqe_private; 1225 u32 value; 1226 1227 value = cqhci_readl(cq_host, CQHCI_CFG); 1228 value |= CQHCI_ENABLE; 1229 cqhci_writel(cq_host, value, CQHCI_CFG); 1230 } 1231 1232 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 1233 { 1234 struct sdhci_host *host = mmc_priv(mmc); 1235 1236 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1237 sdhci_cqe_enable(mmc); 1238 } 1239 1240 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 1241 { 1242 int cmd_error = 0; 1243 int data_error = 0; 1244 1245 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1246 return intmask; 1247 1248 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1249 1250 return 0; 1251 } 1252 1253 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 1254 { 1255 struct sdhci_host *host = mmc_priv(mmc); 1256 struct cqhci_host *cq_host = mmc->cqe_private; 1257 u32 value; 1258 1259 value = cqhci_readl(cq_host, CQHCI_CFG); 1260 value &= ~CQHCI_ENABLE; 1261 cqhci_writel(cq_host, value, CQHCI_CFG); 1262 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1263 } 1264 1265 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 1266 .enable = sdhci_gl9763e_cqe_enable, 1267 .disable = sdhci_cqe_disable, 1268 .dumpregs = sdhci_gl9763e_dumpregs, 1269 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 1270 .post_disable = sdhci_gl9763e_cqe_post_disable, 1271 }; 1272 1273 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 1274 { 1275 struct device *dev = &slot->chip->pdev->dev; 1276 struct sdhci_host *host = slot->host; 1277 struct cqhci_host *cq_host; 1278 bool dma64; 1279 int ret; 1280 1281 ret = sdhci_setup_host(host); 1282 if (ret) 1283 return ret; 1284 1285 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1286 if (!cq_host) { 1287 ret = -ENOMEM; 1288 goto cleanup; 1289 } 1290 1291 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 1292 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 1293 1294 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1295 if (dma64) 1296 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1297 1298 ret = cqhci_init(cq_host, host->mmc, dma64); 1299 if (ret) 1300 goto cleanup; 1301 1302 ret = __sdhci_add_host(host); 1303 if (ret) 1304 goto cleanup; 1305 1306 return 0; 1307 1308 cleanup: 1309 sdhci_cleanup_host(host); 1310 return ret; 1311 } 1312 1313 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 1314 { 1315 struct pci_dev *pdev = slot->chip->pdev; 1316 u32 value; 1317 1318 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1319 value &= ~GLI_9763E_VHS_REV; 1320 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1321 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1322 1323 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 1324 value |= GLI_9763E_SCR_AXI_REQ; 1325 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 1326 1327 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 1328 value &= ~GLI_9763E_HS400_SLOW; 1329 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 1330 1331 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 1332 value &= ~GLI_9763E_CFG2_L1DLY; 1333 /* set ASPM L1 entry delay to 21us */ 1334 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 1335 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 1336 1337 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 1338 value &= ~GLI_9763E_HS400_RXDLY; 1339 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 1340 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 1341 1342 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1343 value &= ~GLI_9763E_VHS_REV; 1344 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1345 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1346 } 1347 1348 #ifdef CONFIG_PM 1349 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable) 1350 { 1351 struct pci_dev *pdev = slot->chip->pdev; 1352 u32 value; 1353 1354 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1355 value &= ~GLI_9763E_VHS_REV; 1356 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1357 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1358 1359 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value); 1360 1361 if (enable) 1362 value &= ~GLI_9763E_CFG_LPSN_DIS; 1363 else 1364 value |= GLI_9763E_CFG_LPSN_DIS; 1365 1366 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value); 1367 1368 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1369 value &= ~GLI_9763E_VHS_REV; 1370 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1371 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1372 } 1373 1374 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 1375 { 1376 struct sdhci_pci_slot *slot = chip->slots[0]; 1377 struct sdhci_host *host = slot->host; 1378 u16 clock; 1379 1380 /* Enable LPM negotiation to allow entering L1 state */ 1381 gl9763e_set_low_power_negotiation(slot, true); 1382 1383 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1384 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 1385 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1386 1387 return 0; 1388 } 1389 1390 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 1391 { 1392 struct sdhci_pci_slot *slot = chip->slots[0]; 1393 struct sdhci_host *host = slot->host; 1394 u16 clock; 1395 1396 if (host->mmc->ios.power_mode != MMC_POWER_ON) 1397 return 0; 1398 1399 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1400 1401 clock |= SDHCI_CLOCK_PLL_EN; 1402 clock &= ~SDHCI_CLOCK_INT_STABLE; 1403 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1404 1405 /* Wait max 150 ms */ 1406 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 1407 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 1408 pr_err("%s: PLL clock never stabilised.\n", 1409 mmc_hostname(host->mmc)); 1410 sdhci_dumpregs(host); 1411 } 1412 1413 clock |= SDHCI_CLOCK_CARD_EN; 1414 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1415 1416 /* Disable LPM negotiation to avoid entering L1 state. */ 1417 gl9763e_set_low_power_negotiation(slot, false); 1418 1419 return 0; 1420 } 1421 #endif 1422 1423 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 1424 { 1425 struct pci_dev *pdev = slot->chip->pdev; 1426 struct sdhci_host *host = slot->host; 1427 u32 value; 1428 1429 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1430 MMC_CAP_1_8V_DDR | 1431 MMC_CAP_NONREMOVABLE; 1432 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1433 MMC_CAP2_HS400_1_8V | 1434 MMC_CAP2_HS400_ES | 1435 MMC_CAP2_NO_SDIO | 1436 MMC_CAP2_NO_SD; 1437 1438 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1439 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 1440 if (value & GLI_9763E_MB_ERP_ON) 1441 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1442 1443 gli_pcie_enable_msi(slot); 1444 host->mmc_host_ops.hs400_enhanced_strobe = 1445 gl9763e_hs400_enhanced_strobe; 1446 gli_set_gl9763e(slot); 1447 sdhci_enable_v4_mode(host); 1448 1449 return 0; 1450 } 1451 1452 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 1453 1454 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 1455 { 1456 u32 val = readl(host->ioaddr + (reg & ~3)); 1457 u16 word; 1458 1459 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 1460 return word; 1461 } 1462 1463 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 1464 { 1465 u32 val = readl(host->ioaddr + (reg & ~3)); 1466 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 1467 1468 return byte; 1469 } 1470 1471 static const struct sdhci_ops sdhci_gl9755_ops = { 1472 .read_w = sdhci_gli_readw, 1473 .read_b = sdhci_gli_readb, 1474 .set_clock = sdhci_gl9755_set_clock, 1475 .enable_dma = sdhci_pci_enable_dma, 1476 .set_bus_width = sdhci_set_bus_width, 1477 .reset = sdhci_reset, 1478 .set_uhs_signaling = sdhci_set_uhs_signaling, 1479 .voltage_switch = sdhci_gli_voltage_switch, 1480 }; 1481 1482 const struct sdhci_pci_fixes sdhci_gl9755 = { 1483 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1484 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1485 .probe_slot = gli_probe_slot_gl9755, 1486 .ops = &sdhci_gl9755_ops, 1487 #ifdef CONFIG_PM_SLEEP 1488 .resume = sdhci_pci_gli_resume, 1489 #endif 1490 }; 1491 1492 static const struct sdhci_ops sdhci_gl9750_ops = { 1493 .read_w = sdhci_gli_readw, 1494 .read_b = sdhci_gli_readb, 1495 .read_l = sdhci_gl9750_readl, 1496 .set_clock = sdhci_gl9750_set_clock, 1497 .enable_dma = sdhci_pci_enable_dma, 1498 .set_bus_width = sdhci_set_bus_width, 1499 .reset = sdhci_gl9750_reset, 1500 .set_uhs_signaling = sdhci_set_uhs_signaling, 1501 .voltage_switch = sdhci_gli_voltage_switch, 1502 .platform_execute_tuning = gl9750_execute_tuning, 1503 }; 1504 1505 const struct sdhci_pci_fixes sdhci_gl9750 = { 1506 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1507 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1508 .probe_slot = gli_probe_slot_gl9750, 1509 .ops = &sdhci_gl9750_ops, 1510 #ifdef CONFIG_PM_SLEEP 1511 .resume = sdhci_pci_gli_resume, 1512 #endif 1513 }; 1514 1515 static const struct sdhci_ops sdhci_gl9763e_ops = { 1516 .set_clock = sdhci_set_clock, 1517 .enable_dma = sdhci_pci_enable_dma, 1518 .set_bus_width = sdhci_set_bus_width, 1519 .reset = sdhci_and_cqhci_reset, 1520 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 1521 .voltage_switch = sdhci_gli_voltage_switch, 1522 .irq = sdhci_gl9763e_cqhci_irq, 1523 }; 1524 1525 const struct sdhci_pci_fixes sdhci_gl9763e = { 1526 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1527 .probe_slot = gli_probe_slot_gl9763e, 1528 .ops = &sdhci_gl9763e_ops, 1529 #ifdef CONFIG_PM_SLEEP 1530 .resume = sdhci_cqhci_gli_resume, 1531 .suspend = sdhci_cqhci_gli_suspend, 1532 #endif 1533 #ifdef CONFIG_PM 1534 .runtime_suspend = gl9763e_runtime_suspend, 1535 .runtime_resume = gl9763e_runtime_resume, 1536 .allow_runtime_pm = true, 1537 #endif 1538 .add_host = gl9763e_add_host, 1539 }; 1540 1541 static const struct sdhci_ops sdhci_gl9767_ops = { 1542 .set_clock = sdhci_gl9767_set_clock, 1543 .enable_dma = sdhci_pci_enable_dma, 1544 .set_bus_width = sdhci_set_bus_width, 1545 .reset = sdhci_gl9767_reset, 1546 .set_uhs_signaling = sdhci_set_uhs_signaling, 1547 .voltage_switch = sdhci_gl9767_voltage_switch, 1548 }; 1549 1550 const struct sdhci_pci_fixes sdhci_gl9767 = { 1551 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1552 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1553 .probe_slot = gli_probe_slot_gl9767, 1554 .ops = &sdhci_gl9767_ops, 1555 #ifdef CONFIG_PM_SLEEP 1556 .resume = sdhci_pci_gli_resume, 1557 #endif 1558 }; 1559