1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include "sdhci.h" 16 #include "sdhci-pci.h" 17 #include "cqhci.h" 18 19 /* Genesys Logic extra registers */ 20 #define SDHCI_GLI_9750_WT 0x800 21 #define SDHCI_GLI_9750_WT_EN BIT(0) 22 #define GLI_9750_WT_EN_ON 0x1 23 #define GLI_9750_WT_EN_OFF 0x0 24 25 #define SDHCI_GLI_9750_CFG2 0x848 26 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 27 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 28 29 #define SDHCI_GLI_9750_DRIVING 0x860 30 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 31 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 32 #define GLI_9750_DRIVING_1_VALUE 0xFFF 33 #define GLI_9750_DRIVING_2_VALUE 0x3 34 #define SDHCI_GLI_9750_SEL_1 BIT(29) 35 #define SDHCI_GLI_9750_SEL_2 BIT(31) 36 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 37 38 #define SDHCI_GLI_9750_PLL 0x864 39 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 40 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 41 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 42 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 43 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 44 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 45 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 46 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 47 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 48 49 #define SDHCI_GLI_9750_PLLSSC 0x86C 50 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 51 52 #define SDHCI_GLI_9750_SW_CTRL 0x874 53 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 54 #define GLI_9750_SW_CTRL_4_VALUE 0x3 55 56 #define SDHCI_GLI_9750_MISC 0x878 57 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 58 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 59 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 60 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 61 #define GLI_9750_MISC_RX_INV_ON 0x1 62 #define GLI_9750_MISC_RX_INV_OFF 0x0 63 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 64 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 65 66 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 67 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 68 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 69 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 70 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 71 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 72 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 73 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 74 75 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 76 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 77 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 78 79 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 80 81 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 82 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 83 84 #define PCIE_GLI_9763E_VHS 0x884 85 #define GLI_9763E_VHS_REV GENMASK(19, 16) 86 #define GLI_9763E_VHS_REV_R 0x0 87 #define GLI_9763E_VHS_REV_M 0x1 88 #define GLI_9763E_VHS_REV_W 0x2 89 #define PCIE_GLI_9763E_MB 0x888 90 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 91 #define GLI_9763E_MB_ERP_ON BIT(7) 92 #define PCIE_GLI_9763E_SCR 0x8E0 93 #define GLI_9763E_SCR_AXI_REQ BIT(9) 94 95 #define PCIE_GLI_9763E_CFG2 0x8A4 96 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 97 #define GLI_9763E_CFG2_L1DLY_MID 0x54 98 99 #define PCIE_GLI_9763E_MMC_CTRL 0x960 100 #define GLI_9763E_HS400_SLOW BIT(3) 101 102 #define PCIE_GLI_9763E_CLKRXDLY 0x934 103 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 104 #define GLI_9763E_HS400_RXDLY_5 0x5 105 106 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 107 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 108 SDHCI_TRNS_BLK_CNT_EN | \ 109 SDHCI_TRNS_DMA) 110 111 #define PCI_GLI_9755_WT 0x800 112 #define PCI_GLI_9755_WT_EN BIT(0) 113 #define GLI_9755_WT_EN_ON 0x1 114 #define GLI_9755_WT_EN_OFF 0x0 115 116 #define PCI_GLI_9755_PECONF 0x44 117 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 118 #define PCI_GLI_9755_DMACLK BIT(29) 119 120 #define PCI_GLI_9755_CFG2 0x48 121 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 122 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 123 124 #define PCI_GLI_9755_PLL 0x64 125 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 126 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 127 #define PCI_GLI_9755_PLL_DIR BIT(15) 128 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 129 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 130 131 #define PCI_GLI_9755_PLLSSC 0x68 132 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 133 134 #define PCI_GLI_9755_SerDes 0x70 135 #define PCI_GLI_9755_SCP_DIS BIT(19) 136 137 #define GLI_MAX_TUNING_LOOP 40 138 139 /* Genesys Logic chipset */ 140 static inline void gl9750_wt_on(struct sdhci_host *host) 141 { 142 u32 wt_value; 143 u32 wt_enable; 144 145 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 146 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 147 148 if (wt_enable == GLI_9750_WT_EN_ON) 149 return; 150 151 wt_value &= ~SDHCI_GLI_9750_WT_EN; 152 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 153 154 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 155 } 156 157 static inline void gl9750_wt_off(struct sdhci_host *host) 158 { 159 u32 wt_value; 160 u32 wt_enable; 161 162 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 163 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 164 165 if (wt_enable == GLI_9750_WT_EN_OFF) 166 return; 167 168 wt_value &= ~SDHCI_GLI_9750_WT_EN; 169 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 170 171 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 172 } 173 174 static void gli_set_9750(struct sdhci_host *host) 175 { 176 u32 driving_value; 177 u32 pll_value; 178 u32 sw_ctrl_value; 179 u32 misc_value; 180 u32 parameter_value; 181 u32 control_value; 182 u16 ctrl2; 183 184 gl9750_wt_on(host); 185 186 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 187 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 188 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 189 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 190 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 191 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 192 193 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 194 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 195 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 196 GLI_9750_DRIVING_1_VALUE); 197 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 198 GLI_9750_DRIVING_2_VALUE); 199 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 200 driving_value |= SDHCI_GLI_9750_SEL_2; 201 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 202 203 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 204 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 205 GLI_9750_SW_CTRL_4_VALUE); 206 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 207 208 /* reset the tuning flow after reinit and before starting tuning */ 209 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 210 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 211 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 212 GLI_9750_PLL_TX2_INV_VALUE); 213 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 214 GLI_9750_PLL_TX2_DLY_VALUE); 215 216 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 217 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 218 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 219 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 220 GLI_9750_MISC_TX1_INV_VALUE); 221 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 222 GLI_9750_MISC_RX_INV_VALUE); 223 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 224 GLI_9750_MISC_TX1_DLY_VALUE); 225 226 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 227 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 228 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 229 230 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 231 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 232 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 233 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 234 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 235 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 236 237 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 238 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 239 240 /* disable tuned clk */ 241 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 242 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 243 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 244 245 /* enable tuning parameters control */ 246 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 247 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 248 GLI_9750_TUNING_CONTROL_EN_ON); 249 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 250 251 /* write tuning parameters */ 252 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 253 254 /* disable tuning parameters control */ 255 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 256 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 257 GLI_9750_TUNING_CONTROL_EN_OFF); 258 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 259 260 /* clear tuned clk */ 261 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 262 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 263 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 264 265 gl9750_wt_off(host); 266 } 267 268 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 269 { 270 u32 misc_value; 271 272 gl9750_wt_on(host); 273 274 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 275 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 276 if (b) { 277 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 278 GLI_9750_MISC_RX_INV_ON); 279 } else { 280 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 281 GLI_9750_MISC_RX_INV_OFF); 282 } 283 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 284 285 gl9750_wt_off(host); 286 } 287 288 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 289 { 290 int i; 291 int rx_inv; 292 293 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 294 gli_set_9750_rx_inv(host, !!rx_inv); 295 sdhci_start_tuning(host); 296 297 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 298 u16 ctrl; 299 300 sdhci_send_tuning(host, opcode); 301 302 if (!host->tuning_done) { 303 sdhci_abort_tuning(host, opcode); 304 break; 305 } 306 307 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 308 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 309 if (ctrl & SDHCI_CTRL_TUNED_CLK) 310 return 0; /* Success! */ 311 break; 312 } 313 } 314 } 315 if (!host->tuning_done) { 316 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 317 mmc_hostname(host->mmc)); 318 return -ETIMEDOUT; 319 } 320 321 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 322 mmc_hostname(host->mmc)); 323 sdhci_reset_tuning(host); 324 325 return -EAGAIN; 326 } 327 328 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 329 { 330 host->mmc->retune_period = 0; 331 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 332 host->mmc->retune_period = host->tuning_count; 333 334 gli_set_9750(host); 335 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 336 sdhci_end_tuning(host); 337 338 return 0; 339 } 340 341 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 342 { 343 u32 pll; 344 345 gl9750_wt_on(host); 346 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 347 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 348 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 349 gl9750_wt_off(host); 350 } 351 352 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 353 { 354 u32 pll; 355 356 gl9750_wt_on(host); 357 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 358 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 359 SDHCI_GLI_9750_PLL_PDIV | 360 SDHCI_GLI_9750_PLL_DIR); 361 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 362 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 363 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 364 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 365 gl9750_wt_off(host); 366 367 /* wait for pll stable */ 368 mdelay(1); 369 } 370 371 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 372 { 373 u32 pll; 374 u32 ssc; 375 376 gl9750_wt_on(host); 377 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 378 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 379 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 380 SDHCI_GLI_9750_PLLSSC_EN); 381 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 382 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 383 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 384 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 385 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 386 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 387 gl9750_wt_off(host); 388 } 389 390 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 391 { 392 /* set pll to 205MHz and enable ssc */ 393 gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7); 394 gl9750_set_pll(host, 0x1, 0x246, 0x0); 395 } 396 397 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 398 { 399 struct mmc_ios *ios = &host->mmc->ios; 400 u16 clk; 401 402 host->mmc->actual_clock = 0; 403 404 gl9750_disable_ssc_pll(host); 405 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 406 407 if (clock == 0) 408 return; 409 410 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 411 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 412 host->mmc->actual_clock = 205000000; 413 gl9750_set_ssc_pll_205mhz(host); 414 } 415 416 sdhci_enable_clk(host, clk); 417 } 418 419 static void gl9750_hw_setting(struct sdhci_host *host) 420 { 421 u32 value; 422 423 gl9750_wt_on(host); 424 425 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 426 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 427 /* set ASPM L1 entry delay to 7.9us */ 428 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 429 GLI_9750_CFG2_L1DLY_VALUE); 430 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 431 432 gl9750_wt_off(host); 433 } 434 435 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 436 { 437 int ret; 438 439 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 440 PCI_IRQ_MSI | PCI_IRQ_MSIX); 441 if (ret < 0) { 442 pr_warn("%s: enable PCI MSI failed, error=%d\n", 443 mmc_hostname(slot->host->mmc), ret); 444 return; 445 } 446 447 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 448 } 449 450 static inline void gl9755_wt_on(struct pci_dev *pdev) 451 { 452 u32 wt_value; 453 u32 wt_enable; 454 455 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 456 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 457 458 if (wt_enable == GLI_9755_WT_EN_ON) 459 return; 460 461 wt_value &= ~PCI_GLI_9755_WT_EN; 462 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 463 464 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 465 } 466 467 static inline void gl9755_wt_off(struct pci_dev *pdev) 468 { 469 u32 wt_value; 470 u32 wt_enable; 471 472 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 473 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 474 475 if (wt_enable == GLI_9755_WT_EN_OFF) 476 return; 477 478 wt_value &= ~PCI_GLI_9755_WT_EN; 479 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 480 481 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 482 } 483 484 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 485 { 486 u32 pll; 487 488 gl9755_wt_on(pdev); 489 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 490 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 491 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 492 gl9755_wt_off(pdev); 493 } 494 495 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 496 { 497 u32 pll; 498 499 gl9755_wt_on(pdev); 500 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 501 pll &= ~(PCI_GLI_9755_PLL_LDIV | 502 PCI_GLI_9755_PLL_PDIV | 503 PCI_GLI_9755_PLL_DIR); 504 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 505 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 506 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 507 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 508 gl9755_wt_off(pdev); 509 510 /* wait for pll stable */ 511 mdelay(1); 512 } 513 514 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 515 { 516 u32 pll; 517 u32 ssc; 518 519 gl9755_wt_on(pdev); 520 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 521 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 522 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 523 PCI_GLI_9755_PLLSSC_EN); 524 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 525 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 526 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 527 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 528 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 529 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 530 gl9755_wt_off(pdev); 531 } 532 533 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 534 { 535 /* set pll to 205MHz and enable ssc */ 536 gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7); 537 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 538 } 539 540 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 541 { 542 struct sdhci_pci_slot *slot = sdhci_priv(host); 543 struct mmc_ios *ios = &host->mmc->ios; 544 struct pci_dev *pdev; 545 u16 clk; 546 547 pdev = slot->chip->pdev; 548 host->mmc->actual_clock = 0; 549 550 gl9755_disable_ssc_pll(pdev); 551 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 552 553 if (clock == 0) 554 return; 555 556 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 557 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 558 host->mmc->actual_clock = 205000000; 559 gl9755_set_ssc_pll_205mhz(pdev); 560 } 561 562 sdhci_enable_clk(host, clk); 563 } 564 565 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 566 { 567 struct pci_dev *pdev = slot->chip->pdev; 568 u32 value; 569 570 gl9755_wt_on(pdev); 571 572 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 573 value &= ~PCI_GLI_9755_LFCLK; 574 value &= ~PCI_GLI_9755_DMACLK; 575 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 576 577 /* enable short circuit protection */ 578 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 579 value &= ~PCI_GLI_9755_SCP_DIS; 580 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 581 582 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 583 value &= ~PCI_GLI_9755_CFG2_L1DLY; 584 /* set ASPM L1 entry delay to 7.9us */ 585 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 586 GLI_9755_CFG2_L1DLY_VALUE); 587 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 588 589 gl9755_wt_off(pdev); 590 } 591 592 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 593 { 594 struct sdhci_host *host = slot->host; 595 596 gl9750_hw_setting(host); 597 gli_pcie_enable_msi(slot); 598 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 599 sdhci_enable_v4_mode(host); 600 601 return 0; 602 } 603 604 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 605 { 606 struct sdhci_host *host = slot->host; 607 608 gl9755_hw_setting(slot); 609 gli_pcie_enable_msi(slot); 610 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 611 sdhci_enable_v4_mode(host); 612 613 return 0; 614 } 615 616 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 617 { 618 /* 619 * According to Section 3.6.1 signal voltage switch procedure in 620 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 621 * follows: 622 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 623 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 624 * period. 625 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 626 * step (12). 627 * 628 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 629 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 630 * 631 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 632 * slightly longer than 5ms before the control register reports that 633 * 1.8V is ready, and far longer still before the card will actually 634 * work reliably. 635 */ 636 usleep_range(100000, 110000); 637 } 638 639 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 640 { 641 sdhci_reset(host, mask); 642 gli_set_9750(host); 643 } 644 645 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 646 { 647 u32 value; 648 649 value = readl(host->ioaddr + reg); 650 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 651 value |= 0xc8; 652 653 return value; 654 } 655 656 #ifdef CONFIG_PM_SLEEP 657 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 658 { 659 struct sdhci_pci_slot *slot = chip->slots[0]; 660 661 pci_free_irq_vectors(slot->chip->pdev); 662 gli_pcie_enable_msi(slot); 663 664 return sdhci_pci_resume_host(chip); 665 } 666 667 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip) 668 { 669 struct sdhci_pci_slot *slot = chip->slots[0]; 670 int ret; 671 672 ret = sdhci_pci_gli_resume(chip); 673 if (ret) 674 return ret; 675 676 return cqhci_resume(slot->host->mmc); 677 } 678 679 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip) 680 { 681 struct sdhci_pci_slot *slot = chip->slots[0]; 682 int ret; 683 684 ret = cqhci_suspend(slot->host->mmc); 685 if (ret) 686 return ret; 687 688 return sdhci_suspend_host(slot->host); 689 } 690 #endif 691 692 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 693 struct mmc_ios *ios) 694 { 695 struct sdhci_host *host = mmc_priv(mmc); 696 u32 val; 697 698 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 699 if (ios->enhanced_strobe) 700 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 701 else 702 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 703 704 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 705 } 706 707 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 708 unsigned int timing) 709 { 710 u16 ctrl_2; 711 712 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 713 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 714 if (timing == MMC_TIMING_MMC_HS200) 715 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 716 else if (timing == MMC_TIMING_MMC_HS) 717 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 718 else if (timing == MMC_TIMING_MMC_DDR52) 719 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 720 else if (timing == MMC_TIMING_MMC_HS400) 721 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 722 723 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 724 } 725 726 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 727 { 728 sdhci_dumpregs(mmc_priv(mmc)); 729 } 730 731 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 732 { 733 struct cqhci_host *cq_host = mmc->cqe_private; 734 u32 value; 735 736 value = cqhci_readl(cq_host, CQHCI_CFG); 737 value |= CQHCI_ENABLE; 738 cqhci_writel(cq_host, value, CQHCI_CFG); 739 } 740 741 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 742 { 743 struct sdhci_host *host = mmc_priv(mmc); 744 745 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 746 sdhci_cqe_enable(mmc); 747 } 748 749 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 750 { 751 int cmd_error = 0; 752 int data_error = 0; 753 754 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 755 return intmask; 756 757 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 758 759 return 0; 760 } 761 762 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 763 { 764 struct sdhci_host *host = mmc_priv(mmc); 765 struct cqhci_host *cq_host = mmc->cqe_private; 766 u32 value; 767 768 value = cqhci_readl(cq_host, CQHCI_CFG); 769 value &= ~CQHCI_ENABLE; 770 cqhci_writel(cq_host, value, CQHCI_CFG); 771 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 772 } 773 774 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 775 .enable = sdhci_gl9763e_cqe_enable, 776 .disable = sdhci_cqe_disable, 777 .dumpregs = sdhci_gl9763e_dumpregs, 778 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 779 .post_disable = sdhci_gl9763e_cqe_post_disable, 780 }; 781 782 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 783 { 784 struct device *dev = &slot->chip->pdev->dev; 785 struct sdhci_host *host = slot->host; 786 struct cqhci_host *cq_host; 787 bool dma64; 788 int ret; 789 790 ret = sdhci_setup_host(host); 791 if (ret) 792 return ret; 793 794 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 795 if (!cq_host) { 796 ret = -ENOMEM; 797 goto cleanup; 798 } 799 800 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 801 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 802 803 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 804 if (dma64) 805 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 806 807 ret = cqhci_init(cq_host, host->mmc, dma64); 808 if (ret) 809 goto cleanup; 810 811 ret = __sdhci_add_host(host); 812 if (ret) 813 goto cleanup; 814 815 return 0; 816 817 cleanup: 818 sdhci_cleanup_host(host); 819 return ret; 820 } 821 822 static void sdhci_gl9763e_reset(struct sdhci_host *host, u8 mask) 823 { 824 if ((host->mmc->caps2 & MMC_CAP2_CQE) && (mask & SDHCI_RESET_ALL) && 825 host->mmc->cqe_private) 826 cqhci_deactivate(host->mmc); 827 sdhci_reset(host, mask); 828 } 829 830 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 831 { 832 struct pci_dev *pdev = slot->chip->pdev; 833 u32 value; 834 835 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 836 value &= ~GLI_9763E_VHS_REV; 837 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 838 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 839 840 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 841 value |= GLI_9763E_SCR_AXI_REQ; 842 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 843 844 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 845 value &= ~GLI_9763E_HS400_SLOW; 846 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 847 848 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 849 value &= ~GLI_9763E_CFG2_L1DLY; 850 /* set ASPM L1 entry delay to 21us */ 851 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 852 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 853 854 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 855 value &= ~GLI_9763E_HS400_RXDLY; 856 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 857 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 858 859 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 860 value &= ~GLI_9763E_VHS_REV; 861 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 862 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 863 } 864 865 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 866 { 867 struct pci_dev *pdev = slot->chip->pdev; 868 struct sdhci_host *host = slot->host; 869 u32 value; 870 871 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 872 MMC_CAP_1_8V_DDR | 873 MMC_CAP_NONREMOVABLE; 874 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 875 MMC_CAP2_HS400_1_8V | 876 MMC_CAP2_HS400_ES | 877 MMC_CAP2_NO_SDIO | 878 MMC_CAP2_NO_SD; 879 880 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 881 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 882 if (value & GLI_9763E_MB_ERP_ON) 883 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 884 885 gli_pcie_enable_msi(slot); 886 host->mmc_host_ops.hs400_enhanced_strobe = 887 gl9763e_hs400_enhanced_strobe; 888 gli_set_gl9763e(slot); 889 sdhci_enable_v4_mode(host); 890 891 return 0; 892 } 893 894 static const struct sdhci_ops sdhci_gl9755_ops = { 895 .set_clock = sdhci_gl9755_set_clock, 896 .enable_dma = sdhci_pci_enable_dma, 897 .set_bus_width = sdhci_set_bus_width, 898 .reset = sdhci_reset, 899 .set_uhs_signaling = sdhci_set_uhs_signaling, 900 .voltage_switch = sdhci_gli_voltage_switch, 901 }; 902 903 const struct sdhci_pci_fixes sdhci_gl9755 = { 904 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 905 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 906 .probe_slot = gli_probe_slot_gl9755, 907 .ops = &sdhci_gl9755_ops, 908 #ifdef CONFIG_PM_SLEEP 909 .resume = sdhci_pci_gli_resume, 910 #endif 911 }; 912 913 static const struct sdhci_ops sdhci_gl9750_ops = { 914 .read_l = sdhci_gl9750_readl, 915 .set_clock = sdhci_gl9750_set_clock, 916 .enable_dma = sdhci_pci_enable_dma, 917 .set_bus_width = sdhci_set_bus_width, 918 .reset = sdhci_gl9750_reset, 919 .set_uhs_signaling = sdhci_set_uhs_signaling, 920 .voltage_switch = sdhci_gli_voltage_switch, 921 .platform_execute_tuning = gl9750_execute_tuning, 922 }; 923 924 const struct sdhci_pci_fixes sdhci_gl9750 = { 925 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 926 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 927 .probe_slot = gli_probe_slot_gl9750, 928 .ops = &sdhci_gl9750_ops, 929 #ifdef CONFIG_PM_SLEEP 930 .resume = sdhci_pci_gli_resume, 931 #endif 932 }; 933 934 static const struct sdhci_ops sdhci_gl9763e_ops = { 935 .set_clock = sdhci_set_clock, 936 .enable_dma = sdhci_pci_enable_dma, 937 .set_bus_width = sdhci_set_bus_width, 938 .reset = sdhci_gl9763e_reset, 939 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 940 .voltage_switch = sdhci_gli_voltage_switch, 941 .irq = sdhci_gl9763e_cqhci_irq, 942 }; 943 944 const struct sdhci_pci_fixes sdhci_gl9763e = { 945 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 946 .probe_slot = gli_probe_slot_gl9763e, 947 .ops = &sdhci_gl9763e_ops, 948 #ifdef CONFIG_PM_SLEEP 949 .resume = sdhci_cqhci_gli_resume, 950 .suspend = sdhci_cqhci_gli_suspend, 951 #endif 952 .add_host = gl9763e_add_host, 953 }; 954