1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/iopoll.h> 17 #include "sdhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pci.h" 20 #include "cqhci.h" 21 22 /* Genesys Logic extra registers */ 23 #define SDHCI_GLI_9750_WT 0x800 24 #define SDHCI_GLI_9750_WT_EN BIT(0) 25 #define GLI_9750_WT_EN_ON 0x1 26 #define GLI_9750_WT_EN_OFF 0x0 27 28 #define SDHCI_GLI_9750_CFG2 0x848 29 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 30 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 31 32 #define SDHCI_GLI_9750_DRIVING 0x860 33 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 34 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 35 #define GLI_9750_DRIVING_1_VALUE 0xFFF 36 #define GLI_9750_DRIVING_2_VALUE 0x3 37 #define SDHCI_GLI_9750_SEL_1 BIT(29) 38 #define SDHCI_GLI_9750_SEL_2 BIT(31) 39 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 40 41 #define SDHCI_GLI_9750_PLL 0x864 42 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 43 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 44 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 45 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 46 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 47 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 48 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 49 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 50 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 51 52 #define SDHCI_GLI_9750_PLLSSC 0x86C 53 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 54 55 #define SDHCI_GLI_9750_SW_CTRL 0x874 56 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 57 #define GLI_9750_SW_CTRL_4_VALUE 0x3 58 59 #define SDHCI_GLI_9750_MISC 0x878 60 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 61 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 62 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 63 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 64 #define GLI_9750_MISC_RX_INV_ON 0x1 65 #define GLI_9750_MISC_RX_INV_OFF 0x0 66 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 67 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 68 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 69 70 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 71 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 72 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 73 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 74 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 75 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 76 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 77 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 78 79 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 80 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 81 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 82 83 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 84 85 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 86 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 87 88 #define PCIE_GLI_9763E_VHS 0x884 89 #define GLI_9763E_VHS_REV GENMASK(19, 16) 90 #define GLI_9763E_VHS_REV_R 0x0 91 #define GLI_9763E_VHS_REV_M 0x1 92 #define GLI_9763E_VHS_REV_W 0x2 93 #define PCIE_GLI_9763E_MB 0x888 94 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 95 #define GLI_9763E_MB_ERP_ON BIT(7) 96 #define PCIE_GLI_9763E_SCR 0x8E0 97 #define GLI_9763E_SCR_AXI_REQ BIT(9) 98 99 #define PCIE_GLI_9763E_CFG 0x8A0 100 #define GLI_9763E_CFG_LPSN_DIS BIT(12) 101 102 #define PCIE_GLI_9763E_CFG2 0x8A4 103 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 104 #define GLI_9763E_CFG2_L1DLY_MID 0x54 105 106 #define PCIE_GLI_9763E_MMC_CTRL 0x960 107 #define GLI_9763E_HS400_SLOW BIT(3) 108 109 #define PCIE_GLI_9763E_CLKRXDLY 0x934 110 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 111 #define GLI_9763E_HS400_RXDLY_5 0x5 112 113 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 114 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 115 SDHCI_TRNS_BLK_CNT_EN | \ 116 SDHCI_TRNS_DMA) 117 118 #define PCI_GLI_9755_WT 0x800 119 #define PCI_GLI_9755_WT_EN BIT(0) 120 #define GLI_9755_WT_EN_ON 0x1 121 #define GLI_9755_WT_EN_OFF 0x0 122 123 #define PCI_GLI_9755_PECONF 0x44 124 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 125 #define PCI_GLI_9755_DMACLK BIT(29) 126 #define PCI_GLI_9755_INVERT_CD BIT(30) 127 #define PCI_GLI_9755_INVERT_WP BIT(31) 128 129 #define PCI_GLI_9755_CFG2 0x48 130 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 131 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 132 133 #define PCI_GLI_9755_PLL 0x64 134 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 135 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 136 #define PCI_GLI_9755_PLL_DIR BIT(15) 137 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 138 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 139 140 #define PCI_GLI_9755_PLLSSC 0x68 141 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 142 143 #define PCI_GLI_9755_SerDes 0x70 144 #define PCI_GLI_9755_SCP_DIS BIT(19) 145 146 #define PCI_GLI_9755_MISC 0x78 147 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 148 149 #define PCI_GLI_9755_PM_CTRL 0xFC 150 #define PCI_GLI_9755_PM_STATE GENMASK(1, 0) 151 152 #define GLI_MAX_TUNING_LOOP 40 153 154 /* Genesys Logic chipset */ 155 static inline void gl9750_wt_on(struct sdhci_host *host) 156 { 157 u32 wt_value; 158 u32 wt_enable; 159 160 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 161 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 162 163 if (wt_enable == GLI_9750_WT_EN_ON) 164 return; 165 166 wt_value &= ~SDHCI_GLI_9750_WT_EN; 167 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 168 169 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 170 } 171 172 static inline void gl9750_wt_off(struct sdhci_host *host) 173 { 174 u32 wt_value; 175 u32 wt_enable; 176 177 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 178 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 179 180 if (wt_enable == GLI_9750_WT_EN_OFF) 181 return; 182 183 wt_value &= ~SDHCI_GLI_9750_WT_EN; 184 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 185 186 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 187 } 188 189 static void gli_set_9750(struct sdhci_host *host) 190 { 191 u32 driving_value; 192 u32 pll_value; 193 u32 sw_ctrl_value; 194 u32 misc_value; 195 u32 parameter_value; 196 u32 control_value; 197 u16 ctrl2; 198 199 gl9750_wt_on(host); 200 201 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 202 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 203 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 204 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 205 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 206 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 207 208 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 209 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 210 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 211 GLI_9750_DRIVING_1_VALUE); 212 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 213 GLI_9750_DRIVING_2_VALUE); 214 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 215 driving_value |= SDHCI_GLI_9750_SEL_2; 216 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 217 218 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 219 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 220 GLI_9750_SW_CTRL_4_VALUE); 221 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 222 223 /* reset the tuning flow after reinit and before starting tuning */ 224 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 225 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 226 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 227 GLI_9750_PLL_TX2_INV_VALUE); 228 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 229 GLI_9750_PLL_TX2_DLY_VALUE); 230 231 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 232 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 233 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 234 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 235 GLI_9750_MISC_TX1_INV_VALUE); 236 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 237 GLI_9750_MISC_RX_INV_VALUE); 238 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 239 GLI_9750_MISC_TX1_DLY_VALUE); 240 241 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 242 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 243 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 244 245 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 246 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 247 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 248 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 249 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 250 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 251 252 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 253 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 254 255 /* disable tuned clk */ 256 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 257 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 258 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 259 260 /* enable tuning parameters control */ 261 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 262 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 263 GLI_9750_TUNING_CONTROL_EN_ON); 264 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 265 266 /* write tuning parameters */ 267 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 268 269 /* disable tuning parameters control */ 270 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 271 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 272 GLI_9750_TUNING_CONTROL_EN_OFF); 273 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 274 275 /* clear tuned clk */ 276 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 277 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 278 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 279 280 gl9750_wt_off(host); 281 } 282 283 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 284 { 285 u32 misc_value; 286 287 gl9750_wt_on(host); 288 289 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 290 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 291 if (b) { 292 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 293 GLI_9750_MISC_RX_INV_ON); 294 } else { 295 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 296 GLI_9750_MISC_RX_INV_OFF); 297 } 298 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 299 300 gl9750_wt_off(host); 301 } 302 303 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 304 { 305 int i; 306 int rx_inv; 307 308 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 309 gli_set_9750_rx_inv(host, !!rx_inv); 310 sdhci_start_tuning(host); 311 312 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 313 u16 ctrl; 314 315 sdhci_send_tuning(host, opcode); 316 317 if (!host->tuning_done) { 318 sdhci_abort_tuning(host, opcode); 319 break; 320 } 321 322 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 323 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 324 if (ctrl & SDHCI_CTRL_TUNED_CLK) 325 return 0; /* Success! */ 326 break; 327 } 328 } 329 } 330 if (!host->tuning_done) { 331 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 332 mmc_hostname(host->mmc)); 333 return -ETIMEDOUT; 334 } 335 336 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 337 mmc_hostname(host->mmc)); 338 sdhci_reset_tuning(host); 339 340 return -EAGAIN; 341 } 342 343 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 344 { 345 host->mmc->retune_period = 0; 346 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 347 host->mmc->retune_period = host->tuning_count; 348 349 gli_set_9750(host); 350 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 351 sdhci_end_tuning(host); 352 353 return 0; 354 } 355 356 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 357 { 358 u32 pll; 359 360 gl9750_wt_on(host); 361 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 362 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 363 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 364 gl9750_wt_off(host); 365 } 366 367 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 368 { 369 u32 pll; 370 371 gl9750_wt_on(host); 372 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 373 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 374 SDHCI_GLI_9750_PLL_PDIV | 375 SDHCI_GLI_9750_PLL_DIR); 376 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 377 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 378 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 379 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 380 gl9750_wt_off(host); 381 382 /* wait for pll stable */ 383 mdelay(1); 384 } 385 386 static bool gl9750_ssc_enable(struct sdhci_host *host) 387 { 388 u32 misc; 389 u8 off; 390 391 gl9750_wt_on(host); 392 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 393 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 394 gl9750_wt_off(host); 395 396 return !off; 397 } 398 399 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 400 { 401 u32 pll; 402 u32 ssc; 403 404 gl9750_wt_on(host); 405 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 406 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 407 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 408 SDHCI_GLI_9750_PLLSSC_EN); 409 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 410 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 411 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 412 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 413 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 414 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 415 gl9750_wt_off(host); 416 } 417 418 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 419 { 420 bool enable = gl9750_ssc_enable(host); 421 422 /* set pll to 205MHz and ssc */ 423 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 424 gl9750_set_pll(host, 0x1, 0x246, 0x0); 425 } 426 427 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 428 { 429 bool enable = gl9750_ssc_enable(host); 430 431 /* set pll to 100MHz and ssc */ 432 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 433 gl9750_set_pll(host, 0x1, 0x244, 0x1); 434 } 435 436 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 437 { 438 bool enable = gl9750_ssc_enable(host); 439 440 /* set pll to 50MHz and ssc */ 441 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 442 gl9750_set_pll(host, 0x1, 0x244, 0x3); 443 } 444 445 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 446 { 447 struct mmc_ios *ios = &host->mmc->ios; 448 u16 clk; 449 450 host->mmc->actual_clock = 0; 451 452 gl9750_disable_ssc_pll(host); 453 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 454 455 if (clock == 0) 456 return; 457 458 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 459 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 460 host->mmc->actual_clock = 205000000; 461 gl9750_set_ssc_pll_205mhz(host); 462 } else if (clock == 100000000) { 463 gl9750_set_ssc_pll_100mhz(host); 464 } else if (clock == 50000000) { 465 gl9750_set_ssc_pll_50mhz(host); 466 } 467 468 sdhci_enable_clk(host, clk); 469 } 470 471 static void gl9750_hw_setting(struct sdhci_host *host) 472 { 473 u32 value; 474 475 gl9750_wt_on(host); 476 477 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 478 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 479 /* set ASPM L1 entry delay to 7.9us */ 480 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 481 GLI_9750_CFG2_L1DLY_VALUE); 482 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 483 484 gl9750_wt_off(host); 485 } 486 487 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 488 { 489 int ret; 490 491 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 492 PCI_IRQ_MSI | PCI_IRQ_MSIX); 493 if (ret < 0) { 494 pr_warn("%s: enable PCI MSI failed, error=%d\n", 495 mmc_hostname(slot->host->mmc), ret); 496 return; 497 } 498 499 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 500 } 501 502 static inline void gl9755_wt_on(struct pci_dev *pdev) 503 { 504 u32 wt_value; 505 u32 wt_enable; 506 507 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 508 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 509 510 if (wt_enable == GLI_9755_WT_EN_ON) 511 return; 512 513 wt_value &= ~PCI_GLI_9755_WT_EN; 514 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 515 516 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 517 } 518 519 static inline void gl9755_wt_off(struct pci_dev *pdev) 520 { 521 u32 wt_value; 522 u32 wt_enable; 523 524 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 525 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 526 527 if (wt_enable == GLI_9755_WT_EN_OFF) 528 return; 529 530 wt_value &= ~PCI_GLI_9755_WT_EN; 531 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 532 533 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 534 } 535 536 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 537 { 538 u32 pll; 539 540 gl9755_wt_on(pdev); 541 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 542 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 543 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 544 gl9755_wt_off(pdev); 545 } 546 547 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 548 { 549 u32 pll; 550 551 gl9755_wt_on(pdev); 552 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 553 pll &= ~(PCI_GLI_9755_PLL_LDIV | 554 PCI_GLI_9755_PLL_PDIV | 555 PCI_GLI_9755_PLL_DIR); 556 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 557 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 558 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 559 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 560 gl9755_wt_off(pdev); 561 562 /* wait for pll stable */ 563 mdelay(1); 564 } 565 566 static bool gl9755_ssc_enable(struct pci_dev *pdev) 567 { 568 u32 misc; 569 u8 off; 570 571 gl9755_wt_on(pdev); 572 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 573 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 574 gl9755_wt_off(pdev); 575 576 return !off; 577 } 578 579 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 580 { 581 u32 pll; 582 u32 ssc; 583 584 gl9755_wt_on(pdev); 585 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 586 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 587 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 588 PCI_GLI_9755_PLLSSC_EN); 589 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 590 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 591 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 592 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 593 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 594 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 595 gl9755_wt_off(pdev); 596 } 597 598 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 599 { 600 bool enable = gl9755_ssc_enable(pdev); 601 602 /* set pll to 205MHz and ssc */ 603 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 604 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 605 } 606 607 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 608 { 609 bool enable = gl9755_ssc_enable(pdev); 610 611 /* set pll to 100MHz and ssc */ 612 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 613 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 614 } 615 616 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 617 { 618 bool enable = gl9755_ssc_enable(pdev); 619 620 /* set pll to 50MHz and ssc */ 621 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 622 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 623 } 624 625 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 626 { 627 struct sdhci_pci_slot *slot = sdhci_priv(host); 628 struct mmc_ios *ios = &host->mmc->ios; 629 struct pci_dev *pdev; 630 u16 clk; 631 632 pdev = slot->chip->pdev; 633 host->mmc->actual_clock = 0; 634 635 gl9755_disable_ssc_pll(pdev); 636 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 637 638 if (clock == 0) 639 return; 640 641 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 642 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 643 host->mmc->actual_clock = 205000000; 644 gl9755_set_ssc_pll_205mhz(pdev); 645 } else if (clock == 100000000) { 646 gl9755_set_ssc_pll_100mhz(pdev); 647 } else if (clock == 50000000) { 648 gl9755_set_ssc_pll_50mhz(pdev); 649 } 650 651 sdhci_enable_clk(host, clk); 652 } 653 654 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 655 { 656 struct pci_dev *pdev = slot->chip->pdev; 657 u32 value; 658 659 gl9755_wt_on(pdev); 660 661 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 662 /* 663 * Apple ARM64 platforms using these chips may have 664 * inverted CD/WP detection. 665 */ 666 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 667 value |= PCI_GLI_9755_INVERT_CD; 668 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 669 value |= PCI_GLI_9755_INVERT_WP; 670 value &= ~PCI_GLI_9755_LFCLK; 671 value &= ~PCI_GLI_9755_DMACLK; 672 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 673 674 /* enable short circuit protection */ 675 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 676 value &= ~PCI_GLI_9755_SCP_DIS; 677 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 678 679 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 680 value &= ~PCI_GLI_9755_CFG2_L1DLY; 681 /* set ASPM L1 entry delay to 7.9us */ 682 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 683 GLI_9755_CFG2_L1DLY_VALUE); 684 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 685 686 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 687 pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value); 688 value |= PCI_GLI_9755_PM_STATE; 689 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 690 value &= ~PCI_GLI_9755_PM_STATE; 691 pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); 692 693 gl9755_wt_off(pdev); 694 } 695 696 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 697 { 698 struct sdhci_host *host = slot->host; 699 700 gl9750_hw_setting(host); 701 gli_pcie_enable_msi(slot); 702 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 703 sdhci_enable_v4_mode(host); 704 705 return 0; 706 } 707 708 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 709 { 710 struct sdhci_host *host = slot->host; 711 712 gl9755_hw_setting(slot); 713 gli_pcie_enable_msi(slot); 714 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 715 sdhci_enable_v4_mode(host); 716 717 return 0; 718 } 719 720 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 721 { 722 /* 723 * According to Section 3.6.1 signal voltage switch procedure in 724 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 725 * follows: 726 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 727 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 728 * period. 729 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 730 * step (12). 731 * 732 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 733 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 734 * 735 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 736 * slightly longer than 5ms before the control register reports that 737 * 1.8V is ready, and far longer still before the card will actually 738 * work reliably. 739 */ 740 usleep_range(100000, 110000); 741 } 742 743 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 744 { 745 sdhci_reset(host, mask); 746 gli_set_9750(host); 747 } 748 749 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 750 { 751 u32 value; 752 753 value = readl(host->ioaddr + reg); 754 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 755 value |= 0xc8; 756 757 return value; 758 } 759 760 #ifdef CONFIG_PM_SLEEP 761 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 762 { 763 struct sdhci_pci_slot *slot = chip->slots[0]; 764 765 pci_free_irq_vectors(slot->chip->pdev); 766 gli_pcie_enable_msi(slot); 767 768 return sdhci_pci_resume_host(chip); 769 } 770 771 static int sdhci_cqhci_gli_resume(struct sdhci_pci_chip *chip) 772 { 773 struct sdhci_pci_slot *slot = chip->slots[0]; 774 int ret; 775 776 ret = sdhci_pci_gli_resume(chip); 777 if (ret) 778 return ret; 779 780 return cqhci_resume(slot->host->mmc); 781 } 782 783 static int sdhci_cqhci_gli_suspend(struct sdhci_pci_chip *chip) 784 { 785 struct sdhci_pci_slot *slot = chip->slots[0]; 786 int ret; 787 788 ret = cqhci_suspend(slot->host->mmc); 789 if (ret) 790 return ret; 791 792 return sdhci_suspend_host(slot->host); 793 } 794 #endif 795 796 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 797 struct mmc_ios *ios) 798 { 799 struct sdhci_host *host = mmc_priv(mmc); 800 u32 val; 801 802 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 803 if (ios->enhanced_strobe) 804 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 805 else 806 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 807 808 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 809 } 810 811 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 812 unsigned int timing) 813 { 814 u16 ctrl_2; 815 816 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 817 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 818 if (timing == MMC_TIMING_MMC_HS200) 819 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 820 else if (timing == MMC_TIMING_MMC_HS) 821 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 822 else if (timing == MMC_TIMING_MMC_DDR52) 823 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 824 else if (timing == MMC_TIMING_MMC_HS400) 825 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 826 827 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 828 } 829 830 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 831 { 832 sdhci_dumpregs(mmc_priv(mmc)); 833 } 834 835 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 836 { 837 struct cqhci_host *cq_host = mmc->cqe_private; 838 u32 value; 839 840 value = cqhci_readl(cq_host, CQHCI_CFG); 841 value |= CQHCI_ENABLE; 842 cqhci_writel(cq_host, value, CQHCI_CFG); 843 } 844 845 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 846 { 847 struct sdhci_host *host = mmc_priv(mmc); 848 849 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 850 sdhci_cqe_enable(mmc); 851 } 852 853 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 854 { 855 int cmd_error = 0; 856 int data_error = 0; 857 858 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 859 return intmask; 860 861 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 862 863 return 0; 864 } 865 866 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 867 { 868 struct sdhci_host *host = mmc_priv(mmc); 869 struct cqhci_host *cq_host = mmc->cqe_private; 870 u32 value; 871 872 value = cqhci_readl(cq_host, CQHCI_CFG); 873 value &= ~CQHCI_ENABLE; 874 cqhci_writel(cq_host, value, CQHCI_CFG); 875 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 876 } 877 878 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 879 .enable = sdhci_gl9763e_cqe_enable, 880 .disable = sdhci_cqe_disable, 881 .dumpregs = sdhci_gl9763e_dumpregs, 882 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 883 .post_disable = sdhci_gl9763e_cqe_post_disable, 884 }; 885 886 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 887 { 888 struct device *dev = &slot->chip->pdev->dev; 889 struct sdhci_host *host = slot->host; 890 struct cqhci_host *cq_host; 891 bool dma64; 892 int ret; 893 894 ret = sdhci_setup_host(host); 895 if (ret) 896 return ret; 897 898 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 899 if (!cq_host) { 900 ret = -ENOMEM; 901 goto cleanup; 902 } 903 904 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 905 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 906 907 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 908 if (dma64) 909 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 910 911 ret = cqhci_init(cq_host, host->mmc, dma64); 912 if (ret) 913 goto cleanup; 914 915 ret = __sdhci_add_host(host); 916 if (ret) 917 goto cleanup; 918 919 return 0; 920 921 cleanup: 922 sdhci_cleanup_host(host); 923 return ret; 924 } 925 926 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 927 { 928 struct pci_dev *pdev = slot->chip->pdev; 929 u32 value; 930 931 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 932 value &= ~GLI_9763E_VHS_REV; 933 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 934 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 935 936 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 937 value |= GLI_9763E_SCR_AXI_REQ; 938 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 939 940 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 941 value &= ~GLI_9763E_HS400_SLOW; 942 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 943 944 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 945 value &= ~GLI_9763E_CFG2_L1DLY; 946 /* set ASPM L1 entry delay to 21us */ 947 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 948 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 949 950 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 951 value &= ~GLI_9763E_HS400_RXDLY; 952 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 953 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 954 955 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 956 value &= ~GLI_9763E_VHS_REV; 957 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 958 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 959 } 960 961 #ifdef CONFIG_PM 962 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable) 963 { 964 struct pci_dev *pdev = slot->chip->pdev; 965 u32 value; 966 967 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 968 value &= ~GLI_9763E_VHS_REV; 969 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 970 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 971 972 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value); 973 974 if (enable) 975 value &= ~GLI_9763E_CFG_LPSN_DIS; 976 else 977 value |= GLI_9763E_CFG_LPSN_DIS; 978 979 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value); 980 981 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 982 value &= ~GLI_9763E_VHS_REV; 983 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 984 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 985 } 986 987 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 988 { 989 struct sdhci_pci_slot *slot = chip->slots[0]; 990 struct sdhci_host *host = slot->host; 991 u16 clock; 992 993 /* Enable LPM negotiation to allow entering L1 state */ 994 gl9763e_set_low_power_negotiation(slot, true); 995 996 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 997 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 998 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 999 1000 return 0; 1001 } 1002 1003 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 1004 { 1005 struct sdhci_pci_slot *slot = chip->slots[0]; 1006 struct sdhci_host *host = slot->host; 1007 u16 clock; 1008 1009 if (host->mmc->ios.power_mode != MMC_POWER_ON) 1010 return 0; 1011 1012 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1013 1014 clock |= SDHCI_CLOCK_PLL_EN; 1015 clock &= ~SDHCI_CLOCK_INT_STABLE; 1016 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1017 1018 /* Wait max 150 ms */ 1019 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 1020 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 1021 pr_err("%s: PLL clock never stabilised.\n", 1022 mmc_hostname(host->mmc)); 1023 sdhci_dumpregs(host); 1024 } 1025 1026 clock |= SDHCI_CLOCK_CARD_EN; 1027 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1028 1029 /* Disable LPM negotiation to avoid entering L1 state. */ 1030 gl9763e_set_low_power_negotiation(slot, false); 1031 1032 return 0; 1033 } 1034 #endif 1035 1036 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 1037 { 1038 struct pci_dev *pdev = slot->chip->pdev; 1039 struct sdhci_host *host = slot->host; 1040 u32 value; 1041 1042 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1043 MMC_CAP_1_8V_DDR | 1044 MMC_CAP_NONREMOVABLE; 1045 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1046 MMC_CAP2_HS400_1_8V | 1047 MMC_CAP2_HS400_ES | 1048 MMC_CAP2_NO_SDIO | 1049 MMC_CAP2_NO_SD; 1050 1051 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1052 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 1053 if (value & GLI_9763E_MB_ERP_ON) 1054 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1055 1056 gli_pcie_enable_msi(slot); 1057 host->mmc_host_ops.hs400_enhanced_strobe = 1058 gl9763e_hs400_enhanced_strobe; 1059 gli_set_gl9763e(slot); 1060 sdhci_enable_v4_mode(host); 1061 1062 return 0; 1063 } 1064 1065 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 1066 1067 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 1068 { 1069 u32 val = readl(host->ioaddr + (reg & ~3)); 1070 u16 word; 1071 1072 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 1073 return word; 1074 } 1075 1076 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 1077 { 1078 u32 val = readl(host->ioaddr + (reg & ~3)); 1079 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 1080 1081 return byte; 1082 } 1083 1084 static const struct sdhci_ops sdhci_gl9755_ops = { 1085 .read_w = sdhci_gli_readw, 1086 .read_b = sdhci_gli_readb, 1087 .set_clock = sdhci_gl9755_set_clock, 1088 .enable_dma = sdhci_pci_enable_dma, 1089 .set_bus_width = sdhci_set_bus_width, 1090 .reset = sdhci_reset, 1091 .set_uhs_signaling = sdhci_set_uhs_signaling, 1092 .voltage_switch = sdhci_gli_voltage_switch, 1093 }; 1094 1095 const struct sdhci_pci_fixes sdhci_gl9755 = { 1096 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1097 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1098 .probe_slot = gli_probe_slot_gl9755, 1099 .ops = &sdhci_gl9755_ops, 1100 #ifdef CONFIG_PM_SLEEP 1101 .resume = sdhci_pci_gli_resume, 1102 #endif 1103 }; 1104 1105 static const struct sdhci_ops sdhci_gl9750_ops = { 1106 .read_w = sdhci_gli_readw, 1107 .read_b = sdhci_gli_readb, 1108 .read_l = sdhci_gl9750_readl, 1109 .set_clock = sdhci_gl9750_set_clock, 1110 .enable_dma = sdhci_pci_enable_dma, 1111 .set_bus_width = sdhci_set_bus_width, 1112 .reset = sdhci_gl9750_reset, 1113 .set_uhs_signaling = sdhci_set_uhs_signaling, 1114 .voltage_switch = sdhci_gli_voltage_switch, 1115 .platform_execute_tuning = gl9750_execute_tuning, 1116 }; 1117 1118 const struct sdhci_pci_fixes sdhci_gl9750 = { 1119 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1120 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1121 .probe_slot = gli_probe_slot_gl9750, 1122 .ops = &sdhci_gl9750_ops, 1123 #ifdef CONFIG_PM_SLEEP 1124 .resume = sdhci_pci_gli_resume, 1125 #endif 1126 }; 1127 1128 static const struct sdhci_ops sdhci_gl9763e_ops = { 1129 .set_clock = sdhci_set_clock, 1130 .enable_dma = sdhci_pci_enable_dma, 1131 .set_bus_width = sdhci_set_bus_width, 1132 .reset = sdhci_and_cqhci_reset, 1133 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 1134 .voltage_switch = sdhci_gli_voltage_switch, 1135 .irq = sdhci_gl9763e_cqhci_irq, 1136 }; 1137 1138 const struct sdhci_pci_fixes sdhci_gl9763e = { 1139 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1140 .probe_slot = gli_probe_slot_gl9763e, 1141 .ops = &sdhci_gl9763e_ops, 1142 #ifdef CONFIG_PM_SLEEP 1143 .resume = sdhci_cqhci_gli_resume, 1144 .suspend = sdhci_cqhci_gli_suspend, 1145 #endif 1146 #ifdef CONFIG_PM 1147 .runtime_suspend = gl9763e_runtime_suspend, 1148 .runtime_resume = gl9763e_runtime_resume, 1149 .allow_runtime_pm = true, 1150 #endif 1151 .add_host = gl9763e_add_host, 1152 }; 1153