1e51df6ceSBen Chuang // SPDX-License-Identifier: GPL-2.0+ 2e51df6ceSBen Chuang /* 3e51df6ceSBen Chuang * Copyright (C) 2019 Genesys Logic, Inc. 4e51df6ceSBen Chuang * 5e51df6ceSBen Chuang * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6e51df6ceSBen Chuang * 7e51df6ceSBen Chuang * Version: v0.9.0 (2019-08-08) 8e51df6ceSBen Chuang */ 9e51df6ceSBen Chuang 10e51df6ceSBen Chuang #include <linux/bitfield.h> 11e51df6ceSBen Chuang #include <linux/bits.h> 12e51df6ceSBen Chuang #include <linux/pci.h> 13e51df6ceSBen Chuang #include <linux/mmc/mmc.h> 14e51df6ceSBen Chuang #include <linux/delay.h> 15e51df6ceSBen Chuang #include "sdhci.h" 16e51df6ceSBen Chuang #include "sdhci-pci.h" 17e51df6ceSBen Chuang 18e51df6ceSBen Chuang /* Genesys Logic extra registers */ 19e51df6ceSBen Chuang #define SDHCI_GLI_9750_WT 0x800 20e51df6ceSBen Chuang #define SDHCI_GLI_9750_WT_EN BIT(0) 21e51df6ceSBen Chuang #define GLI_9750_WT_EN_ON 0x1 22e51df6ceSBen Chuang #define GLI_9750_WT_EN_OFF 0x0 23e51df6ceSBen Chuang 24e51df6ceSBen Chuang #define SDHCI_GLI_9750_DRIVING 0x860 25e51df6ceSBen Chuang #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 26e51df6ceSBen Chuang #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 27e51df6ceSBen Chuang #define GLI_9750_DRIVING_1_VALUE 0xFFF 28e51df6ceSBen Chuang #define GLI_9750_DRIVING_2_VALUE 0x3 29e51df6ceSBen Chuang 30e51df6ceSBen Chuang #define SDHCI_GLI_9750_PLL 0x864 31e51df6ceSBen Chuang #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 32e51df6ceSBen Chuang #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 33e51df6ceSBen Chuang #define GLI_9750_PLL_TX2_INV_VALUE 0x1 34e51df6ceSBen Chuang #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 35e51df6ceSBen Chuang 36e51df6ceSBen Chuang #define SDHCI_GLI_9750_SW_CTRL 0x874 37e51df6ceSBen Chuang #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 38e51df6ceSBen Chuang #define GLI_9750_SW_CTRL_4_VALUE 0x3 39e51df6ceSBen Chuang 40e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC 0x878 41e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 42e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 43e51df6ceSBen Chuang #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 44e51df6ceSBen Chuang #define GLI_9750_MISC_TX1_INV_VALUE 0x0 45e51df6ceSBen Chuang #define GLI_9750_MISC_RX_INV_ON 0x1 46e51df6ceSBen Chuang #define GLI_9750_MISC_RX_INV_OFF 0x0 47e51df6ceSBen Chuang #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 48e51df6ceSBen Chuang #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 49e51df6ceSBen Chuang 50e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 51e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 52e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 53e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 54e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 55e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 56e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 57e51df6ceSBen Chuang #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 58e51df6ceSBen Chuang 59e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 60e51df6ceSBen Chuang #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 61e51df6ceSBen Chuang #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 62e51df6ceSBen Chuang 63e51df6ceSBen Chuang #define GLI_MAX_TUNING_LOOP 40 64e51df6ceSBen Chuang 65e51df6ceSBen Chuang /* Genesys Logic chipset */ 66e51df6ceSBen Chuang static inline void gl9750_wt_on(struct sdhci_host *host) 67e51df6ceSBen Chuang { 68e51df6ceSBen Chuang u32 wt_value; 69e51df6ceSBen Chuang u32 wt_enable; 70e51df6ceSBen Chuang 71e51df6ceSBen Chuang wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 72e51df6ceSBen Chuang wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 73e51df6ceSBen Chuang 74e51df6ceSBen Chuang if (wt_enable == GLI_9750_WT_EN_ON) 75e51df6ceSBen Chuang return; 76e51df6ceSBen Chuang 77e51df6ceSBen Chuang wt_value &= ~SDHCI_GLI_9750_WT_EN; 78e51df6ceSBen Chuang wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 79e51df6ceSBen Chuang 80e51df6ceSBen Chuang sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 81e51df6ceSBen Chuang } 82e51df6ceSBen Chuang 83e51df6ceSBen Chuang static inline void gl9750_wt_off(struct sdhci_host *host) 84e51df6ceSBen Chuang { 85e51df6ceSBen Chuang u32 wt_value; 86e51df6ceSBen Chuang u32 wt_enable; 87e51df6ceSBen Chuang 88e51df6ceSBen Chuang wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 89e51df6ceSBen Chuang wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 90e51df6ceSBen Chuang 91e51df6ceSBen Chuang if (wt_enable == GLI_9750_WT_EN_OFF) 92e51df6ceSBen Chuang return; 93e51df6ceSBen Chuang 94e51df6ceSBen Chuang wt_value &= ~SDHCI_GLI_9750_WT_EN; 95e51df6ceSBen Chuang wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 96e51df6ceSBen Chuang 97e51df6ceSBen Chuang sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 98e51df6ceSBen Chuang } 99e51df6ceSBen Chuang 100e51df6ceSBen Chuang static void gli_set_9750(struct sdhci_host *host) 101e51df6ceSBen Chuang { 102e51df6ceSBen Chuang u32 driving_value; 103e51df6ceSBen Chuang u32 pll_value; 104e51df6ceSBen Chuang u32 sw_ctrl_value; 105e51df6ceSBen Chuang u32 misc_value; 106e51df6ceSBen Chuang u32 parameter_value; 107e51df6ceSBen Chuang u32 control_value; 108e51df6ceSBen Chuang u16 ctrl2; 109e51df6ceSBen Chuang 110e51df6ceSBen Chuang gl9750_wt_on(host); 111e51df6ceSBen Chuang 112e51df6ceSBen Chuang driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 113e51df6ceSBen Chuang pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 114e51df6ceSBen Chuang sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 115e51df6ceSBen Chuang misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 116e51df6ceSBen Chuang parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 117e51df6ceSBen Chuang control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 118e51df6ceSBen Chuang 119e51df6ceSBen Chuang driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 120e51df6ceSBen Chuang driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 121e51df6ceSBen Chuang driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 122e51df6ceSBen Chuang GLI_9750_DRIVING_1_VALUE); 123e51df6ceSBen Chuang driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 124e51df6ceSBen Chuang GLI_9750_DRIVING_2_VALUE); 125e51df6ceSBen Chuang sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 126e51df6ceSBen Chuang 127e51df6ceSBen Chuang sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 128e51df6ceSBen Chuang sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 129e51df6ceSBen Chuang GLI_9750_SW_CTRL_4_VALUE); 130e51df6ceSBen Chuang sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 131e51df6ceSBen Chuang 132e51df6ceSBen Chuang /* reset the tuning flow after reinit and before starting tuning */ 133e51df6ceSBen Chuang pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 134e51df6ceSBen Chuang pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 135e51df6ceSBen Chuang pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 136e51df6ceSBen Chuang GLI_9750_PLL_TX2_INV_VALUE); 137e51df6ceSBen Chuang pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 138e51df6ceSBen Chuang GLI_9750_PLL_TX2_DLY_VALUE); 139e51df6ceSBen Chuang 140e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 141e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 142e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 143e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 144e51df6ceSBen Chuang GLI_9750_MISC_TX1_INV_VALUE); 145e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 146e51df6ceSBen Chuang GLI_9750_MISC_RX_INV_VALUE); 147e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 148e51df6ceSBen Chuang GLI_9750_MISC_TX1_DLY_VALUE); 149e51df6ceSBen Chuang 150e51df6ceSBen Chuang parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 151e51df6ceSBen Chuang parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 152e51df6ceSBen Chuang GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 153e51df6ceSBen Chuang 154e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 155e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 156e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 157e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 158e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 159e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 160e51df6ceSBen Chuang 161e51df6ceSBen Chuang sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 162e51df6ceSBen Chuang sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 163e51df6ceSBen Chuang 164e51df6ceSBen Chuang /* disable tuned clk */ 165e51df6ceSBen Chuang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 166e51df6ceSBen Chuang ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 167e51df6ceSBen Chuang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 168e51df6ceSBen Chuang 169e51df6ceSBen Chuang /* enable tuning parameters control */ 170e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 171e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 172e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_EN_ON); 173e51df6ceSBen Chuang sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 174e51df6ceSBen Chuang 175e51df6ceSBen Chuang /* write tuning parameters */ 176e51df6ceSBen Chuang sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 177e51df6ceSBen Chuang 178e51df6ceSBen Chuang /* disable tuning parameters control */ 179e51df6ceSBen Chuang control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 180e51df6ceSBen Chuang control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 181e51df6ceSBen Chuang GLI_9750_TUNING_CONTROL_EN_OFF); 182e51df6ceSBen Chuang sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 183e51df6ceSBen Chuang 184e51df6ceSBen Chuang /* clear tuned clk */ 185e51df6ceSBen Chuang ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 186e51df6ceSBen Chuang ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 187e51df6ceSBen Chuang sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 188e51df6ceSBen Chuang 189e51df6ceSBen Chuang gl9750_wt_off(host); 190e51df6ceSBen Chuang } 191e51df6ceSBen Chuang 192e51df6ceSBen Chuang static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 193e51df6ceSBen Chuang { 194e51df6ceSBen Chuang u32 misc_value; 195e51df6ceSBen Chuang 196e51df6ceSBen Chuang gl9750_wt_on(host); 197e51df6ceSBen Chuang 198e51df6ceSBen Chuang misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 199e51df6ceSBen Chuang misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 200e51df6ceSBen Chuang if (b) { 201e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 202e51df6ceSBen Chuang GLI_9750_MISC_RX_INV_ON); 203e51df6ceSBen Chuang } else { 204e51df6ceSBen Chuang misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 205e51df6ceSBen Chuang GLI_9750_MISC_RX_INV_OFF); 206e51df6ceSBen Chuang } 207e51df6ceSBen Chuang sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 208e51df6ceSBen Chuang 209e51df6ceSBen Chuang gl9750_wt_off(host); 210e51df6ceSBen Chuang } 211e51df6ceSBen Chuang 212e51df6ceSBen Chuang static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 213e51df6ceSBen Chuang { 214e51df6ceSBen Chuang int i; 215e51df6ceSBen Chuang int rx_inv; 216e51df6ceSBen Chuang 217e51df6ceSBen Chuang for (rx_inv = 0; rx_inv < 2; rx_inv++) { 218e51df6ceSBen Chuang gli_set_9750_rx_inv(host, !!rx_inv); 219e51df6ceSBen Chuang sdhci_start_tuning(host); 220e51df6ceSBen Chuang 221e51df6ceSBen Chuang for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 222e51df6ceSBen Chuang u16 ctrl; 223e51df6ceSBen Chuang 224e51df6ceSBen Chuang sdhci_send_tuning(host, opcode); 225e51df6ceSBen Chuang 226e51df6ceSBen Chuang if (!host->tuning_done) { 227e51df6ceSBen Chuang sdhci_abort_tuning(host, opcode); 228e51df6ceSBen Chuang break; 229e51df6ceSBen Chuang } 230e51df6ceSBen Chuang 231e51df6ceSBen Chuang ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 232e51df6ceSBen Chuang if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 233e51df6ceSBen Chuang if (ctrl & SDHCI_CTRL_TUNED_CLK) 234e51df6ceSBen Chuang return 0; /* Success! */ 235e51df6ceSBen Chuang break; 236e51df6ceSBen Chuang } 237e51df6ceSBen Chuang } 238e51df6ceSBen Chuang } 239e51df6ceSBen Chuang if (!host->tuning_done) { 240e51df6ceSBen Chuang pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 241e51df6ceSBen Chuang mmc_hostname(host->mmc)); 242e51df6ceSBen Chuang return -ETIMEDOUT; 243e51df6ceSBen Chuang } 244e51df6ceSBen Chuang 245e51df6ceSBen Chuang pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 246e51df6ceSBen Chuang mmc_hostname(host->mmc)); 247e51df6ceSBen Chuang sdhci_reset_tuning(host); 248e51df6ceSBen Chuang 249e51df6ceSBen Chuang return -EAGAIN; 250e51df6ceSBen Chuang } 251e51df6ceSBen Chuang 252e51df6ceSBen Chuang static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 253e51df6ceSBen Chuang { 254e51df6ceSBen Chuang host->mmc->retune_period = 0; 255e51df6ceSBen Chuang if (host->tuning_mode == SDHCI_TUNING_MODE_1) 256e51df6ceSBen Chuang host->mmc->retune_period = host->tuning_count; 257e51df6ceSBen Chuang 258e51df6ceSBen Chuang gli_set_9750(host); 259e51df6ceSBen Chuang host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 260e51df6ceSBen Chuang sdhci_end_tuning(host); 261e51df6ceSBen Chuang 262e51df6ceSBen Chuang return 0; 263e51df6ceSBen Chuang } 264e51df6ceSBen Chuang 265e51df6ceSBen Chuang static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 266e51df6ceSBen Chuang { 267e51df6ceSBen Chuang struct sdhci_host *host = slot->host; 268e51df6ceSBen Chuang 269e51df6ceSBen Chuang slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 270e51df6ceSBen Chuang sdhci_enable_v4_mode(host); 271e51df6ceSBen Chuang 272e51df6ceSBen Chuang return 0; 273e51df6ceSBen Chuang } 274e51df6ceSBen Chuang 275e51df6ceSBen Chuang static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 276e51df6ceSBen Chuang { 277e51df6ceSBen Chuang struct sdhci_host *host = slot->host; 278e51df6ceSBen Chuang 279e51df6ceSBen Chuang slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 280e51df6ceSBen Chuang sdhci_enable_v4_mode(host); 281e51df6ceSBen Chuang 282e51df6ceSBen Chuang return 0; 283e51df6ceSBen Chuang } 284e51df6ceSBen Chuang 285e51df6ceSBen Chuang static void sdhci_gli_voltage_switch(struct sdhci_host *host) 286e51df6ceSBen Chuang { 287e51df6ceSBen Chuang /* 288e51df6ceSBen Chuang * According to Section 3.6.1 signal voltage switch procedure in 289e51df6ceSBen Chuang * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 290e51df6ceSBen Chuang * follows: 291e51df6ceSBen Chuang * (6) Set 1.8V Signal Enable in the Host Control 2 register. 292e51df6ceSBen Chuang * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 293e51df6ceSBen Chuang * period. 294e51df6ceSBen Chuang * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 295e51df6ceSBen Chuang * step (12). 296e51df6ceSBen Chuang * 297e51df6ceSBen Chuang * Wait 5ms after set 1.8V signal enable in Host Control 2 register 298e51df6ceSBen Chuang * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 299e51df6ceSBen Chuang */ 300e51df6ceSBen Chuang usleep_range(5000, 5500); 301e51df6ceSBen Chuang } 302e51df6ceSBen Chuang 303e51df6ceSBen Chuang static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 304e51df6ceSBen Chuang { 305e51df6ceSBen Chuang sdhci_reset(host, mask); 306e51df6ceSBen Chuang gli_set_9750(host); 307e51df6ceSBen Chuang } 308e51df6ceSBen Chuang 309e51df6ceSBen Chuang static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 310e51df6ceSBen Chuang { 311e51df6ceSBen Chuang u32 value; 312e51df6ceSBen Chuang 313e51df6ceSBen Chuang value = readl(host->ioaddr + reg); 314e51df6ceSBen Chuang if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 315e51df6ceSBen Chuang value |= 0xc8; 316e51df6ceSBen Chuang 317e51df6ceSBen Chuang return value; 318e51df6ceSBen Chuang } 319e51df6ceSBen Chuang 320e51df6ceSBen Chuang static const struct sdhci_ops sdhci_gl9755_ops = { 321e51df6ceSBen Chuang .set_clock = sdhci_set_clock, 322e51df6ceSBen Chuang .enable_dma = sdhci_pci_enable_dma, 323e51df6ceSBen Chuang .set_bus_width = sdhci_set_bus_width, 324e51df6ceSBen Chuang .reset = sdhci_reset, 325e51df6ceSBen Chuang .set_uhs_signaling = sdhci_set_uhs_signaling, 326e51df6ceSBen Chuang .voltage_switch = sdhci_gli_voltage_switch, 327e51df6ceSBen Chuang }; 328e51df6ceSBen Chuang 329e51df6ceSBen Chuang const struct sdhci_pci_fixes sdhci_gl9755 = { 330e51df6ceSBen Chuang .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 331e51df6ceSBen Chuang .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 332e51df6ceSBen Chuang .probe_slot = gli_probe_slot_gl9755, 333e51df6ceSBen Chuang .ops = &sdhci_gl9755_ops, 334e51df6ceSBen Chuang }; 335e51df6ceSBen Chuang 336e51df6ceSBen Chuang static const struct sdhci_ops sdhci_gl9750_ops = { 337e51df6ceSBen Chuang .read_l = sdhci_gl9750_readl, 338e51df6ceSBen Chuang .set_clock = sdhci_set_clock, 339e51df6ceSBen Chuang .enable_dma = sdhci_pci_enable_dma, 340e51df6ceSBen Chuang .set_bus_width = sdhci_set_bus_width, 341e51df6ceSBen Chuang .reset = sdhci_gl9750_reset, 342e51df6ceSBen Chuang .set_uhs_signaling = sdhci_set_uhs_signaling, 343e51df6ceSBen Chuang .voltage_switch = sdhci_gli_voltage_switch, 344e51df6ceSBen Chuang .platform_execute_tuning = gl9750_execute_tuning, 345e51df6ceSBen Chuang }; 346e51df6ceSBen Chuang 347e51df6ceSBen Chuang const struct sdhci_pci_fixes sdhci_gl9750 = { 348e51df6ceSBen Chuang .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 349e51df6ceSBen Chuang .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 350e51df6ceSBen Chuang .probe_slot = gli_probe_slot_gl9750, 351e51df6ceSBen Chuang .ops = &sdhci_gl9750_ops, 352e51df6ceSBen Chuang }; 353