1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller 4 * 5 * Copyright (C) 2018 Synaptics Incorporated 6 * 7 * Author: Jisheng Zhang <jszhang@kernel.org> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/sizes.h> 20 21 #include "sdhci-pltfm.h" 22 23 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 24 25 /* DWCMSHC specific Mode Select value */ 26 #define DWCMSHC_CTRL_HS400 0x7 27 28 /* DWC IP vendor area 1 pointer */ 29 #define DWCMSHC_P_VENDOR_AREA1 0xe8 30 #define DWCMSHC_AREA1_MASK GENMASK(11, 0) 31 /* Offset inside the vendor area 1 */ 32 #define DWCMSHC_HOST_CTRL3 0x8 33 #define DWCMSHC_EMMC_CONTROL 0x2c 34 #define DWCMSHC_CARD_IS_EMMC BIT(0) 35 #define DWCMSHC_ENHANCED_STROBE BIT(8) 36 #define DWCMSHC_EMMC_ATCTRL 0x40 37 38 /* Rockchip specific Registers */ 39 #define DWCMSHC_EMMC_DLL_CTRL 0x800 40 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 41 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 42 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 43 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 44 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 45 #define DWCMSHC_EMMC_DLL_START BIT(0) 46 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 47 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 48 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 49 #define DWCMSHC_EMMC_DLL_START_POINT 16 50 #define DWCMSHC_EMMC_DLL_INC 8 51 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 52 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 53 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 54 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA 55 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 56 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8 57 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 58 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 59 #define DLL_STRBIN_DELAY_NUM_OFFSET 16 60 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 61 #define DLL_RXCLK_NO_INVERTER 1 62 #define DLL_RXCLK_INVERTER 0 63 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 64 #define DLL_RXCLK_ORI_GATE BIT(31) 65 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 66 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 67 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 68 69 #define DLL_LOCK_WO_TMOUT(x) \ 70 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 71 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 72 #define RK35xx_MAX_CLKS 3 73 74 #define BOUNDARY_OK(addr, len) \ 75 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) 76 77 enum dwcmshc_rk_type { 78 DWCMSHC_RK3568, 79 DWCMSHC_RK3588, 80 }; 81 82 struct rk35xx_priv { 83 /* Rockchip specified optional clocks */ 84 struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; 85 struct reset_control *reset; 86 enum dwcmshc_rk_type devtype; 87 u8 txclk_tapnum; 88 }; 89 90 struct dwcmshc_priv { 91 struct clk *bus_clk; 92 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ 93 void *priv; /* pointer to SoC private stuff */ 94 }; 95 96 /* 97 * If DMA addr spans 128MB boundary, we split the DMA transfer into two 98 * so that each DMA transfer doesn't exceed the boundary. 99 */ 100 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, 101 dma_addr_t addr, int len, unsigned int cmd) 102 { 103 int tmplen, offset; 104 105 if (likely(!len || BOUNDARY_OK(addr, len))) { 106 sdhci_adma_write_desc(host, desc, addr, len, cmd); 107 return; 108 } 109 110 offset = addr & (SZ_128M - 1); 111 tmplen = SZ_128M - offset; 112 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); 113 114 addr += tmplen; 115 len -= tmplen; 116 sdhci_adma_write_desc(host, desc, addr, len, cmd); 117 } 118 119 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) 120 { 121 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 122 123 if (pltfm_host->clk) 124 return sdhci_pltfm_clk_get_max_clock(host); 125 else 126 return pltfm_host->clock; 127 } 128 129 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) 130 { 131 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 132 133 return clk_round_rate(pltfm_host->clk, ULONG_MAX); 134 } 135 136 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, 137 struct mmc_request *mrq) 138 { 139 struct sdhci_host *host = mmc_priv(mmc); 140 141 /* 142 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit 143 * block count register which doesn't support stuff bits of 144 * CMD23 argument on dwcmsch host controller. 145 */ 146 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) 147 host->flags &= ~SDHCI_AUTO_CMD23; 148 else 149 host->flags |= SDHCI_AUTO_CMD23; 150 } 151 152 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) 153 { 154 dwcmshc_check_auto_cmd23(mmc, mrq); 155 156 sdhci_request(mmc, mrq); 157 } 158 159 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, 160 unsigned int timing) 161 { 162 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 163 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 164 u16 ctrl, ctrl_2; 165 166 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 167 /* Select Bus Speed Mode for host */ 168 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 169 if ((timing == MMC_TIMING_MMC_HS200) || 170 (timing == MMC_TIMING_UHS_SDR104)) 171 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 172 else if (timing == MMC_TIMING_UHS_SDR12) 173 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 174 else if ((timing == MMC_TIMING_UHS_SDR25) || 175 (timing == MMC_TIMING_MMC_HS)) 176 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 177 else if (timing == MMC_TIMING_UHS_SDR50) 178 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 179 else if ((timing == MMC_TIMING_UHS_DDR50) || 180 (timing == MMC_TIMING_MMC_DDR52)) 181 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 182 else if (timing == MMC_TIMING_MMC_HS400) { 183 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ 184 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 185 ctrl |= DWCMSHC_CARD_IS_EMMC; 186 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 187 188 ctrl_2 |= DWCMSHC_CTRL_HS400; 189 } 190 191 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 192 } 193 194 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, 195 struct mmc_ios *ios) 196 { 197 u32 vendor; 198 struct sdhci_host *host = mmc_priv(mmc); 199 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 200 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 201 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; 202 203 vendor = sdhci_readl(host, reg); 204 if (ios->enhanced_strobe) 205 vendor |= DWCMSHC_ENHANCED_STROBE; 206 else 207 vendor &= ~DWCMSHC_ENHANCED_STROBE; 208 209 sdhci_writel(host, vendor, reg); 210 } 211 212 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 213 { 214 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 215 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 216 struct rk35xx_priv *priv = dwc_priv->priv; 217 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 218 u32 extra, reg; 219 int err; 220 221 host->mmc->actual_clock = 0; 222 223 if (clock == 0) { 224 /* Disable interface clock at initial state. */ 225 sdhci_set_clock(host, clock); 226 return; 227 } 228 229 /* Rockchip platform only support 375KHz for identify mode */ 230 if (clock <= 400000) 231 clock = 375000; 232 233 err = clk_set_rate(pltfm_host->clk, clock); 234 if (err) 235 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); 236 237 sdhci_set_clock(host, clock); 238 239 /* Disable cmd conflict check */ 240 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; 241 extra = sdhci_readl(host, reg); 242 extra &= ~BIT(0); 243 sdhci_writel(host, extra, reg); 244 245 if (clock <= 52000000) { 246 /* 247 * Disable DLL and reset both of sample and drive clock. 248 * The bypass bit and start bit need to be set if DLL is not locked. 249 */ 250 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); 251 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); 252 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 253 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 254 /* 255 * Before switching to hs400es mode, the driver will enable 256 * enhanced strobe first. PHY needs to configure the parameters 257 * of enhanced strobe first. 258 */ 259 extra = DWCMSHC_EMMC_DLL_DLYENA | 260 DLL_STRBIN_DELAY_NUM_SEL | 261 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; 262 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 263 return; 264 } 265 266 /* Reset DLL */ 267 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 268 udelay(1); 269 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); 270 271 /* 272 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but 273 * we must set it in higher speed mode. 274 */ 275 extra = DWCMSHC_EMMC_DLL_DLYENA; 276 if (priv->devtype == DWCMSHC_RK3568) 277 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 278 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 279 280 /* Init DLL settings */ 281 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 282 0x2 << DWCMSHC_EMMC_DLL_INC | 283 DWCMSHC_EMMC_DLL_START; 284 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 285 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, 286 extra, DLL_LOCK_WO_TMOUT(extra), 1, 287 500 * USEC_PER_MSEC); 288 if (err) { 289 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); 290 return; 291 } 292 293 extra = 0x1 << 16 | /* tune clock stop en */ 294 0x3 << 17 | /* pre-change delay */ 295 0x3 << 19; /* post-change delay */ 296 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 297 298 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || 299 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) 300 txclk_tapnum = priv->txclk_tapnum; 301 302 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 303 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; 304 305 extra = DLL_CMDOUT_SRC_CLK_NEG | 306 DLL_CMDOUT_EN_SRC_CLK_NEG | 307 DWCMSHC_EMMC_DLL_DLYENA | 308 DLL_CMDOUT_TAPNUM_90_DEGREES | 309 DLL_CMDOUT_TAPNUM_FROM_SW; 310 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 311 } 312 313 extra = DWCMSHC_EMMC_DLL_DLYENA | 314 DLL_TXCLK_TAPNUM_FROM_SW | 315 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | 316 txclk_tapnum; 317 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 318 319 extra = DWCMSHC_EMMC_DLL_DLYENA | 320 DLL_STRBIN_TAPNUM_DEFAULT | 321 DLL_STRBIN_TAPNUM_FROM_SW; 322 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 323 } 324 325 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) 326 { 327 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 328 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 329 struct rk35xx_priv *priv = dwc_priv->priv; 330 331 if (mask & SDHCI_RESET_ALL && priv->reset) { 332 reset_control_assert(priv->reset); 333 udelay(1); 334 reset_control_deassert(priv->reset); 335 } 336 337 sdhci_reset(host, mask); 338 } 339 340 static const struct sdhci_ops sdhci_dwcmshc_ops = { 341 .set_clock = sdhci_set_clock, 342 .set_bus_width = sdhci_set_bus_width, 343 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 344 .get_max_clock = dwcmshc_get_max_clock, 345 .reset = sdhci_reset, 346 .adma_write_desc = dwcmshc_adma_write_desc, 347 }; 348 349 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { 350 .set_clock = dwcmshc_rk3568_set_clock, 351 .set_bus_width = sdhci_set_bus_width, 352 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 353 .get_max_clock = rk35xx_get_max_clock, 354 .reset = rk35xx_sdhci_reset, 355 .adma_write_desc = dwcmshc_adma_write_desc, 356 }; 357 358 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { 359 .ops = &sdhci_dwcmshc_ops, 360 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 361 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 362 }; 363 364 #ifdef CONFIG_ACPI 365 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { 366 .ops = &sdhci_dwcmshc_ops, 367 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 368 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 369 SDHCI_QUIRK2_ACMD23_BROKEN, 370 }; 371 #endif 372 373 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 374 .ops = &sdhci_dwcmshc_rk35xx_ops, 375 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 376 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 377 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 378 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 379 }; 380 381 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 382 { 383 int err; 384 struct rk35xx_priv *priv = dwc_priv->priv; 385 386 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 387 if (IS_ERR(priv->reset)) { 388 err = PTR_ERR(priv->reset); 389 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 390 return err; 391 } 392 393 priv->rockchip_clks[0].id = "axi"; 394 priv->rockchip_clks[1].id = "block"; 395 priv->rockchip_clks[2].id = "timer"; 396 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, 397 priv->rockchip_clks); 398 if (err) { 399 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); 400 return err; 401 } 402 403 err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); 404 if (err) { 405 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); 406 return err; 407 } 408 409 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 410 &priv->txclk_tapnum)) 411 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 412 413 /* Disable cmd conflict check */ 414 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 415 /* Reset previous settings */ 416 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 417 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 418 419 return 0; 420 } 421 422 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 423 { 424 /* 425 * Don't support highspeed bus mode with low clk speed as we 426 * cannot use DLL for this condition. 427 */ 428 if (host->mmc->f_max <= 52000000) { 429 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 430 host->mmc->f_max); 431 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 432 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 433 } 434 } 435 436 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { 437 { 438 .compatible = "rockchip,rk3588-dwcmshc", 439 .data = &sdhci_dwcmshc_rk35xx_pdata, 440 }, 441 { 442 .compatible = "rockchip,rk3568-dwcmshc", 443 .data = &sdhci_dwcmshc_rk35xx_pdata, 444 }, 445 { 446 .compatible = "snps,dwcmshc-sdhci", 447 .data = &sdhci_dwcmshc_pdata, 448 }, 449 {}, 450 }; 451 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); 452 453 #ifdef CONFIG_ACPI 454 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { 455 { 456 .id = "MLNXBF30", 457 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata, 458 }, 459 {} 460 }; 461 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids); 462 #endif 463 464 static int dwcmshc_probe(struct platform_device *pdev) 465 { 466 struct device *dev = &pdev->dev; 467 struct sdhci_pltfm_host *pltfm_host; 468 struct sdhci_host *host; 469 struct dwcmshc_priv *priv; 470 struct rk35xx_priv *rk_priv = NULL; 471 const struct sdhci_pltfm_data *pltfm_data; 472 int err; 473 u32 extra; 474 475 pltfm_data = device_get_match_data(&pdev->dev); 476 if (!pltfm_data) { 477 dev_err(&pdev->dev, "Error: No device match data found\n"); 478 return -ENODEV; 479 } 480 481 host = sdhci_pltfm_init(pdev, pltfm_data, 482 sizeof(struct dwcmshc_priv)); 483 if (IS_ERR(host)) 484 return PTR_ERR(host); 485 486 /* 487 * extra adma table cnt for cross 128M boundary handling. 488 */ 489 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); 490 if (extra > SDHCI_MAX_SEGS) 491 extra = SDHCI_MAX_SEGS; 492 host->adma_table_cnt += extra; 493 494 pltfm_host = sdhci_priv(host); 495 priv = sdhci_pltfm_priv(pltfm_host); 496 497 if (dev->of_node) { 498 pltfm_host->clk = devm_clk_get(dev, "core"); 499 if (IS_ERR(pltfm_host->clk)) { 500 err = PTR_ERR(pltfm_host->clk); 501 dev_err(dev, "failed to get core clk: %d\n", err); 502 goto free_pltfm; 503 } 504 err = clk_prepare_enable(pltfm_host->clk); 505 if (err) 506 goto free_pltfm; 507 508 priv->bus_clk = devm_clk_get(dev, "bus"); 509 if (!IS_ERR(priv->bus_clk)) 510 clk_prepare_enable(priv->bus_clk); 511 } 512 513 err = mmc_of_parse(host->mmc); 514 if (err) 515 goto err_clk; 516 517 sdhci_get_of_property(pdev); 518 519 priv->vendor_specific_area1 = 520 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; 521 522 host->mmc_host_ops.request = dwcmshc_request; 523 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 524 525 if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { 526 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 527 if (!rk_priv) { 528 err = -ENOMEM; 529 goto err_clk; 530 } 531 532 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) 533 rk_priv->devtype = DWCMSHC_RK3588; 534 else 535 rk_priv->devtype = DWCMSHC_RK3568; 536 537 priv->priv = rk_priv; 538 539 err = dwcmshc_rk35xx_init(host, priv); 540 if (err) 541 goto err_clk; 542 } 543 544 #ifdef CONFIG_ACPI 545 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) 546 sdhci_enable_v4_mode(host); 547 #endif 548 549 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 550 551 err = sdhci_setup_host(host); 552 if (err) 553 goto err_clk; 554 555 if (rk_priv) 556 dwcmshc_rk35xx_postinit(host, priv); 557 558 err = __sdhci_add_host(host); 559 if (err) 560 goto err_setup_host; 561 562 return 0; 563 564 err_setup_host: 565 sdhci_cleanup_host(host); 566 err_clk: 567 clk_disable_unprepare(pltfm_host->clk); 568 clk_disable_unprepare(priv->bus_clk); 569 if (rk_priv) 570 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 571 rk_priv->rockchip_clks); 572 free_pltfm: 573 sdhci_pltfm_free(pdev); 574 return err; 575 } 576 577 static void dwcmshc_remove(struct platform_device *pdev) 578 { 579 struct sdhci_host *host = platform_get_drvdata(pdev); 580 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 581 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 582 struct rk35xx_priv *rk_priv = priv->priv; 583 584 sdhci_remove_host(host, 0); 585 586 clk_disable_unprepare(pltfm_host->clk); 587 clk_disable_unprepare(priv->bus_clk); 588 if (rk_priv) 589 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 590 rk_priv->rockchip_clks); 591 sdhci_pltfm_free(pdev); 592 } 593 594 #ifdef CONFIG_PM_SLEEP 595 static int dwcmshc_suspend(struct device *dev) 596 { 597 struct sdhci_host *host = dev_get_drvdata(dev); 598 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 599 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 600 struct rk35xx_priv *rk_priv = priv->priv; 601 int ret; 602 603 ret = sdhci_suspend_host(host); 604 if (ret) 605 return ret; 606 607 clk_disable_unprepare(pltfm_host->clk); 608 if (!IS_ERR(priv->bus_clk)) 609 clk_disable_unprepare(priv->bus_clk); 610 611 if (rk_priv) 612 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 613 rk_priv->rockchip_clks); 614 615 return ret; 616 } 617 618 static int dwcmshc_resume(struct device *dev) 619 { 620 struct sdhci_host *host = dev_get_drvdata(dev); 621 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 622 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 623 struct rk35xx_priv *rk_priv = priv->priv; 624 int ret; 625 626 ret = clk_prepare_enable(pltfm_host->clk); 627 if (ret) 628 return ret; 629 630 if (!IS_ERR(priv->bus_clk)) { 631 ret = clk_prepare_enable(priv->bus_clk); 632 if (ret) 633 goto disable_clk; 634 } 635 636 if (rk_priv) { 637 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, 638 rk_priv->rockchip_clks); 639 if (ret) 640 goto disable_bus_clk; 641 } 642 643 ret = sdhci_resume_host(host); 644 if (ret) 645 goto disable_rockchip_clks; 646 647 return 0; 648 649 disable_rockchip_clks: 650 if (rk_priv) 651 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 652 rk_priv->rockchip_clks); 653 disable_bus_clk: 654 if (!IS_ERR(priv->bus_clk)) 655 clk_disable_unprepare(priv->bus_clk); 656 disable_clk: 657 clk_disable_unprepare(pltfm_host->clk); 658 return ret; 659 } 660 #endif 661 662 static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume); 663 664 static struct platform_driver sdhci_dwcmshc_driver = { 665 .driver = { 666 .name = "sdhci-dwcmshc", 667 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 668 .of_match_table = sdhci_dwcmshc_dt_ids, 669 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), 670 .pm = &dwcmshc_pmops, 671 }, 672 .probe = dwcmshc_probe, 673 .remove_new = dwcmshc_remove, 674 }; 675 module_platform_driver(sdhci_dwcmshc_driver); 676 677 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC"); 678 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); 679 MODULE_LICENSE("GPL v2"); 680