1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller 4 * 5 * Copyright (C) 2018 Synaptics Incorporated 6 * 7 * Author: Jisheng Zhang <jszhang@kernel.org> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/reset.h> 19 #include <linux/sizes.h> 20 21 #include "sdhci-pltfm.h" 22 23 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 24 25 /* DWCMSHC specific Mode Select value */ 26 #define DWCMSHC_CTRL_HS400 0x7 27 28 /* DWC IP vendor area 1 pointer */ 29 #define DWCMSHC_P_VENDOR_AREA1 0xe8 30 #define DWCMSHC_AREA1_MASK GENMASK(11, 0) 31 /* Offset inside the vendor area 1 */ 32 #define DWCMSHC_HOST_CTRL3 0x8 33 #define DWCMSHC_EMMC_CONTROL 0x2c 34 #define DWCMSHC_CARD_IS_EMMC BIT(0) 35 #define DWCMSHC_ENHANCED_STROBE BIT(8) 36 #define DWCMSHC_EMMC_ATCTRL 0x40 37 38 /* Rockchip specific Registers */ 39 #define DWCMSHC_EMMC_DLL_CTRL 0x800 40 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 41 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 42 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 43 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 44 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 45 #define DWCMSHC_EMMC_DLL_START BIT(0) 46 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 47 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 48 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 49 #define DWCMSHC_EMMC_DLL_START_POINT 16 50 #define DWCMSHC_EMMC_DLL_INC 8 51 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 52 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 53 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 54 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA 55 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 56 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8 57 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 58 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 59 #define DLL_STRBIN_DELAY_NUM_OFFSET 16 60 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 61 #define DLL_RXCLK_NO_INVERTER 1 62 #define DLL_RXCLK_INVERTER 0 63 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 64 #define DLL_RXCLK_ORI_GATE BIT(31) 65 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 66 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 67 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 68 69 #define DLL_LOCK_WO_TMOUT(x) \ 70 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 71 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 72 #define RK35xx_MAX_CLKS 3 73 74 #define BOUNDARY_OK(addr, len) \ 75 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) 76 77 enum dwcmshc_rk_type { 78 DWCMSHC_RK3568, 79 DWCMSHC_RK3588, 80 }; 81 82 struct rk35xx_priv { 83 /* Rockchip specified optional clocks */ 84 struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; 85 struct reset_control *reset; 86 enum dwcmshc_rk_type devtype; 87 u8 txclk_tapnum; 88 }; 89 90 struct dwcmshc_priv { 91 struct clk *bus_clk; 92 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ 93 void *priv; /* pointer to SoC private stuff */ 94 }; 95 96 /* 97 * If DMA addr spans 128MB boundary, we split the DMA transfer into two 98 * so that each DMA transfer doesn't exceed the boundary. 99 */ 100 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, 101 dma_addr_t addr, int len, unsigned int cmd) 102 { 103 int tmplen, offset; 104 105 if (likely(!len || BOUNDARY_OK(addr, len))) { 106 sdhci_adma_write_desc(host, desc, addr, len, cmd); 107 return; 108 } 109 110 offset = addr & (SZ_128M - 1); 111 tmplen = SZ_128M - offset; 112 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); 113 114 addr += tmplen; 115 len -= tmplen; 116 sdhci_adma_write_desc(host, desc, addr, len, cmd); 117 } 118 119 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) 120 { 121 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 122 123 if (pltfm_host->clk) 124 return sdhci_pltfm_clk_get_max_clock(host); 125 else 126 return pltfm_host->clock; 127 } 128 129 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, 130 struct mmc_request *mrq) 131 { 132 struct sdhci_host *host = mmc_priv(mmc); 133 134 /* 135 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit 136 * block count register which doesn't support stuff bits of 137 * CMD23 argument on dwcmsch host controller. 138 */ 139 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) 140 host->flags &= ~SDHCI_AUTO_CMD23; 141 else 142 host->flags |= SDHCI_AUTO_CMD23; 143 } 144 145 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) 146 { 147 dwcmshc_check_auto_cmd23(mmc, mrq); 148 149 sdhci_request(mmc, mrq); 150 } 151 152 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, 153 unsigned int timing) 154 { 155 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 156 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 157 u16 ctrl, ctrl_2; 158 159 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 160 /* Select Bus Speed Mode for host */ 161 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 162 if ((timing == MMC_TIMING_MMC_HS200) || 163 (timing == MMC_TIMING_UHS_SDR104)) 164 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 165 else if (timing == MMC_TIMING_UHS_SDR12) 166 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 167 else if ((timing == MMC_TIMING_UHS_SDR25) || 168 (timing == MMC_TIMING_MMC_HS)) 169 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 170 else if (timing == MMC_TIMING_UHS_SDR50) 171 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 172 else if ((timing == MMC_TIMING_UHS_DDR50) || 173 (timing == MMC_TIMING_MMC_DDR52)) 174 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 175 else if (timing == MMC_TIMING_MMC_HS400) { 176 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ 177 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 178 ctrl |= DWCMSHC_CARD_IS_EMMC; 179 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 180 181 ctrl_2 |= DWCMSHC_CTRL_HS400; 182 } 183 184 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 185 } 186 187 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, 188 struct mmc_ios *ios) 189 { 190 u32 vendor; 191 struct sdhci_host *host = mmc_priv(mmc); 192 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 193 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 194 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; 195 196 vendor = sdhci_readl(host, reg); 197 if (ios->enhanced_strobe) 198 vendor |= DWCMSHC_ENHANCED_STROBE; 199 else 200 vendor &= ~DWCMSHC_ENHANCED_STROBE; 201 202 sdhci_writel(host, vendor, reg); 203 } 204 205 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 206 { 207 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 208 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 209 struct rk35xx_priv *priv = dwc_priv->priv; 210 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 211 u32 extra, reg; 212 int err; 213 214 host->mmc->actual_clock = 0; 215 216 if (clock == 0) { 217 /* Disable interface clock at initial state. */ 218 sdhci_set_clock(host, clock); 219 return; 220 } 221 222 /* Rockchip platform only support 375KHz for identify mode */ 223 if (clock <= 400000) 224 clock = 375000; 225 226 err = clk_set_rate(pltfm_host->clk, clock); 227 if (err) 228 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); 229 230 sdhci_set_clock(host, clock); 231 232 /* Disable cmd conflict check */ 233 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; 234 extra = sdhci_readl(host, reg); 235 extra &= ~BIT(0); 236 sdhci_writel(host, extra, reg); 237 238 if (clock <= 52000000) { 239 /* 240 * Disable DLL and reset both of sample and drive clock. 241 * The bypass bit and start bit need to be set if DLL is not locked. 242 */ 243 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); 244 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); 245 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 246 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 247 /* 248 * Before switching to hs400es mode, the driver will enable 249 * enhanced strobe first. PHY needs to configure the parameters 250 * of enhanced strobe first. 251 */ 252 extra = DWCMSHC_EMMC_DLL_DLYENA | 253 DLL_STRBIN_DELAY_NUM_SEL | 254 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; 255 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 256 return; 257 } 258 259 /* Reset DLL */ 260 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 261 udelay(1); 262 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); 263 264 /* 265 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but 266 * we must set it in higher speed mode. 267 */ 268 extra = DWCMSHC_EMMC_DLL_DLYENA; 269 if (priv->devtype == DWCMSHC_RK3568) 270 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 271 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 272 273 /* Init DLL settings */ 274 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 275 0x2 << DWCMSHC_EMMC_DLL_INC | 276 DWCMSHC_EMMC_DLL_START; 277 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 278 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, 279 extra, DLL_LOCK_WO_TMOUT(extra), 1, 280 500 * USEC_PER_MSEC); 281 if (err) { 282 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); 283 return; 284 } 285 286 extra = 0x1 << 16 | /* tune clock stop en */ 287 0x3 << 17 | /* pre-change delay */ 288 0x3 << 19; /* post-change delay */ 289 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 290 291 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || 292 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) 293 txclk_tapnum = priv->txclk_tapnum; 294 295 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 296 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; 297 298 extra = DLL_CMDOUT_SRC_CLK_NEG | 299 DLL_CMDOUT_EN_SRC_CLK_NEG | 300 DWCMSHC_EMMC_DLL_DLYENA | 301 DLL_CMDOUT_TAPNUM_90_DEGREES | 302 DLL_CMDOUT_TAPNUM_FROM_SW; 303 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 304 } 305 306 extra = DWCMSHC_EMMC_DLL_DLYENA | 307 DLL_TXCLK_TAPNUM_FROM_SW | 308 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | 309 txclk_tapnum; 310 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 311 312 extra = DWCMSHC_EMMC_DLL_DLYENA | 313 DLL_STRBIN_TAPNUM_DEFAULT | 314 DLL_STRBIN_TAPNUM_FROM_SW; 315 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 316 } 317 318 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) 319 { 320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 321 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 322 struct rk35xx_priv *priv = dwc_priv->priv; 323 324 if (mask & SDHCI_RESET_ALL && priv->reset) { 325 reset_control_assert(priv->reset); 326 udelay(1); 327 reset_control_deassert(priv->reset); 328 } 329 330 sdhci_reset(host, mask); 331 } 332 333 static const struct sdhci_ops sdhci_dwcmshc_ops = { 334 .set_clock = sdhci_set_clock, 335 .set_bus_width = sdhci_set_bus_width, 336 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 337 .get_max_clock = dwcmshc_get_max_clock, 338 .reset = sdhci_reset, 339 .adma_write_desc = dwcmshc_adma_write_desc, 340 }; 341 342 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { 343 .set_clock = dwcmshc_rk3568_set_clock, 344 .set_bus_width = sdhci_set_bus_width, 345 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 346 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 347 .reset = rk35xx_sdhci_reset, 348 .adma_write_desc = dwcmshc_adma_write_desc, 349 }; 350 351 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { 352 .ops = &sdhci_dwcmshc_ops, 353 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 354 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 355 }; 356 357 #ifdef CONFIG_ACPI 358 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { 359 .ops = &sdhci_dwcmshc_ops, 360 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 361 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 362 SDHCI_QUIRK2_ACMD23_BROKEN, 363 }; 364 #endif 365 366 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 367 .ops = &sdhci_dwcmshc_rk35xx_ops, 368 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 369 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 370 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 371 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 372 }; 373 374 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 375 { 376 int err; 377 struct rk35xx_priv *priv = dwc_priv->priv; 378 379 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 380 if (IS_ERR(priv->reset)) { 381 err = PTR_ERR(priv->reset); 382 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 383 return err; 384 } 385 386 priv->rockchip_clks[0].id = "axi"; 387 priv->rockchip_clks[1].id = "block"; 388 priv->rockchip_clks[2].id = "timer"; 389 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, 390 priv->rockchip_clks); 391 if (err) { 392 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); 393 return err; 394 } 395 396 err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); 397 if (err) { 398 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); 399 return err; 400 } 401 402 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 403 &priv->txclk_tapnum)) 404 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 405 406 /* Disable cmd conflict check */ 407 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 408 /* Reset previous settings */ 409 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 410 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 411 412 return 0; 413 } 414 415 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 416 { 417 /* 418 * Don't support highspeed bus mode with low clk speed as we 419 * cannot use DLL for this condition. 420 */ 421 if (host->mmc->f_max <= 52000000) { 422 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 423 host->mmc->f_max); 424 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 425 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 426 } 427 } 428 429 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { 430 { 431 .compatible = "rockchip,rk3588-dwcmshc", 432 .data = &sdhci_dwcmshc_rk35xx_pdata, 433 }, 434 { 435 .compatible = "rockchip,rk3568-dwcmshc", 436 .data = &sdhci_dwcmshc_rk35xx_pdata, 437 }, 438 { 439 .compatible = "snps,dwcmshc-sdhci", 440 .data = &sdhci_dwcmshc_pdata, 441 }, 442 {}, 443 }; 444 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); 445 446 #ifdef CONFIG_ACPI 447 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { 448 { 449 .id = "MLNXBF30", 450 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata, 451 }, 452 {} 453 }; 454 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids); 455 #endif 456 457 static int dwcmshc_probe(struct platform_device *pdev) 458 { 459 struct device *dev = &pdev->dev; 460 struct sdhci_pltfm_host *pltfm_host; 461 struct sdhci_host *host; 462 struct dwcmshc_priv *priv; 463 struct rk35xx_priv *rk_priv = NULL; 464 const struct sdhci_pltfm_data *pltfm_data; 465 int err; 466 u32 extra; 467 468 pltfm_data = device_get_match_data(&pdev->dev); 469 if (!pltfm_data) { 470 dev_err(&pdev->dev, "Error: No device match data found\n"); 471 return -ENODEV; 472 } 473 474 host = sdhci_pltfm_init(pdev, pltfm_data, 475 sizeof(struct dwcmshc_priv)); 476 if (IS_ERR(host)) 477 return PTR_ERR(host); 478 479 /* 480 * extra adma table cnt for cross 128M boundary handling. 481 */ 482 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); 483 if (extra > SDHCI_MAX_SEGS) 484 extra = SDHCI_MAX_SEGS; 485 host->adma_table_cnt += extra; 486 487 pltfm_host = sdhci_priv(host); 488 priv = sdhci_pltfm_priv(pltfm_host); 489 490 if (dev->of_node) { 491 pltfm_host->clk = devm_clk_get(dev, "core"); 492 if (IS_ERR(pltfm_host->clk)) { 493 err = PTR_ERR(pltfm_host->clk); 494 dev_err(dev, "failed to get core clk: %d\n", err); 495 goto free_pltfm; 496 } 497 err = clk_prepare_enable(pltfm_host->clk); 498 if (err) 499 goto free_pltfm; 500 501 priv->bus_clk = devm_clk_get(dev, "bus"); 502 if (!IS_ERR(priv->bus_clk)) 503 clk_prepare_enable(priv->bus_clk); 504 } 505 506 err = mmc_of_parse(host->mmc); 507 if (err) 508 goto err_clk; 509 510 sdhci_get_of_property(pdev); 511 512 priv->vendor_specific_area1 = 513 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; 514 515 host->mmc_host_ops.request = dwcmshc_request; 516 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 517 518 if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { 519 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 520 if (!rk_priv) { 521 err = -ENOMEM; 522 goto err_clk; 523 } 524 525 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) 526 rk_priv->devtype = DWCMSHC_RK3588; 527 else 528 rk_priv->devtype = DWCMSHC_RK3568; 529 530 priv->priv = rk_priv; 531 532 err = dwcmshc_rk35xx_init(host, priv); 533 if (err) 534 goto err_clk; 535 } 536 537 #ifdef CONFIG_ACPI 538 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) 539 sdhci_enable_v4_mode(host); 540 #endif 541 542 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 543 544 err = sdhci_setup_host(host); 545 if (err) 546 goto err_clk; 547 548 if (rk_priv) 549 dwcmshc_rk35xx_postinit(host, priv); 550 551 err = __sdhci_add_host(host); 552 if (err) 553 goto err_setup_host; 554 555 return 0; 556 557 err_setup_host: 558 sdhci_cleanup_host(host); 559 err_clk: 560 clk_disable_unprepare(pltfm_host->clk); 561 clk_disable_unprepare(priv->bus_clk); 562 if (rk_priv) 563 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 564 rk_priv->rockchip_clks); 565 free_pltfm: 566 sdhci_pltfm_free(pdev); 567 return err; 568 } 569 570 static int dwcmshc_remove(struct platform_device *pdev) 571 { 572 struct sdhci_host *host = platform_get_drvdata(pdev); 573 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 574 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 575 struct rk35xx_priv *rk_priv = priv->priv; 576 577 sdhci_remove_host(host, 0); 578 579 clk_disable_unprepare(pltfm_host->clk); 580 clk_disable_unprepare(priv->bus_clk); 581 if (rk_priv) 582 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 583 rk_priv->rockchip_clks); 584 sdhci_pltfm_free(pdev); 585 586 return 0; 587 } 588 589 #ifdef CONFIG_PM_SLEEP 590 static int dwcmshc_suspend(struct device *dev) 591 { 592 struct sdhci_host *host = dev_get_drvdata(dev); 593 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 594 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 595 struct rk35xx_priv *rk_priv = priv->priv; 596 int ret; 597 598 ret = sdhci_suspend_host(host); 599 if (ret) 600 return ret; 601 602 clk_disable_unprepare(pltfm_host->clk); 603 if (!IS_ERR(priv->bus_clk)) 604 clk_disable_unprepare(priv->bus_clk); 605 606 if (rk_priv) 607 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 608 rk_priv->rockchip_clks); 609 610 return ret; 611 } 612 613 static int dwcmshc_resume(struct device *dev) 614 { 615 struct sdhci_host *host = dev_get_drvdata(dev); 616 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 617 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 618 struct rk35xx_priv *rk_priv = priv->priv; 619 int ret; 620 621 ret = clk_prepare_enable(pltfm_host->clk); 622 if (ret) 623 return ret; 624 625 if (!IS_ERR(priv->bus_clk)) { 626 ret = clk_prepare_enable(priv->bus_clk); 627 if (ret) 628 return ret; 629 } 630 631 if (rk_priv) { 632 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, 633 rk_priv->rockchip_clks); 634 if (ret) 635 return ret; 636 } 637 638 return sdhci_resume_host(host); 639 } 640 #endif 641 642 static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume); 643 644 static struct platform_driver sdhci_dwcmshc_driver = { 645 .driver = { 646 .name = "sdhci-dwcmshc", 647 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 648 .of_match_table = sdhci_dwcmshc_dt_ids, 649 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), 650 .pm = &dwcmshc_pmops, 651 }, 652 .probe = dwcmshc_probe, 653 .remove = dwcmshc_remove, 654 }; 655 module_platform_driver(sdhci_dwcmshc_driver); 656 657 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC"); 658 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); 659 MODULE_LICENSE("GPL v2"); 660