197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
29cb15142SSrinivas Kandagatla /*
39cb15142SSrinivas Kandagatla *
49cb15142SSrinivas Kandagatla * Copyright (c) 2011, The Linux Foundation. All rights reserved.
59cb15142SSrinivas Kandagatla */
69cb15142SSrinivas Kandagatla #include <linux/of.h>
79cb15142SSrinivas Kandagatla #include <linux/of_dma.h>
89cb15142SSrinivas Kandagatla #include <linux/bitops.h>
99cb15142SSrinivas Kandagatla #include <linux/mmc/host.h>
109cb15142SSrinivas Kandagatla #include <linux/mmc/card.h>
119cb15142SSrinivas Kandagatla #include "mmci.h"
129cb15142SSrinivas Kandagatla
139cb15142SSrinivas Kandagatla /* Registers */
149cb15142SSrinivas Kandagatla #define DML_CONFIG 0x00
159cb15142SSrinivas Kandagatla #define PRODUCER_CRCI_MSK GENMASK(1, 0)
169cb15142SSrinivas Kandagatla #define PRODUCER_CRCI_DISABLE 0
179cb15142SSrinivas Kandagatla #define PRODUCER_CRCI_X_SEL BIT(0)
189cb15142SSrinivas Kandagatla #define PRODUCER_CRCI_Y_SEL BIT(1)
199cb15142SSrinivas Kandagatla #define CONSUMER_CRCI_MSK GENMASK(3, 2)
209cb15142SSrinivas Kandagatla #define CONSUMER_CRCI_DISABLE 0
219cb15142SSrinivas Kandagatla #define CONSUMER_CRCI_X_SEL BIT(2)
229cb15142SSrinivas Kandagatla #define CONSUMER_CRCI_Y_SEL BIT(3)
239cb15142SSrinivas Kandagatla #define PRODUCER_TRANS_END_EN BIT(4)
249cb15142SSrinivas Kandagatla #define BYPASS BIT(16)
259cb15142SSrinivas Kandagatla #define DIRECT_MODE BIT(17)
269cb15142SSrinivas Kandagatla #define INFINITE_CONS_TRANS BIT(18)
279cb15142SSrinivas Kandagatla
289cb15142SSrinivas Kandagatla #define DML_SW_RESET 0x08
299cb15142SSrinivas Kandagatla #define DML_PRODUCER_START 0x0c
309cb15142SSrinivas Kandagatla #define DML_CONSUMER_START 0x10
319cb15142SSrinivas Kandagatla #define DML_PRODUCER_PIPE_LOGICAL_SIZE 0x14
329cb15142SSrinivas Kandagatla #define DML_CONSUMER_PIPE_LOGICAL_SIZE 0x18
339cb15142SSrinivas Kandagatla #define DML_PIPE_ID 0x1c
349cb15142SSrinivas Kandagatla #define PRODUCER_PIPE_ID_SHFT 0
359cb15142SSrinivas Kandagatla #define PRODUCER_PIPE_ID_MSK GENMASK(4, 0)
369cb15142SSrinivas Kandagatla #define CONSUMER_PIPE_ID_SHFT 16
379cb15142SSrinivas Kandagatla #define CONSUMER_PIPE_ID_MSK GENMASK(20, 16)
389cb15142SSrinivas Kandagatla
399cb15142SSrinivas Kandagatla #define DML_PRODUCER_BAM_BLOCK_SIZE 0x24
409cb15142SSrinivas Kandagatla #define DML_PRODUCER_BAM_TRANS_SIZE 0x28
419cb15142SSrinivas Kandagatla
429cb15142SSrinivas Kandagatla /* other definitions */
439cb15142SSrinivas Kandagatla #define PRODUCER_PIPE_LOGICAL_SIZE 4096
449cb15142SSrinivas Kandagatla #define CONSUMER_PIPE_LOGICAL_SIZE 4096
459cb15142SSrinivas Kandagatla
469cb15142SSrinivas Kandagatla #define DML_OFFSET 0x800
479cb15142SSrinivas Kandagatla
qcom_dma_start(struct mmci_host * host,unsigned int * datactrl)48ea27c95aSUlf Hansson static int qcom_dma_start(struct mmci_host *host, unsigned int *datactrl)
499cb15142SSrinivas Kandagatla {
509cb15142SSrinivas Kandagatla u32 config;
519cb15142SSrinivas Kandagatla void __iomem *base = host->base + DML_OFFSET;
52ea27c95aSUlf Hansson struct mmc_data *data = host->data;
53ea27c95aSUlf Hansson int ret = mmci_dmae_start(host, datactrl);
54ea27c95aSUlf Hansson
55ea27c95aSUlf Hansson if (ret)
56ea27c95aSUlf Hansson return ret;
579cb15142SSrinivas Kandagatla
589cb15142SSrinivas Kandagatla if (data->flags & MMC_DATA_READ) {
599cb15142SSrinivas Kandagatla /* Read operation: configure DML for producer operation */
609cb15142SSrinivas Kandagatla /* Set producer CRCI-x and disable consumer CRCI */
619cb15142SSrinivas Kandagatla config = readl_relaxed(base + DML_CONFIG);
629cb15142SSrinivas Kandagatla config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_X_SEL;
639cb15142SSrinivas Kandagatla config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_DISABLE;
649cb15142SSrinivas Kandagatla writel_relaxed(config, base + DML_CONFIG);
659cb15142SSrinivas Kandagatla
669cb15142SSrinivas Kandagatla /* Set the Producer BAM block size */
679cb15142SSrinivas Kandagatla writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE);
689cb15142SSrinivas Kandagatla
699cb15142SSrinivas Kandagatla /* Set Producer BAM Transaction size */
709cb15142SSrinivas Kandagatla writel_relaxed(data->blocks * data->blksz,
719cb15142SSrinivas Kandagatla base + DML_PRODUCER_BAM_TRANS_SIZE);
729cb15142SSrinivas Kandagatla /* Set Producer Transaction End bit */
739cb15142SSrinivas Kandagatla config = readl_relaxed(base + DML_CONFIG);
749cb15142SSrinivas Kandagatla config |= PRODUCER_TRANS_END_EN;
759cb15142SSrinivas Kandagatla writel_relaxed(config, base + DML_CONFIG);
769cb15142SSrinivas Kandagatla /* Trigger producer */
779cb15142SSrinivas Kandagatla writel_relaxed(1, base + DML_PRODUCER_START);
789cb15142SSrinivas Kandagatla } else {
799cb15142SSrinivas Kandagatla /* Write operation: configure DML for consumer operation */
809cb15142SSrinivas Kandagatla /* Set consumer CRCI-x and disable producer CRCI*/
819cb15142SSrinivas Kandagatla config = readl_relaxed(base + DML_CONFIG);
829cb15142SSrinivas Kandagatla config = (config & ~CONSUMER_CRCI_MSK) | CONSUMER_CRCI_X_SEL;
839cb15142SSrinivas Kandagatla config = (config & ~PRODUCER_CRCI_MSK) | PRODUCER_CRCI_DISABLE;
849cb15142SSrinivas Kandagatla writel_relaxed(config, base + DML_CONFIG);
859cb15142SSrinivas Kandagatla /* Clear Producer Transaction End bit */
869cb15142SSrinivas Kandagatla config = readl_relaxed(base + DML_CONFIG);
879cb15142SSrinivas Kandagatla config &= ~PRODUCER_TRANS_END_EN;
889cb15142SSrinivas Kandagatla writel_relaxed(config, base + DML_CONFIG);
899cb15142SSrinivas Kandagatla /* Trigger consumer */
909cb15142SSrinivas Kandagatla writel_relaxed(1, base + DML_CONSUMER_START);
919cb15142SSrinivas Kandagatla }
929cb15142SSrinivas Kandagatla
939cb15142SSrinivas Kandagatla /* make sure the dml is configured before dma is triggered */
949cb15142SSrinivas Kandagatla wmb();
95ea27c95aSUlf Hansson return 0;
969cb15142SSrinivas Kandagatla }
979cb15142SSrinivas Kandagatla
of_get_dml_pipe_index(struct device_node * np,const char * name)989cb15142SSrinivas Kandagatla static int of_get_dml_pipe_index(struct device_node *np, const char *name)
999cb15142SSrinivas Kandagatla {
1009cb15142SSrinivas Kandagatla int index;
1019cb15142SSrinivas Kandagatla struct of_phandle_args dma_spec;
1029cb15142SSrinivas Kandagatla
1039cb15142SSrinivas Kandagatla index = of_property_match_string(np, "dma-names", name);
1049cb15142SSrinivas Kandagatla
1059cb15142SSrinivas Kandagatla if (index < 0)
1069cb15142SSrinivas Kandagatla return -ENODEV;
1079cb15142SSrinivas Kandagatla
1089cb15142SSrinivas Kandagatla if (of_parse_phandle_with_args(np, "dmas", "#dma-cells", index,
1099cb15142SSrinivas Kandagatla &dma_spec))
1109cb15142SSrinivas Kandagatla return -ENODEV;
1119cb15142SSrinivas Kandagatla
1129cb15142SSrinivas Kandagatla if (dma_spec.args_count)
1139cb15142SSrinivas Kandagatla return dma_spec.args[0];
1149cb15142SSrinivas Kandagatla
1159cb15142SSrinivas Kandagatla return -ENODEV;
1169cb15142SSrinivas Kandagatla }
1179cb15142SSrinivas Kandagatla
1189cb15142SSrinivas Kandagatla /* Initialize the dml hardware connected to SD Card controller */
qcom_dma_setup(struct mmci_host * host)119c3647fdcSLudovic Barre static int qcom_dma_setup(struct mmci_host *host)
1209cb15142SSrinivas Kandagatla {
1219cb15142SSrinivas Kandagatla u32 config;
1229cb15142SSrinivas Kandagatla void __iomem *base;
1239cb15142SSrinivas Kandagatla int consumer_id, producer_id;
12429aba07aSUlf Hansson struct device_node *np = host->mmc->parent->of_node;
1259cb15142SSrinivas Kandagatla
126c3647fdcSLudovic Barre if (mmci_dmae_setup(host))
127c3647fdcSLudovic Barre return -EINVAL;
128c3647fdcSLudovic Barre
1299cb15142SSrinivas Kandagatla consumer_id = of_get_dml_pipe_index(np, "tx");
1309cb15142SSrinivas Kandagatla producer_id = of_get_dml_pipe_index(np, "rx");
1319cb15142SSrinivas Kandagatla
13229aba07aSUlf Hansson if (producer_id < 0 || consumer_id < 0) {
133c3647fdcSLudovic Barre mmci_dmae_release(host);
134c3647fdcSLudovic Barre return -EINVAL;
13529aba07aSUlf Hansson }
1369cb15142SSrinivas Kandagatla
1379cb15142SSrinivas Kandagatla base = host->base + DML_OFFSET;
1389cb15142SSrinivas Kandagatla
1399cb15142SSrinivas Kandagatla /* Reset the DML block */
1409cb15142SSrinivas Kandagatla writel_relaxed(1, base + DML_SW_RESET);
1419cb15142SSrinivas Kandagatla
1429cb15142SSrinivas Kandagatla /* Disable the producer and consumer CRCI */
1439cb15142SSrinivas Kandagatla config = (PRODUCER_CRCI_DISABLE | CONSUMER_CRCI_DISABLE);
1449cb15142SSrinivas Kandagatla /*
1459cb15142SSrinivas Kandagatla * Disable the bypass mode. Bypass mode will only be used
1469cb15142SSrinivas Kandagatla * if data transfer is to happen in PIO mode and don't
1479cb15142SSrinivas Kandagatla * want the BAM interface to connect with SDCC-DML.
1489cb15142SSrinivas Kandagatla */
1499cb15142SSrinivas Kandagatla config &= ~BYPASS;
1509cb15142SSrinivas Kandagatla /*
1519cb15142SSrinivas Kandagatla * Disable direct mode as we don't DML to MASTER the AHB bus.
1529cb15142SSrinivas Kandagatla * BAM connected with DML should MASTER the AHB bus.
1539cb15142SSrinivas Kandagatla */
1549cb15142SSrinivas Kandagatla config &= ~DIRECT_MODE;
1559cb15142SSrinivas Kandagatla /*
1569cb15142SSrinivas Kandagatla * Disable infinite mode transfer as we won't be doing any
1579cb15142SSrinivas Kandagatla * infinite size data transfers. All data transfer will be
1589cb15142SSrinivas Kandagatla * of finite data size.
1599cb15142SSrinivas Kandagatla */
1609cb15142SSrinivas Kandagatla config &= ~INFINITE_CONS_TRANS;
1619cb15142SSrinivas Kandagatla writel_relaxed(config, base + DML_CONFIG);
1629cb15142SSrinivas Kandagatla
1639cb15142SSrinivas Kandagatla /*
1649cb15142SSrinivas Kandagatla * Initialize the logical BAM pipe size for producer
1659cb15142SSrinivas Kandagatla * and consumer.
1669cb15142SSrinivas Kandagatla */
1679cb15142SSrinivas Kandagatla writel_relaxed(PRODUCER_PIPE_LOGICAL_SIZE,
1689cb15142SSrinivas Kandagatla base + DML_PRODUCER_PIPE_LOGICAL_SIZE);
1699cb15142SSrinivas Kandagatla writel_relaxed(CONSUMER_PIPE_LOGICAL_SIZE,
1709cb15142SSrinivas Kandagatla base + DML_CONSUMER_PIPE_LOGICAL_SIZE);
1719cb15142SSrinivas Kandagatla
1729cb15142SSrinivas Kandagatla /* Initialize Producer/consumer pipe id */
1739cb15142SSrinivas Kandagatla writel_relaxed(producer_id | (consumer_id << CONSUMER_PIPE_ID_SHFT),
1749cb15142SSrinivas Kandagatla base + DML_PIPE_ID);
1759cb15142SSrinivas Kandagatla
176183b8021SMasahiro Yamada /* Make sure dml initialization is finished */
1779cb15142SSrinivas Kandagatla mb();
178c3647fdcSLudovic Barre
179c3647fdcSLudovic Barre return 0;
18029aba07aSUlf Hansson }
1819cb15142SSrinivas Kandagatla
qcom_get_dctrl_cfg(struct mmci_host * host)1825db1e1fcSLudovic Barre static u32 qcom_get_dctrl_cfg(struct mmci_host *host)
1835db1e1fcSLudovic Barre {
1845db1e1fcSLudovic Barre return MCI_DPSM_ENABLE | (host->data->blksz << 4);
1855db1e1fcSLudovic Barre }
1865db1e1fcSLudovic Barre
18729aba07aSUlf Hansson static struct mmci_host_ops qcom_variant_ops = {
18847983510SLudovic Barre .prep_data = mmci_dmae_prep_data,
18947983510SLudovic Barre .unprep_data = mmci_dmae_unprep_data,
1905db1e1fcSLudovic Barre .get_datactrl_cfg = qcom_get_dctrl_cfg,
19102769968SLudovic Barre .get_next_data = mmci_dmae_get_next_data,
19229aba07aSUlf Hansson .dma_setup = qcom_dma_setup,
193c3647fdcSLudovic Barre .dma_release = mmci_dmae_release,
194ea27c95aSUlf Hansson .dma_start = qcom_dma_start,
1955a9f10c3SLudovic Barre .dma_finalize = mmci_dmae_finalize,
196cfccc6acSLudovic Barre .dma_error = mmci_dmae_error,
19729aba07aSUlf Hansson };
19829aba07aSUlf Hansson
qcom_variant_init(struct mmci_host * host)19929aba07aSUlf Hansson void qcom_variant_init(struct mmci_host *host)
20029aba07aSUlf Hansson {
20129aba07aSUlf Hansson host->ops = &qcom_variant_ops;
2029cb15142SSrinivas Kandagatla }
203