1 /* 2 * bcm2835 sdhost driver. 3 * 4 * The 2835 has two SD controllers: The Arasan sdhci controller 5 * (supported by the iproc driver) and a custom sdhost controller 6 * (supported by this driver). 7 * 8 * The sdhci controller supports both sdcard and sdio. The sdhost 9 * controller supports the sdcard only, but has better performance. 10 * Also note that the rpi3 has sdio wifi, so driving the sdcard with 11 * the sdhost controller allows to use the sdhci controller for wifi 12 * support. 13 * 14 * The configuration is done by devicetree via pin muxing. Both 15 * SD controller are available on the same pins (2 pin groups = pin 22 16 * to 27 + pin 48 to 53). So it's possible to use both SD controllers 17 * at the same time with different pin groups. 18 * 19 * Author: Phil Elwell <phil@raspberrypi.org> 20 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 21 * 22 * Based on 23 * mmc-bcm2835.c by Gellert Weisz 24 * which is, in turn, based on 25 * sdhci-bcm2708.c by Broadcom 26 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 27 * sdhci.c and sdhci-pci.c by Pierre Ossman 28 * 29 * This program is free software; you can redistribute it and/or modify it 30 * under the terms and conditions of the GNU General Public License, 31 * version 2, as published by the Free Software Foundation. 32 * 33 * This program is distributed in the hope it will be useful, but WITHOUT 34 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 35 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 36 * more details. 37 * 38 * You should have received a copy of the GNU General Public License 39 * along with this program. If not, see <http://www.gnu.org/licenses/>. 40 */ 41 #include <linux/clk.h> 42 #include <linux/delay.h> 43 #include <linux/device.h> 44 #include <linux/dmaengine.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/err.h> 47 #include <linux/highmem.h> 48 #include <linux/interrupt.h> 49 #include <linux/io.h> 50 #include <linux/iopoll.h> 51 #include <linux/module.h> 52 #include <linux/of_address.h> 53 #include <linux/of_irq.h> 54 #include <linux/platform_device.h> 55 #include <linux/scatterlist.h> 56 #include <linux/time.h> 57 #include <linux/workqueue.h> 58 59 #include <linux/mmc/host.h> 60 #include <linux/mmc/mmc.h> 61 #include <linux/mmc/sd.h> 62 63 #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 64 #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 65 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 66 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 67 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 68 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 69 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 70 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 71 #define SDHSTS 0x20 /* SD host status - 11 R/W */ 72 #define SDVDD 0x30 /* SD card power control - 1 R/W */ 73 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 74 #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 75 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 76 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 77 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 78 79 #define SDCMD_NEW_FLAG 0x8000 80 #define SDCMD_FAIL_FLAG 0x4000 81 #define SDCMD_BUSYWAIT 0x800 82 #define SDCMD_NO_RESPONSE 0x400 83 #define SDCMD_LONG_RESPONSE 0x200 84 #define SDCMD_WRITE_CMD 0x80 85 #define SDCMD_READ_CMD 0x40 86 #define SDCMD_CMD_MASK 0x3f 87 88 #define SDCDIV_MAX_CDIV 0x7ff 89 90 #define SDHSTS_BUSY_IRPT 0x400 91 #define SDHSTS_BLOCK_IRPT 0x200 92 #define SDHSTS_SDIO_IRPT 0x100 93 #define SDHSTS_REW_TIME_OUT 0x80 94 #define SDHSTS_CMD_TIME_OUT 0x40 95 #define SDHSTS_CRC16_ERROR 0x20 96 #define SDHSTS_CRC7_ERROR 0x10 97 #define SDHSTS_FIFO_ERROR 0x08 98 /* Reserved */ 99 /* Reserved */ 100 #define SDHSTS_DATA_FLAG 0x01 101 102 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 103 SDHSTS_CRC16_ERROR | \ 104 SDHSTS_REW_TIME_OUT | \ 105 SDHSTS_FIFO_ERROR) 106 107 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 108 SDHSTS_TRANSFER_ERROR_MASK) 109 110 #define SDHCFG_BUSY_IRPT_EN BIT(10) 111 #define SDHCFG_BLOCK_IRPT_EN BIT(8) 112 #define SDHCFG_SDIO_IRPT_EN BIT(5) 113 #define SDHCFG_DATA_IRPT_EN BIT(4) 114 #define SDHCFG_SLOW_CARD BIT(3) 115 #define SDHCFG_WIDE_EXT_BUS BIT(2) 116 #define SDHCFG_WIDE_INT_BUS BIT(1) 117 #define SDHCFG_REL_CMD_LINE BIT(0) 118 119 #define SDVDD_POWER_OFF 0 120 #define SDVDD_POWER_ON 1 121 122 #define SDEDM_FORCE_DATA_MODE BIT(19) 123 #define SDEDM_CLOCK_PULSE BIT(20) 124 #define SDEDM_BYPASS BIT(21) 125 126 #define SDEDM_WRITE_THRESHOLD_SHIFT 9 127 #define SDEDM_READ_THRESHOLD_SHIFT 14 128 #define SDEDM_THRESHOLD_MASK 0x1f 129 130 #define SDEDM_FSM_MASK 0xf 131 #define SDEDM_FSM_IDENTMODE 0x0 132 #define SDEDM_FSM_DATAMODE 0x1 133 #define SDEDM_FSM_READDATA 0x2 134 #define SDEDM_FSM_WRITEDATA 0x3 135 #define SDEDM_FSM_READWAIT 0x4 136 #define SDEDM_FSM_READCRC 0x5 137 #define SDEDM_FSM_WRITECRC 0x6 138 #define SDEDM_FSM_WRITEWAIT1 0x7 139 #define SDEDM_FSM_POWERDOWN 0x8 140 #define SDEDM_FSM_POWERUP 0x9 141 #define SDEDM_FSM_WRITESTART1 0xa 142 #define SDEDM_FSM_WRITESTART2 0xb 143 #define SDEDM_FSM_GENPULSES 0xc 144 #define SDEDM_FSM_WRITEWAIT2 0xd 145 #define SDEDM_FSM_STARTPOWDOWN 0xf 146 147 #define SDDATA_FIFO_WORDS 16 148 149 #define FIFO_READ_THRESHOLD 4 150 #define FIFO_WRITE_THRESHOLD 4 151 #define SDDATA_FIFO_PIO_BURST 8 152 153 #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */ 154 155 struct bcm2835_host { 156 spinlock_t lock; 157 struct mutex mutex; 158 159 void __iomem *ioaddr; 160 u32 phys_addr; 161 162 struct mmc_host *mmc; 163 struct platform_device *pdev; 164 165 int clock; /* Current clock speed */ 166 unsigned int max_clk; /* Max possible freq */ 167 struct work_struct dma_work; 168 struct delayed_work timeout_work; /* Timer for timeouts */ 169 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 170 unsigned int blocks; /* remaining PIO blocks */ 171 int irq; /* Device IRQ */ 172 173 u32 ns_per_fifo_word; 174 175 /* cached registers */ 176 u32 hcfg; 177 u32 cdiv; 178 179 struct mmc_request *mrq; /* Current request */ 180 struct mmc_command *cmd; /* Current command */ 181 struct mmc_data *data; /* Current data request */ 182 bool data_complete:1;/* Data finished before cmd */ 183 bool use_busy:1; /* Wait for busy interrupt */ 184 bool use_sbc:1; /* Send CMD23 */ 185 186 /* for threaded irq handler */ 187 bool irq_block; 188 bool irq_busy; 189 bool irq_data; 190 191 /* DMA part */ 192 struct dma_chan *dma_chan_rxtx; 193 struct dma_chan *dma_chan; 194 struct dma_slave_config dma_cfg_rx; 195 struct dma_slave_config dma_cfg_tx; 196 struct dma_async_tx_descriptor *dma_desc; 197 u32 dma_dir; 198 u32 drain_words; 199 struct page *drain_page; 200 u32 drain_offset; 201 bool use_dma; 202 }; 203 204 static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd, 205 const char *label) 206 { 207 struct device *dev = &host->pdev->dev; 208 209 if (!cmd) 210 return; 211 212 dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", 213 (cmd == host->cmd) ? '>' : ' ', 214 label, cmd->opcode, cmd->arg, cmd->flags, 215 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], 216 cmd->error); 217 } 218 219 static void bcm2835_dumpregs(struct bcm2835_host *host) 220 { 221 struct mmc_request *mrq = host->mrq; 222 struct device *dev = &host->pdev->dev; 223 224 if (mrq) { 225 bcm2835_dumpcmd(host, mrq->sbc, "sbc"); 226 bcm2835_dumpcmd(host, mrq->cmd, "cmd"); 227 if (mrq->data) { 228 dev_dbg(dev, "data blocks %x blksz %x - err %d\n", 229 mrq->data->blocks, 230 mrq->data->blksz, 231 mrq->data->error); 232 } 233 bcm2835_dumpcmd(host, mrq->stop, "stop"); 234 } 235 236 dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 237 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 238 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 239 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 240 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 241 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 242 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 243 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 244 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 245 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 246 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 247 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 248 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 249 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 250 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 251 dev_dbg(dev, "===========================================\n"); 252 } 253 254 static void bcm2835_reset_internal(struct bcm2835_host *host) 255 { 256 u32 temp; 257 258 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 259 writel(0, host->ioaddr + SDCMD); 260 writel(0, host->ioaddr + SDARG); 261 writel(0xf00000, host->ioaddr + SDTOUT); 262 writel(0, host->ioaddr + SDCDIV); 263 writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */ 264 writel(0, host->ioaddr + SDHCFG); 265 writel(0, host->ioaddr + SDHBCT); 266 writel(0, host->ioaddr + SDHBLC); 267 268 /* Limit fifo usage due to silicon bug */ 269 temp = readl(host->ioaddr + SDEDM); 270 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 271 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 272 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 273 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 274 writel(temp, host->ioaddr + SDEDM); 275 msleep(20); 276 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 277 msleep(20); 278 host->clock = 0; 279 writel(host->hcfg, host->ioaddr + SDHCFG); 280 writel(host->cdiv, host->ioaddr + SDCDIV); 281 } 282 283 static void bcm2835_reset(struct mmc_host *mmc) 284 { 285 struct bcm2835_host *host = mmc_priv(mmc); 286 287 if (host->dma_chan) 288 dmaengine_terminate_sync(host->dma_chan); 289 bcm2835_reset_internal(host); 290 } 291 292 static void bcm2835_finish_command(struct bcm2835_host *host); 293 294 static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) 295 { 296 int timediff; 297 u32 alternate_idle; 298 299 alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ? 300 SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; 301 302 timediff = 0; 303 304 while (1) { 305 u32 edm, fsm; 306 307 edm = readl(host->ioaddr + SDEDM); 308 fsm = edm & SDEDM_FSM_MASK; 309 310 if ((fsm == SDEDM_FSM_IDENTMODE) || 311 (fsm == SDEDM_FSM_DATAMODE)) 312 break; 313 if (fsm == alternate_idle) { 314 writel(edm | SDEDM_FORCE_DATA_MODE, 315 host->ioaddr + SDEDM); 316 break; 317 } 318 319 timediff++; 320 if (timediff == 100000) { 321 dev_err(&host->pdev->dev, 322 "wait_transfer_complete - still waiting after %d retries\n", 323 timediff); 324 bcm2835_dumpregs(host); 325 host->mrq->data->error = -ETIMEDOUT; 326 return; 327 } 328 cpu_relax(); 329 } 330 } 331 332 static void bcm2835_dma_complete(void *param) 333 { 334 struct bcm2835_host *host = param; 335 336 schedule_work(&host->dma_work); 337 } 338 339 static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 340 { 341 unsigned long flags; 342 size_t blksize; 343 unsigned long wait_max; 344 345 blksize = host->data->blksz; 346 347 wait_max = jiffies + msecs_to_jiffies(500); 348 349 local_irq_save(flags); 350 351 while (blksize) { 352 int copy_words; 353 u32 hsts = 0; 354 size_t len; 355 u32 *buf; 356 357 if (!sg_miter_next(&host->sg_miter)) { 358 host->data->error = -EINVAL; 359 break; 360 } 361 362 len = min(host->sg_miter.length, blksize); 363 if (len % 4) { 364 host->data->error = -EINVAL; 365 break; 366 } 367 368 blksize -= len; 369 host->sg_miter.consumed = len; 370 371 buf = (u32 *)host->sg_miter.addr; 372 373 copy_words = len / 4; 374 375 while (copy_words) { 376 int burst_words, words; 377 u32 edm; 378 379 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 380 edm = readl(host->ioaddr + SDEDM); 381 if (is_read) 382 words = ((edm >> 4) & 0x1f); 383 else 384 words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f); 385 386 if (words < burst_words) { 387 int fsm_state = (edm & SDEDM_FSM_MASK); 388 struct device *dev = &host->pdev->dev; 389 390 if ((is_read && 391 (fsm_state != SDEDM_FSM_READDATA && 392 fsm_state != SDEDM_FSM_READWAIT && 393 fsm_state != SDEDM_FSM_READCRC)) || 394 (!is_read && 395 (fsm_state != SDEDM_FSM_WRITEDATA && 396 fsm_state != SDEDM_FSM_WRITESTART1 && 397 fsm_state != SDEDM_FSM_WRITESTART2))) { 398 hsts = readl(host->ioaddr + SDHSTS); 399 dev_err(dev, "fsm %x, hsts %08x\n", 400 fsm_state, hsts); 401 if (hsts & SDHSTS_ERROR_MASK) 402 break; 403 } 404 405 if (time_after(jiffies, wait_max)) { 406 dev_err(dev, "PIO %s timeout - EDM %08x\n", 407 is_read ? "read" : "write", 408 edm); 409 hsts = SDHSTS_REW_TIME_OUT; 410 break; 411 } 412 ndelay((burst_words - words) * 413 host->ns_per_fifo_word); 414 continue; 415 } else if (words > copy_words) { 416 words = copy_words; 417 } 418 419 copy_words -= words; 420 421 while (words) { 422 if (is_read) 423 *(buf++) = readl(host->ioaddr + SDDATA); 424 else 425 writel(*(buf++), host->ioaddr + SDDATA); 426 words--; 427 } 428 } 429 430 if (hsts & SDHSTS_ERROR_MASK) 431 break; 432 } 433 434 sg_miter_stop(&host->sg_miter); 435 436 local_irq_restore(flags); 437 } 438 439 static void bcm2835_transfer_pio(struct bcm2835_host *host) 440 { 441 struct device *dev = &host->pdev->dev; 442 u32 sdhsts; 443 bool is_read; 444 445 is_read = (host->data->flags & MMC_DATA_READ) != 0; 446 bcm2835_transfer_block_pio(host, is_read); 447 448 sdhsts = readl(host->ioaddr + SDHSTS); 449 if (sdhsts & (SDHSTS_CRC16_ERROR | 450 SDHSTS_CRC7_ERROR | 451 SDHSTS_FIFO_ERROR)) { 452 dev_err(dev, "%s transfer error - HSTS %08x\n", 453 is_read ? "read" : "write", sdhsts); 454 host->data->error = -EILSEQ; 455 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 456 SDHSTS_REW_TIME_OUT))) { 457 dev_err(dev, "%s timeout error - HSTS %08x\n", 458 is_read ? "read" : "write", sdhsts); 459 host->data->error = -ETIMEDOUT; 460 } 461 } 462 463 static 464 void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data) 465 { 466 int len, dir_data, dir_slave; 467 struct dma_async_tx_descriptor *desc = NULL; 468 struct dma_chan *dma_chan; 469 470 dma_chan = host->dma_chan_rxtx; 471 if (data->flags & MMC_DATA_READ) { 472 dir_data = DMA_FROM_DEVICE; 473 dir_slave = DMA_DEV_TO_MEM; 474 } else { 475 dir_data = DMA_TO_DEVICE; 476 dir_slave = DMA_MEM_TO_DEV; 477 } 478 479 /* The block doesn't manage the FIFO DREQs properly for 480 * multi-block transfers, so don't attempt to DMA the final 481 * few words. Unfortunately this requires the final sg entry 482 * to be trimmed. N.B. This code demands that the overspill 483 * is contained in a single sg entry. 484 */ 485 486 host->drain_words = 0; 487 if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) { 488 struct scatterlist *sg; 489 u32 len; 490 int i; 491 492 len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4, 493 (u32)data->blocks * data->blksz); 494 495 for_each_sg(data->sg, sg, data->sg_len, i) { 496 if (sg_is_last(sg)) { 497 WARN_ON(sg->length < len); 498 sg->length -= len; 499 host->drain_page = sg_page(sg); 500 host->drain_offset = sg->offset + sg->length; 501 } 502 } 503 host->drain_words = len / 4; 504 } 505 506 /* The parameters have already been validated, so this will not fail */ 507 (void)dmaengine_slave_config(dma_chan, 508 (dir_data == DMA_FROM_DEVICE) ? 509 &host->dma_cfg_rx : 510 &host->dma_cfg_tx); 511 512 len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len, 513 dir_data); 514 515 if (len > 0) { 516 desc = dmaengine_prep_slave_sg(dma_chan, data->sg, 517 len, dir_slave, 518 DMA_PREP_INTERRUPT | 519 DMA_CTRL_ACK); 520 } 521 522 if (desc) { 523 desc->callback = bcm2835_dma_complete; 524 desc->callback_param = host; 525 host->dma_desc = desc; 526 host->dma_chan = dma_chan; 527 host->dma_dir = dir_data; 528 } 529 } 530 531 static void bcm2835_start_dma(struct bcm2835_host *host) 532 { 533 dmaengine_submit(host->dma_desc); 534 dma_async_issue_pending(host->dma_chan); 535 } 536 537 static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) 538 { 539 u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | 540 SDHCFG_BUSY_IRPT_EN; 541 542 if (host->dma_desc) { 543 host->hcfg = (host->hcfg & ~all_irqs) | 544 SDHCFG_BUSY_IRPT_EN; 545 } else { 546 host->hcfg = (host->hcfg & ~all_irqs) | 547 SDHCFG_DATA_IRPT_EN | 548 SDHCFG_BUSY_IRPT_EN; 549 } 550 551 writel(host->hcfg, host->ioaddr + SDHCFG); 552 } 553 554 static 555 void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) 556 { 557 struct mmc_data *data = cmd->data; 558 559 WARN_ON(host->data); 560 561 host->data = data; 562 if (!data) 563 return; 564 565 host->data_complete = false; 566 host->data->bytes_xfered = 0; 567 568 if (!host->dma_desc) { 569 /* Use PIO */ 570 int flags = SG_MITER_ATOMIC; 571 572 if (data->flags & MMC_DATA_READ) 573 flags |= SG_MITER_TO_SG; 574 else 575 flags |= SG_MITER_FROM_SG; 576 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 577 host->blocks = data->blocks; 578 } 579 580 bcm2835_set_transfer_irqs(host); 581 582 writel(data->blksz, host->ioaddr + SDHBCT); 583 writel(data->blocks, host->ioaddr + SDHBLC); 584 } 585 586 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms) 587 { 588 struct device *dev = &host->pdev->dev; 589 u32 value; 590 int ret; 591 592 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 593 !(value & SDCMD_NEW_FLAG), 1, 10); 594 if (ret == -ETIMEDOUT) 595 /* if it takes a while make poll interval bigger */ 596 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 597 !(value & SDCMD_NEW_FLAG), 598 10, max_ms * 1000); 599 if (ret == -ETIMEDOUT) 600 dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms); 601 602 return value; 603 } 604 605 static void bcm2835_finish_request(struct bcm2835_host *host) 606 { 607 struct dma_chan *terminate_chan = NULL; 608 struct mmc_request *mrq; 609 610 cancel_delayed_work(&host->timeout_work); 611 612 mrq = host->mrq; 613 614 host->mrq = NULL; 615 host->cmd = NULL; 616 host->data = NULL; 617 618 host->dma_desc = NULL; 619 terminate_chan = host->dma_chan; 620 host->dma_chan = NULL; 621 622 if (terminate_chan) { 623 int err = dmaengine_terminate_all(terminate_chan); 624 625 if (err) 626 dev_err(&host->pdev->dev, 627 "failed to terminate DMA (%d)\n", err); 628 } 629 630 mmc_request_done(host->mmc, mrq); 631 } 632 633 static 634 bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd) 635 { 636 struct device *dev = &host->pdev->dev; 637 u32 sdcmd, sdhsts; 638 unsigned long timeout; 639 640 WARN_ON(host->cmd); 641 642 sdcmd = bcm2835_read_wait_sdcmd(host, 100); 643 if (sdcmd & SDCMD_NEW_FLAG) { 644 dev_err(dev, "previous command never completed.\n"); 645 bcm2835_dumpregs(host); 646 cmd->error = -EILSEQ; 647 bcm2835_finish_request(host); 648 return false; 649 } 650 651 if (!cmd->data && cmd->busy_timeout > 9000) 652 timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 653 else 654 timeout = 10 * HZ; 655 schedule_delayed_work(&host->timeout_work, timeout); 656 657 host->cmd = cmd; 658 659 /* Clear any error flags */ 660 sdhsts = readl(host->ioaddr + SDHSTS); 661 if (sdhsts & SDHSTS_ERROR_MASK) 662 writel(sdhsts, host->ioaddr + SDHSTS); 663 664 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 665 dev_err(dev, "unsupported response type!\n"); 666 cmd->error = -EINVAL; 667 bcm2835_finish_request(host); 668 return false; 669 } 670 671 bcm2835_prepare_data(host, cmd); 672 673 writel(cmd->arg, host->ioaddr + SDARG); 674 675 sdcmd = cmd->opcode & SDCMD_CMD_MASK; 676 677 host->use_busy = false; 678 if (!(cmd->flags & MMC_RSP_PRESENT)) { 679 sdcmd |= SDCMD_NO_RESPONSE; 680 } else { 681 if (cmd->flags & MMC_RSP_136) 682 sdcmd |= SDCMD_LONG_RESPONSE; 683 if (cmd->flags & MMC_RSP_BUSY) { 684 sdcmd |= SDCMD_BUSYWAIT; 685 host->use_busy = true; 686 } 687 } 688 689 if (cmd->data) { 690 if (cmd->data->flags & MMC_DATA_WRITE) 691 sdcmd |= SDCMD_WRITE_CMD; 692 if (cmd->data->flags & MMC_DATA_READ) 693 sdcmd |= SDCMD_READ_CMD; 694 } 695 696 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 697 698 return true; 699 } 700 701 static void bcm2835_transfer_complete(struct bcm2835_host *host) 702 { 703 struct mmc_data *data; 704 705 WARN_ON(!host->data_complete); 706 707 data = host->data; 708 host->data = NULL; 709 710 /* Need to send CMD12 if - 711 * a) open-ended multiblock transfer (no CMD23) 712 * b) error in multiblock transfer 713 */ 714 if (host->mrq->stop && (data->error || !host->use_sbc)) { 715 if (bcm2835_send_command(host, host->mrq->stop)) { 716 /* No busy, so poll for completion */ 717 if (!host->use_busy) 718 bcm2835_finish_command(host); 719 } 720 } else { 721 bcm2835_wait_transfer_complete(host); 722 bcm2835_finish_request(host); 723 } 724 } 725 726 static void bcm2835_finish_data(struct bcm2835_host *host) 727 { 728 struct device *dev = &host->pdev->dev; 729 struct mmc_data *data; 730 731 data = host->data; 732 733 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 734 writel(host->hcfg, host->ioaddr + SDHCFG); 735 736 data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks); 737 738 host->data_complete = true; 739 740 if (host->cmd) { 741 /* Data managed to finish before the 742 * command completed. Make sure we do 743 * things in the proper order. 744 */ 745 dev_dbg(dev, "Finished early - HSTS %08x\n", 746 readl(host->ioaddr + SDHSTS)); 747 } else { 748 bcm2835_transfer_complete(host); 749 } 750 } 751 752 static void bcm2835_finish_command(struct bcm2835_host *host) 753 { 754 struct device *dev = &host->pdev->dev; 755 struct mmc_command *cmd = host->cmd; 756 u32 sdcmd; 757 758 sdcmd = bcm2835_read_wait_sdcmd(host, 100); 759 760 /* Check for errors */ 761 if (sdcmd & SDCMD_NEW_FLAG) { 762 dev_err(dev, "command never completed.\n"); 763 bcm2835_dumpregs(host); 764 host->cmd->error = -EIO; 765 bcm2835_finish_request(host); 766 return; 767 } else if (sdcmd & SDCMD_FAIL_FLAG) { 768 u32 sdhsts = readl(host->ioaddr + SDHSTS); 769 770 /* Clear the errors */ 771 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 772 773 if (!(sdhsts & SDHSTS_CRC7_ERROR) || 774 (host->cmd->opcode != MMC_SEND_OP_COND)) { 775 if (sdhsts & SDHSTS_CMD_TIME_OUT) { 776 host->cmd->error = -ETIMEDOUT; 777 } else { 778 dev_err(dev, "unexpected command %d error\n", 779 host->cmd->opcode); 780 bcm2835_dumpregs(host); 781 host->cmd->error = -EILSEQ; 782 } 783 bcm2835_finish_request(host); 784 return; 785 } 786 } 787 788 if (cmd->flags & MMC_RSP_PRESENT) { 789 if (cmd->flags & MMC_RSP_136) { 790 int i; 791 792 for (i = 0; i < 4; i++) { 793 cmd->resp[3 - i] = 794 readl(host->ioaddr + SDRSP0 + i * 4); 795 } 796 } else { 797 cmd->resp[0] = readl(host->ioaddr + SDRSP0); 798 } 799 } 800 801 if (cmd == host->mrq->sbc) { 802 /* Finished CMD23, now send actual command. */ 803 host->cmd = NULL; 804 if (bcm2835_send_command(host, host->mrq->cmd)) { 805 if (host->data && host->dma_desc) 806 /* DMA transfer starts now, PIO starts 807 * after irq 808 */ 809 bcm2835_start_dma(host); 810 811 if (!host->use_busy) 812 bcm2835_finish_command(host); 813 } 814 } else if (cmd == host->mrq->stop) { 815 /* Finished CMD12 */ 816 bcm2835_finish_request(host); 817 } else { 818 /* Processed actual command. */ 819 host->cmd = NULL; 820 if (!host->data) 821 bcm2835_finish_request(host); 822 else if (host->data_complete) 823 bcm2835_transfer_complete(host); 824 } 825 } 826 827 static void bcm2835_timeout(struct work_struct *work) 828 { 829 struct delayed_work *d = to_delayed_work(work); 830 struct bcm2835_host *host = 831 container_of(d, struct bcm2835_host, timeout_work); 832 struct device *dev = &host->pdev->dev; 833 834 mutex_lock(&host->mutex); 835 836 if (host->mrq) { 837 dev_err(dev, "timeout waiting for hardware interrupt.\n"); 838 bcm2835_dumpregs(host); 839 840 if (host->data) { 841 host->data->error = -ETIMEDOUT; 842 bcm2835_finish_data(host); 843 } else { 844 if (host->cmd) 845 host->cmd->error = -ETIMEDOUT; 846 else 847 host->mrq->cmd->error = -ETIMEDOUT; 848 849 bcm2835_finish_request(host); 850 } 851 } 852 853 mutex_unlock(&host->mutex); 854 } 855 856 static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 857 { 858 struct device *dev = &host->pdev->dev; 859 860 if (!(intmask & SDHSTS_ERROR_MASK)) 861 return false; 862 863 if (!host->cmd) 864 return true; 865 866 dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask); 867 if (intmask & SDHSTS_CRC7_ERROR) { 868 host->cmd->error = -EILSEQ; 869 } else if (intmask & (SDHSTS_CRC16_ERROR | 870 SDHSTS_FIFO_ERROR)) { 871 if (host->mrq->data) 872 host->mrq->data->error = -EILSEQ; 873 else 874 host->cmd->error = -EILSEQ; 875 } else if (intmask & SDHSTS_REW_TIME_OUT) { 876 if (host->mrq->data) 877 host->mrq->data->error = -ETIMEDOUT; 878 else 879 host->cmd->error = -ETIMEDOUT; 880 } else if (intmask & SDHSTS_CMD_TIME_OUT) { 881 host->cmd->error = -ETIMEDOUT; 882 } 883 bcm2835_dumpregs(host); 884 return true; 885 } 886 887 static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 888 { 889 if (!host->data) 890 return; 891 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 892 host->data->error = -EILSEQ; 893 if (intmask & SDHSTS_REW_TIME_OUT) 894 host->data->error = -ETIMEDOUT; 895 } 896 897 static void bcm2835_busy_irq(struct bcm2835_host *host) 898 { 899 if (WARN_ON(!host->cmd)) { 900 bcm2835_dumpregs(host); 901 return; 902 } 903 904 if (WARN_ON(!host->use_busy)) { 905 bcm2835_dumpregs(host); 906 return; 907 } 908 host->use_busy = false; 909 910 bcm2835_finish_command(host); 911 } 912 913 static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) 914 { 915 /* There are no dedicated data/space available interrupt 916 * status bits, so it is necessary to use the single shared 917 * data/space available FIFO status bits. It is therefore not 918 * an error to get here when there is no data transfer in 919 * progress. 920 */ 921 if (!host->data) 922 return; 923 924 bcm2835_check_data_error(host, intmask); 925 if (host->data->error) 926 goto finished; 927 928 if (host->data->flags & MMC_DATA_WRITE) { 929 /* Use the block interrupt for writes after the first block */ 930 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); 931 host->hcfg |= SDHCFG_BLOCK_IRPT_EN; 932 writel(host->hcfg, host->ioaddr + SDHCFG); 933 bcm2835_transfer_pio(host); 934 } else { 935 bcm2835_transfer_pio(host); 936 host->blocks--; 937 if ((host->blocks == 0) || host->data->error) 938 goto finished; 939 } 940 return; 941 942 finished: 943 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 944 writel(host->hcfg, host->ioaddr + SDHCFG); 945 } 946 947 static void bcm2835_data_threaded_irq(struct bcm2835_host *host) 948 { 949 if (!host->data) 950 return; 951 if ((host->blocks == 0) || host->data->error) 952 bcm2835_finish_data(host); 953 } 954 955 static void bcm2835_block_irq(struct bcm2835_host *host) 956 { 957 if (WARN_ON(!host->data)) { 958 bcm2835_dumpregs(host); 959 return; 960 } 961 962 if (!host->dma_desc) { 963 WARN_ON(!host->blocks); 964 if (host->data->error || (--host->blocks == 0)) 965 bcm2835_finish_data(host); 966 else 967 bcm2835_transfer_pio(host); 968 } else if (host->data->flags & MMC_DATA_WRITE) { 969 bcm2835_finish_data(host); 970 } 971 } 972 973 static irqreturn_t bcm2835_irq(int irq, void *dev_id) 974 { 975 irqreturn_t result = IRQ_NONE; 976 struct bcm2835_host *host = dev_id; 977 u32 intmask; 978 979 spin_lock(&host->lock); 980 981 intmask = readl(host->ioaddr + SDHSTS); 982 983 writel(SDHSTS_BUSY_IRPT | 984 SDHSTS_BLOCK_IRPT | 985 SDHSTS_SDIO_IRPT | 986 SDHSTS_DATA_FLAG, 987 host->ioaddr + SDHSTS); 988 989 if (intmask & SDHSTS_BLOCK_IRPT) { 990 bcm2835_check_data_error(host, intmask); 991 host->irq_block = true; 992 result = IRQ_WAKE_THREAD; 993 } 994 995 if (intmask & SDHSTS_BUSY_IRPT) { 996 if (!bcm2835_check_cmd_error(host, intmask)) { 997 host->irq_busy = true; 998 result = IRQ_WAKE_THREAD; 999 } else { 1000 result = IRQ_HANDLED; 1001 } 1002 } 1003 1004 /* There is no true data interrupt status bit, so it is 1005 * necessary to qualify the data flag with the interrupt 1006 * enable bit. 1007 */ 1008 if ((intmask & SDHSTS_DATA_FLAG) && 1009 (host->hcfg & SDHCFG_DATA_IRPT_EN)) { 1010 bcm2835_data_irq(host, intmask); 1011 host->irq_data = true; 1012 result = IRQ_WAKE_THREAD; 1013 } 1014 1015 spin_unlock(&host->lock); 1016 1017 return result; 1018 } 1019 1020 static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) 1021 { 1022 struct bcm2835_host *host = dev_id; 1023 unsigned long flags; 1024 bool block, busy, data; 1025 1026 spin_lock_irqsave(&host->lock, flags); 1027 1028 block = host->irq_block; 1029 busy = host->irq_busy; 1030 data = host->irq_data; 1031 host->irq_block = false; 1032 host->irq_busy = false; 1033 host->irq_data = false; 1034 1035 spin_unlock_irqrestore(&host->lock, flags); 1036 1037 mutex_lock(&host->mutex); 1038 1039 if (block) 1040 bcm2835_block_irq(host); 1041 if (busy) 1042 bcm2835_busy_irq(host); 1043 if (data) 1044 bcm2835_data_threaded_irq(host); 1045 1046 mutex_unlock(&host->mutex); 1047 1048 return IRQ_HANDLED; 1049 } 1050 1051 static void bcm2835_dma_complete_work(struct work_struct *work) 1052 { 1053 struct bcm2835_host *host = 1054 container_of(work, struct bcm2835_host, dma_work); 1055 struct mmc_data *data = host->data; 1056 1057 mutex_lock(&host->mutex); 1058 1059 if (host->dma_chan) { 1060 dma_unmap_sg(host->dma_chan->device->dev, 1061 data->sg, data->sg_len, 1062 host->dma_dir); 1063 1064 host->dma_chan = NULL; 1065 } 1066 1067 if (host->drain_words) { 1068 unsigned long flags; 1069 void *page; 1070 u32 *buf; 1071 1072 if (host->drain_offset & PAGE_MASK) { 1073 host->drain_page += host->drain_offset >> PAGE_SHIFT; 1074 host->drain_offset &= ~PAGE_MASK; 1075 } 1076 local_irq_save(flags); 1077 page = kmap_atomic(host->drain_page); 1078 buf = page + host->drain_offset; 1079 1080 while (host->drain_words) { 1081 u32 edm = readl(host->ioaddr + SDEDM); 1082 1083 if ((edm >> 4) & 0x1f) 1084 *(buf++) = readl(host->ioaddr + SDDATA); 1085 host->drain_words--; 1086 } 1087 1088 kunmap_atomic(page); 1089 local_irq_restore(flags); 1090 } 1091 1092 bcm2835_finish_data(host); 1093 1094 mutex_unlock(&host->mutex); 1095 } 1096 1097 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 1098 { 1099 int div; 1100 1101 /* The SDCDIV register has 11 bits, and holds (div - 2). But 1102 * in data mode the max is 50MHz wihout a minimum, and only 1103 * the bottom 3 bits are used. Since the switch over is 1104 * automatic (unless we have marked the card as slow...), 1105 * chosen values have to make sense in both modes. Ident mode 1106 * must be 100-400KHz, so can range check the requested 1107 * clock. CMD15 must be used to return to data mode, so this 1108 * can be monitored. 1109 * 1110 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 1111 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 1112 * 1113 * 623->400KHz/27.8MHz 1114 * reset value (507)->491159/50MHz 1115 * 1116 * BUT, the 3-bit clock divisor in data mode is too small if 1117 * the core clock is higher than 250MHz, so instead use the 1118 * SLOW_CARD configuration bit to force the use of the ident 1119 * clock divisor at all times. 1120 */ 1121 1122 if (clock < 100000) { 1123 /* Can't stop the clock, but make it as slow as possible 1124 * to show willing 1125 */ 1126 host->cdiv = SDCDIV_MAX_CDIV; 1127 writel(host->cdiv, host->ioaddr + SDCDIV); 1128 return; 1129 } 1130 1131 div = host->max_clk / clock; 1132 if (div < 2) 1133 div = 2; 1134 if ((host->max_clk / div) > clock) 1135 div++; 1136 div -= 2; 1137 1138 if (div > SDCDIV_MAX_CDIV) 1139 div = SDCDIV_MAX_CDIV; 1140 1141 clock = host->max_clk / (div + 2); 1142 host->mmc->actual_clock = clock; 1143 1144 /* Calibrate some delays */ 1145 1146 host->ns_per_fifo_word = (1000000000 / clock) * 1147 ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32); 1148 1149 host->cdiv = div; 1150 writel(host->cdiv, host->ioaddr + SDCDIV); 1151 1152 /* Set the timeout to 500ms */ 1153 writel(host->mmc->actual_clock / 2, host->ioaddr + SDTOUT); 1154 } 1155 1156 static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq) 1157 { 1158 struct bcm2835_host *host = mmc_priv(mmc); 1159 struct device *dev = &host->pdev->dev; 1160 u32 edm, fsm; 1161 1162 /* Reset the error statuses in case this is a retry */ 1163 if (mrq->sbc) 1164 mrq->sbc->error = 0; 1165 if (mrq->cmd) 1166 mrq->cmd->error = 0; 1167 if (mrq->data) 1168 mrq->data->error = 0; 1169 if (mrq->stop) 1170 mrq->stop->error = 0; 1171 1172 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 1173 dev_err(dev, "unsupported block size (%d bytes)\n", 1174 mrq->data->blksz); 1175 1176 if (mrq->cmd) 1177 mrq->cmd->error = -EINVAL; 1178 1179 mmc_request_done(mmc, mrq); 1180 return; 1181 } 1182 1183 if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD)) 1184 bcm2835_prepare_dma(host, mrq->data); 1185 1186 mutex_lock(&host->mutex); 1187 1188 WARN_ON(host->mrq); 1189 host->mrq = mrq; 1190 1191 edm = readl(host->ioaddr + SDEDM); 1192 fsm = edm & SDEDM_FSM_MASK; 1193 1194 if ((fsm != SDEDM_FSM_IDENTMODE) && 1195 (fsm != SDEDM_FSM_DATAMODE)) { 1196 dev_err(dev, "previous command (%d) not complete (EDM %08x)\n", 1197 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, 1198 edm); 1199 bcm2835_dumpregs(host); 1200 1201 if (mrq->cmd) 1202 mrq->cmd->error = -EILSEQ; 1203 1204 bcm2835_finish_request(host); 1205 mutex_unlock(&host->mutex); 1206 return; 1207 } 1208 1209 host->use_sbc = !!mrq->sbc && host->mrq->data && 1210 (host->mrq->data->flags & MMC_DATA_READ); 1211 if (host->use_sbc) { 1212 if (bcm2835_send_command(host, mrq->sbc)) { 1213 if (!host->use_busy) 1214 bcm2835_finish_command(host); 1215 } 1216 } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) { 1217 if (host->data && host->dma_desc) { 1218 /* DMA transfer starts now, PIO starts after irq */ 1219 bcm2835_start_dma(host); 1220 } 1221 1222 if (!host->use_busy) 1223 bcm2835_finish_command(host); 1224 } 1225 1226 mutex_unlock(&host->mutex); 1227 } 1228 1229 static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1230 { 1231 struct bcm2835_host *host = mmc_priv(mmc); 1232 1233 mutex_lock(&host->mutex); 1234 1235 if (!ios->clock || ios->clock != host->clock) { 1236 bcm2835_set_clock(host, ios->clock); 1237 host->clock = ios->clock; 1238 } 1239 1240 /* set bus width */ 1241 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 1242 if (ios->bus_width == MMC_BUS_WIDTH_4) 1243 host->hcfg |= SDHCFG_WIDE_EXT_BUS; 1244 1245 host->hcfg |= SDHCFG_WIDE_INT_BUS; 1246 1247 /* Disable clever clock switching, to cope with fast core clocks */ 1248 host->hcfg |= SDHCFG_SLOW_CARD; 1249 1250 writel(host->hcfg, host->ioaddr + SDHCFG); 1251 1252 mutex_unlock(&host->mutex); 1253 } 1254 1255 static const struct mmc_host_ops bcm2835_ops = { 1256 .request = bcm2835_request, 1257 .set_ios = bcm2835_set_ios, 1258 .hw_reset = bcm2835_reset, 1259 }; 1260 1261 static int bcm2835_add_host(struct bcm2835_host *host) 1262 { 1263 struct mmc_host *mmc = host->mmc; 1264 struct device *dev = &host->pdev->dev; 1265 char pio_limit_string[20]; 1266 int ret; 1267 1268 mmc->f_max = host->max_clk; 1269 mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; 1270 1271 mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000); 1272 1273 dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n", 1274 mmc->f_max, mmc->f_min, mmc->max_busy_timeout); 1275 1276 /* host controller capabilities */ 1277 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 1278 MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE | 1279 MMC_CAP_CMD23; 1280 1281 spin_lock_init(&host->lock); 1282 mutex_init(&host->mutex); 1283 1284 if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) { 1285 dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n"); 1286 host->use_dma = false; 1287 } else { 1288 host->use_dma = true; 1289 1290 host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1291 host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1292 host->dma_cfg_tx.slave_id = 13; /* DREQ channel */ 1293 host->dma_cfg_tx.direction = DMA_MEM_TO_DEV; 1294 host->dma_cfg_tx.src_addr = 0; 1295 host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA; 1296 1297 host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1298 host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1299 host->dma_cfg_rx.slave_id = 13; /* DREQ channel */ 1300 host->dma_cfg_rx.direction = DMA_DEV_TO_MEM; 1301 host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA; 1302 host->dma_cfg_rx.dst_addr = 0; 1303 1304 if (dmaengine_slave_config(host->dma_chan_rxtx, 1305 &host->dma_cfg_tx) != 0 || 1306 dmaengine_slave_config(host->dma_chan_rxtx, 1307 &host->dma_cfg_rx) != 0) 1308 host->use_dma = false; 1309 } 1310 1311 mmc->max_segs = 128; 1312 mmc->max_req_size = 524288; 1313 mmc->max_seg_size = mmc->max_req_size; 1314 mmc->max_blk_size = 1024; 1315 mmc->max_blk_count = 65535; 1316 1317 /* report supported voltage ranges */ 1318 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1319 1320 INIT_WORK(&host->dma_work, bcm2835_dma_complete_work); 1321 INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout); 1322 1323 /* Set interrupt enables */ 1324 host->hcfg = SDHCFG_BUSY_IRPT_EN; 1325 1326 bcm2835_reset_internal(host); 1327 1328 ret = request_threaded_irq(host->irq, bcm2835_irq, 1329 bcm2835_threaded_irq, 1330 0, mmc_hostname(mmc), host); 1331 if (ret) { 1332 dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret); 1333 return ret; 1334 } 1335 1336 ret = mmc_add_host(mmc); 1337 if (ret) { 1338 free_irq(host->irq, host); 1339 return ret; 1340 } 1341 1342 pio_limit_string[0] = '\0'; 1343 if (host->use_dma && (PIO_THRESHOLD > 0)) 1344 sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD); 1345 dev_info(dev, "loaded - DMA %s%s\n", 1346 host->use_dma ? "enabled" : "disabled", pio_limit_string); 1347 1348 return 0; 1349 } 1350 1351 static int bcm2835_probe(struct platform_device *pdev) 1352 { 1353 struct device *dev = &pdev->dev; 1354 struct clk *clk; 1355 struct resource *iomem; 1356 struct bcm2835_host *host; 1357 struct mmc_host *mmc; 1358 const __be32 *regaddr_p; 1359 int ret; 1360 1361 dev_dbg(dev, "%s\n", __func__); 1362 mmc = mmc_alloc_host(sizeof(*host), dev); 1363 if (!mmc) 1364 return -ENOMEM; 1365 1366 mmc->ops = &bcm2835_ops; 1367 host = mmc_priv(mmc); 1368 host->mmc = mmc; 1369 host->pdev = pdev; 1370 spin_lock_init(&host->lock); 1371 1372 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1373 host->ioaddr = devm_ioremap_resource(dev, iomem); 1374 if (IS_ERR(host->ioaddr)) { 1375 ret = PTR_ERR(host->ioaddr); 1376 goto err; 1377 } 1378 1379 /* Parse OF address directly to get the physical address for 1380 * DMA to our registers. 1381 */ 1382 regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL); 1383 if (!regaddr_p) { 1384 dev_err(dev, "Can't get phys address\n"); 1385 ret = -EINVAL; 1386 goto err; 1387 } 1388 1389 host->phys_addr = be32_to_cpup(regaddr_p); 1390 1391 host->dma_chan = NULL; 1392 host->dma_desc = NULL; 1393 1394 host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx"); 1395 1396 clk = devm_clk_get(dev, NULL); 1397 if (IS_ERR(clk)) { 1398 ret = PTR_ERR(clk); 1399 if (ret != -EPROBE_DEFER) 1400 dev_err(dev, "could not get clk: %d\n", ret); 1401 goto err; 1402 } 1403 1404 host->max_clk = clk_get_rate(clk); 1405 1406 host->irq = platform_get_irq(pdev, 0); 1407 if (host->irq <= 0) { 1408 dev_err(dev, "get IRQ failed\n"); 1409 ret = -EINVAL; 1410 goto err; 1411 } 1412 1413 ret = mmc_of_parse(mmc); 1414 if (ret) 1415 goto err; 1416 1417 ret = bcm2835_add_host(host); 1418 if (ret) 1419 goto err; 1420 1421 platform_set_drvdata(pdev, host); 1422 1423 dev_dbg(dev, "%s -> OK\n", __func__); 1424 1425 return 0; 1426 1427 err: 1428 dev_dbg(dev, "%s -> err %d\n", __func__, ret); 1429 mmc_free_host(mmc); 1430 1431 return ret; 1432 } 1433 1434 static int bcm2835_remove(struct platform_device *pdev) 1435 { 1436 struct bcm2835_host *host = platform_get_drvdata(pdev); 1437 1438 mmc_remove_host(host->mmc); 1439 1440 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 1441 1442 free_irq(host->irq, host); 1443 1444 cancel_work_sync(&host->dma_work); 1445 cancel_delayed_work_sync(&host->timeout_work); 1446 1447 mmc_free_host(host->mmc); 1448 platform_set_drvdata(pdev, NULL); 1449 1450 return 0; 1451 } 1452 1453 static const struct of_device_id bcm2835_match[] = { 1454 { .compatible = "brcm,bcm2835-sdhost" }, 1455 { } 1456 }; 1457 MODULE_DEVICE_TABLE(of, bcm2835_match); 1458 1459 static struct platform_driver bcm2835_driver = { 1460 .probe = bcm2835_probe, 1461 .remove = bcm2835_remove, 1462 .driver = { 1463 .name = "sdhost-bcm2835", 1464 .of_match_table = bcm2835_match, 1465 }, 1466 }; 1467 module_platform_driver(bcm2835_driver); 1468 1469 MODULE_ALIAS("platform:sdhost-bcm2835"); 1470 MODULE_DESCRIPTION("BCM2835 SDHost driver"); 1471 MODULE_LICENSE("GPL v2"); 1472 MODULE_AUTHOR("Phil Elwell"); 1473