1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * bcm2835 sdhost driver. 4 * 5 * The 2835 has two SD controllers: The Arasan sdhci controller 6 * (supported by the iproc driver) and a custom sdhost controller 7 * (supported by this driver). 8 * 9 * The sdhci controller supports both sdcard and sdio. The sdhost 10 * controller supports the sdcard only, but has better performance. 11 * Also note that the rpi3 has sdio wifi, so driving the sdcard with 12 * the sdhost controller allows to use the sdhci controller for wifi 13 * support. 14 * 15 * The configuration is done by devicetree via pin muxing. Both 16 * SD controller are available on the same pins (2 pin groups = pin 22 17 * to 27 + pin 48 to 53). So it's possible to use both SD controllers 18 * at the same time with different pin groups. 19 * 20 * Author: Phil Elwell <phil@raspberrypi.org> 21 * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd. 22 * 23 * Based on 24 * mmc-bcm2835.c by Gellert Weisz 25 * which is, in turn, based on 26 * sdhci-bcm2708.c by Broadcom 27 * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko 28 * sdhci.c and sdhci-pci.c by Pierre Ossman 29 */ 30 #include <linux/clk.h> 31 #include <linux/delay.h> 32 #include <linux/device.h> 33 #include <linux/dmaengine.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/err.h> 36 #include <linux/highmem.h> 37 #include <linux/interrupt.h> 38 #include <linux/io.h> 39 #include <linux/iopoll.h> 40 #include <linux/module.h> 41 #include <linux/of_address.h> 42 #include <linux/of_irq.h> 43 #include <linux/platform_device.h> 44 #include <linux/scatterlist.h> 45 #include <linux/time.h> 46 #include <linux/workqueue.h> 47 48 #include <linux/mmc/host.h> 49 #include <linux/mmc/mmc.h> 50 #include <linux/mmc/sd.h> 51 52 #define SDCMD 0x00 /* Command to SD card - 16 R/W */ 53 #define SDARG 0x04 /* Argument to SD card - 32 R/W */ 54 #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ 55 #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ 56 #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */ 57 #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */ 58 #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */ 59 #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */ 60 #define SDHSTS 0x20 /* SD host status - 11 R/W */ 61 #define SDVDD 0x30 /* SD card power control - 1 R/W */ 62 #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ 63 #define SDHCFG 0x38 /* Host configuration - 2 R/W */ 64 #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ 65 #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ 66 #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ 67 68 #define SDCMD_NEW_FLAG 0x8000 69 #define SDCMD_FAIL_FLAG 0x4000 70 #define SDCMD_BUSYWAIT 0x800 71 #define SDCMD_NO_RESPONSE 0x400 72 #define SDCMD_LONG_RESPONSE 0x200 73 #define SDCMD_WRITE_CMD 0x80 74 #define SDCMD_READ_CMD 0x40 75 #define SDCMD_CMD_MASK 0x3f 76 77 #define SDCDIV_MAX_CDIV 0x7ff 78 79 #define SDHSTS_BUSY_IRPT 0x400 80 #define SDHSTS_BLOCK_IRPT 0x200 81 #define SDHSTS_SDIO_IRPT 0x100 82 #define SDHSTS_REW_TIME_OUT 0x80 83 #define SDHSTS_CMD_TIME_OUT 0x40 84 #define SDHSTS_CRC16_ERROR 0x20 85 #define SDHSTS_CRC7_ERROR 0x10 86 #define SDHSTS_FIFO_ERROR 0x08 87 /* Reserved */ 88 /* Reserved */ 89 #define SDHSTS_DATA_FLAG 0x01 90 91 #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \ 92 SDHSTS_CRC16_ERROR | \ 93 SDHSTS_REW_TIME_OUT | \ 94 SDHSTS_FIFO_ERROR) 95 96 #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \ 97 SDHSTS_TRANSFER_ERROR_MASK) 98 99 #define SDHCFG_BUSY_IRPT_EN BIT(10) 100 #define SDHCFG_BLOCK_IRPT_EN BIT(8) 101 #define SDHCFG_SDIO_IRPT_EN BIT(5) 102 #define SDHCFG_DATA_IRPT_EN BIT(4) 103 #define SDHCFG_SLOW_CARD BIT(3) 104 #define SDHCFG_WIDE_EXT_BUS BIT(2) 105 #define SDHCFG_WIDE_INT_BUS BIT(1) 106 #define SDHCFG_REL_CMD_LINE BIT(0) 107 108 #define SDVDD_POWER_OFF 0 109 #define SDVDD_POWER_ON 1 110 111 #define SDEDM_FORCE_DATA_MODE BIT(19) 112 #define SDEDM_CLOCK_PULSE BIT(20) 113 #define SDEDM_BYPASS BIT(21) 114 115 #define SDEDM_WRITE_THRESHOLD_SHIFT 9 116 #define SDEDM_READ_THRESHOLD_SHIFT 14 117 #define SDEDM_THRESHOLD_MASK 0x1f 118 119 #define SDEDM_FSM_MASK 0xf 120 #define SDEDM_FSM_IDENTMODE 0x0 121 #define SDEDM_FSM_DATAMODE 0x1 122 #define SDEDM_FSM_READDATA 0x2 123 #define SDEDM_FSM_WRITEDATA 0x3 124 #define SDEDM_FSM_READWAIT 0x4 125 #define SDEDM_FSM_READCRC 0x5 126 #define SDEDM_FSM_WRITECRC 0x6 127 #define SDEDM_FSM_WRITEWAIT1 0x7 128 #define SDEDM_FSM_POWERDOWN 0x8 129 #define SDEDM_FSM_POWERUP 0x9 130 #define SDEDM_FSM_WRITESTART1 0xa 131 #define SDEDM_FSM_WRITESTART2 0xb 132 #define SDEDM_FSM_GENPULSES 0xc 133 #define SDEDM_FSM_WRITEWAIT2 0xd 134 #define SDEDM_FSM_STARTPOWDOWN 0xf 135 136 #define SDDATA_FIFO_WORDS 16 137 138 #define FIFO_READ_THRESHOLD 4 139 #define FIFO_WRITE_THRESHOLD 4 140 #define SDDATA_FIFO_PIO_BURST 8 141 142 #define PIO_THRESHOLD 1 /* Maximum block count for PIO (0 = always DMA) */ 143 144 struct bcm2835_host { 145 spinlock_t lock; 146 struct mutex mutex; 147 148 void __iomem *ioaddr; 149 u32 phys_addr; 150 151 struct mmc_host *mmc; 152 struct platform_device *pdev; 153 154 int clock; /* Current clock speed */ 155 unsigned int max_clk; /* Max possible freq */ 156 struct work_struct dma_work; 157 struct delayed_work timeout_work; /* Timer for timeouts */ 158 struct sg_mapping_iter sg_miter; /* SG state for PIO */ 159 unsigned int blocks; /* remaining PIO blocks */ 160 int irq; /* Device IRQ */ 161 162 u32 ns_per_fifo_word; 163 164 /* cached registers */ 165 u32 hcfg; 166 u32 cdiv; 167 168 struct mmc_request *mrq; /* Current request */ 169 struct mmc_command *cmd; /* Current command */ 170 struct mmc_data *data; /* Current data request */ 171 bool data_complete:1;/* Data finished before cmd */ 172 bool use_busy:1; /* Wait for busy interrupt */ 173 bool use_sbc:1; /* Send CMD23 */ 174 175 /* for threaded irq handler */ 176 bool irq_block; 177 bool irq_busy; 178 bool irq_data; 179 180 /* DMA part */ 181 struct dma_chan *dma_chan_rxtx; 182 struct dma_chan *dma_chan; 183 struct dma_slave_config dma_cfg_rx; 184 struct dma_slave_config dma_cfg_tx; 185 struct dma_async_tx_descriptor *dma_desc; 186 u32 dma_dir; 187 u32 drain_words; 188 struct page *drain_page; 189 u32 drain_offset; 190 bool use_dma; 191 }; 192 193 static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd, 194 const char *label) 195 { 196 struct device *dev = &host->pdev->dev; 197 198 if (!cmd) 199 return; 200 201 dev_dbg(dev, "%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n", 202 (cmd == host->cmd) ? '>' : ' ', 203 label, cmd->opcode, cmd->arg, cmd->flags, 204 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], 205 cmd->error); 206 } 207 208 static void bcm2835_dumpregs(struct bcm2835_host *host) 209 { 210 struct mmc_request *mrq = host->mrq; 211 struct device *dev = &host->pdev->dev; 212 213 if (mrq) { 214 bcm2835_dumpcmd(host, mrq->sbc, "sbc"); 215 bcm2835_dumpcmd(host, mrq->cmd, "cmd"); 216 if (mrq->data) { 217 dev_dbg(dev, "data blocks %x blksz %x - err %d\n", 218 mrq->data->blocks, 219 mrq->data->blksz, 220 mrq->data->error); 221 } 222 bcm2835_dumpcmd(host, mrq->stop, "stop"); 223 } 224 225 dev_dbg(dev, "=========== REGISTER DUMP ===========\n"); 226 dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD)); 227 dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG)); 228 dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT)); 229 dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV)); 230 dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0)); 231 dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1)); 232 dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2)); 233 dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3)); 234 dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS)); 235 dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD)); 236 dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM)); 237 dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG)); 238 dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT)); 239 dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC)); 240 dev_dbg(dev, "===========================================\n"); 241 } 242 243 static void bcm2835_reset_internal(struct bcm2835_host *host) 244 { 245 u32 temp; 246 247 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 248 writel(0, host->ioaddr + SDCMD); 249 writel(0, host->ioaddr + SDARG); 250 writel(0xf00000, host->ioaddr + SDTOUT); 251 writel(0, host->ioaddr + SDCDIV); 252 writel(0x7f8, host->ioaddr + SDHSTS); /* Write 1s to clear */ 253 writel(0, host->ioaddr + SDHCFG); 254 writel(0, host->ioaddr + SDHBCT); 255 writel(0, host->ioaddr + SDHBLC); 256 257 /* Limit fifo usage due to silicon bug */ 258 temp = readl(host->ioaddr + SDEDM); 259 temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) | 260 (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT)); 261 temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) | 262 (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT); 263 writel(temp, host->ioaddr + SDEDM); 264 msleep(20); 265 writel(SDVDD_POWER_ON, host->ioaddr + SDVDD); 266 msleep(20); 267 host->clock = 0; 268 writel(host->hcfg, host->ioaddr + SDHCFG); 269 writel(host->cdiv, host->ioaddr + SDCDIV); 270 } 271 272 static void bcm2835_reset(struct mmc_host *mmc) 273 { 274 struct bcm2835_host *host = mmc_priv(mmc); 275 276 if (host->dma_chan) 277 dmaengine_terminate_sync(host->dma_chan); 278 host->dma_chan = NULL; 279 bcm2835_reset_internal(host); 280 } 281 282 static void bcm2835_finish_command(struct bcm2835_host *host); 283 284 static void bcm2835_wait_transfer_complete(struct bcm2835_host *host) 285 { 286 int timediff; 287 u32 alternate_idle; 288 289 alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ? 290 SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1; 291 292 timediff = 0; 293 294 while (1) { 295 u32 edm, fsm; 296 297 edm = readl(host->ioaddr + SDEDM); 298 fsm = edm & SDEDM_FSM_MASK; 299 300 if ((fsm == SDEDM_FSM_IDENTMODE) || 301 (fsm == SDEDM_FSM_DATAMODE)) 302 break; 303 if (fsm == alternate_idle) { 304 writel(edm | SDEDM_FORCE_DATA_MODE, 305 host->ioaddr + SDEDM); 306 break; 307 } 308 309 timediff++; 310 if (timediff == 100000) { 311 dev_err(&host->pdev->dev, 312 "wait_transfer_complete - still waiting after %d retries\n", 313 timediff); 314 bcm2835_dumpregs(host); 315 host->mrq->data->error = -ETIMEDOUT; 316 return; 317 } 318 cpu_relax(); 319 } 320 } 321 322 static void bcm2835_dma_complete(void *param) 323 { 324 struct bcm2835_host *host = param; 325 326 schedule_work(&host->dma_work); 327 } 328 329 static void bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read) 330 { 331 unsigned long flags; 332 size_t blksize; 333 unsigned long wait_max; 334 335 blksize = host->data->blksz; 336 337 wait_max = jiffies + msecs_to_jiffies(500); 338 339 local_irq_save(flags); 340 341 while (blksize) { 342 int copy_words; 343 u32 hsts = 0; 344 size_t len; 345 u32 *buf; 346 347 if (!sg_miter_next(&host->sg_miter)) { 348 host->data->error = -EINVAL; 349 break; 350 } 351 352 len = min(host->sg_miter.length, blksize); 353 if (len % 4) { 354 host->data->error = -EINVAL; 355 break; 356 } 357 358 blksize -= len; 359 host->sg_miter.consumed = len; 360 361 buf = (u32 *)host->sg_miter.addr; 362 363 copy_words = len / 4; 364 365 while (copy_words) { 366 int burst_words, words; 367 u32 edm; 368 369 burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words); 370 edm = readl(host->ioaddr + SDEDM); 371 if (is_read) 372 words = ((edm >> 4) & 0x1f); 373 else 374 words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f); 375 376 if (words < burst_words) { 377 int fsm_state = (edm & SDEDM_FSM_MASK); 378 struct device *dev = &host->pdev->dev; 379 380 if ((is_read && 381 (fsm_state != SDEDM_FSM_READDATA && 382 fsm_state != SDEDM_FSM_READWAIT && 383 fsm_state != SDEDM_FSM_READCRC)) || 384 (!is_read && 385 (fsm_state != SDEDM_FSM_WRITEDATA && 386 fsm_state != SDEDM_FSM_WRITESTART1 && 387 fsm_state != SDEDM_FSM_WRITESTART2))) { 388 hsts = readl(host->ioaddr + SDHSTS); 389 dev_err(dev, "fsm %x, hsts %08x\n", 390 fsm_state, hsts); 391 if (hsts & SDHSTS_ERROR_MASK) 392 break; 393 } 394 395 if (time_after(jiffies, wait_max)) { 396 dev_err(dev, "PIO %s timeout - EDM %08x\n", 397 is_read ? "read" : "write", 398 edm); 399 hsts = SDHSTS_REW_TIME_OUT; 400 break; 401 } 402 ndelay((burst_words - words) * 403 host->ns_per_fifo_word); 404 continue; 405 } else if (words > copy_words) { 406 words = copy_words; 407 } 408 409 copy_words -= words; 410 411 while (words) { 412 if (is_read) 413 *(buf++) = readl(host->ioaddr + SDDATA); 414 else 415 writel(*(buf++), host->ioaddr + SDDATA); 416 words--; 417 } 418 } 419 420 if (hsts & SDHSTS_ERROR_MASK) 421 break; 422 } 423 424 sg_miter_stop(&host->sg_miter); 425 426 local_irq_restore(flags); 427 } 428 429 static void bcm2835_transfer_pio(struct bcm2835_host *host) 430 { 431 struct device *dev = &host->pdev->dev; 432 u32 sdhsts; 433 bool is_read; 434 435 is_read = (host->data->flags & MMC_DATA_READ) != 0; 436 bcm2835_transfer_block_pio(host, is_read); 437 438 sdhsts = readl(host->ioaddr + SDHSTS); 439 if (sdhsts & (SDHSTS_CRC16_ERROR | 440 SDHSTS_CRC7_ERROR | 441 SDHSTS_FIFO_ERROR)) { 442 dev_err(dev, "%s transfer error - HSTS %08x\n", 443 is_read ? "read" : "write", sdhsts); 444 host->data->error = -EILSEQ; 445 } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT | 446 SDHSTS_REW_TIME_OUT))) { 447 dev_err(dev, "%s timeout error - HSTS %08x\n", 448 is_read ? "read" : "write", sdhsts); 449 host->data->error = -ETIMEDOUT; 450 } 451 } 452 453 static 454 void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data) 455 { 456 int len, dir_data, dir_slave; 457 struct dma_async_tx_descriptor *desc = NULL; 458 struct dma_chan *dma_chan; 459 460 dma_chan = host->dma_chan_rxtx; 461 if (data->flags & MMC_DATA_READ) { 462 dir_data = DMA_FROM_DEVICE; 463 dir_slave = DMA_DEV_TO_MEM; 464 } else { 465 dir_data = DMA_TO_DEVICE; 466 dir_slave = DMA_MEM_TO_DEV; 467 } 468 469 /* The block doesn't manage the FIFO DREQs properly for 470 * multi-block transfers, so don't attempt to DMA the final 471 * few words. Unfortunately this requires the final sg entry 472 * to be trimmed. N.B. This code demands that the overspill 473 * is contained in a single sg entry. 474 */ 475 476 host->drain_words = 0; 477 if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) { 478 struct scatterlist *sg; 479 u32 len; 480 int i; 481 482 len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4, 483 (u32)data->blocks * data->blksz); 484 485 for_each_sg(data->sg, sg, data->sg_len, i) { 486 if (sg_is_last(sg)) { 487 WARN_ON(sg->length < len); 488 sg->length -= len; 489 host->drain_page = sg_page(sg); 490 host->drain_offset = sg->offset + sg->length; 491 } 492 } 493 host->drain_words = len / 4; 494 } 495 496 /* The parameters have already been validated, so this will not fail */ 497 (void)dmaengine_slave_config(dma_chan, 498 (dir_data == DMA_FROM_DEVICE) ? 499 &host->dma_cfg_rx : 500 &host->dma_cfg_tx); 501 502 len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len, 503 dir_data); 504 505 if (len > 0) { 506 desc = dmaengine_prep_slave_sg(dma_chan, data->sg, 507 len, dir_slave, 508 DMA_PREP_INTERRUPT | 509 DMA_CTRL_ACK); 510 } 511 512 if (desc) { 513 desc->callback = bcm2835_dma_complete; 514 desc->callback_param = host; 515 host->dma_desc = desc; 516 host->dma_chan = dma_chan; 517 host->dma_dir = dir_data; 518 } 519 } 520 521 static void bcm2835_start_dma(struct bcm2835_host *host) 522 { 523 dmaengine_submit(host->dma_desc); 524 dma_async_issue_pending(host->dma_chan); 525 } 526 527 static void bcm2835_set_transfer_irqs(struct bcm2835_host *host) 528 { 529 u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN | 530 SDHCFG_BUSY_IRPT_EN; 531 532 if (host->dma_desc) { 533 host->hcfg = (host->hcfg & ~all_irqs) | 534 SDHCFG_BUSY_IRPT_EN; 535 } else { 536 host->hcfg = (host->hcfg & ~all_irqs) | 537 SDHCFG_DATA_IRPT_EN | 538 SDHCFG_BUSY_IRPT_EN; 539 } 540 541 writel(host->hcfg, host->ioaddr + SDHCFG); 542 } 543 544 static 545 void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd) 546 { 547 struct mmc_data *data = cmd->data; 548 549 WARN_ON(host->data); 550 551 host->data = data; 552 if (!data) 553 return; 554 555 host->data_complete = false; 556 host->data->bytes_xfered = 0; 557 558 if (!host->dma_desc) { 559 /* Use PIO */ 560 int flags = SG_MITER_ATOMIC; 561 562 if (data->flags & MMC_DATA_READ) 563 flags |= SG_MITER_TO_SG; 564 else 565 flags |= SG_MITER_FROM_SG; 566 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 567 host->blocks = data->blocks; 568 } 569 570 bcm2835_set_transfer_irqs(host); 571 572 writel(data->blksz, host->ioaddr + SDHBCT); 573 writel(data->blocks, host->ioaddr + SDHBLC); 574 } 575 576 static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host, u32 max_ms) 577 { 578 struct device *dev = &host->pdev->dev; 579 u32 value; 580 int ret; 581 582 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 583 !(value & SDCMD_NEW_FLAG), 1, 10); 584 if (ret == -ETIMEDOUT) 585 /* if it takes a while make poll interval bigger */ 586 ret = readl_poll_timeout(host->ioaddr + SDCMD, value, 587 !(value & SDCMD_NEW_FLAG), 588 10, max_ms * 1000); 589 if (ret == -ETIMEDOUT) 590 dev_err(dev, "%s: timeout (%d ms)\n", __func__, max_ms); 591 592 return value; 593 } 594 595 static void bcm2835_finish_request(struct bcm2835_host *host) 596 { 597 struct dma_chan *terminate_chan = NULL; 598 struct mmc_request *mrq; 599 600 cancel_delayed_work(&host->timeout_work); 601 602 mrq = host->mrq; 603 604 host->mrq = NULL; 605 host->cmd = NULL; 606 host->data = NULL; 607 608 host->dma_desc = NULL; 609 terminate_chan = host->dma_chan; 610 host->dma_chan = NULL; 611 612 if (terminate_chan) { 613 int err = dmaengine_terminate_all(terminate_chan); 614 615 if (err) 616 dev_err(&host->pdev->dev, 617 "failed to terminate DMA (%d)\n", err); 618 } 619 620 mmc_request_done(host->mmc, mrq); 621 } 622 623 static 624 bool bcm2835_send_command(struct bcm2835_host *host, struct mmc_command *cmd) 625 { 626 struct device *dev = &host->pdev->dev; 627 u32 sdcmd, sdhsts; 628 unsigned long timeout; 629 630 WARN_ON(host->cmd); 631 632 sdcmd = bcm2835_read_wait_sdcmd(host, 100); 633 if (sdcmd & SDCMD_NEW_FLAG) { 634 dev_err(dev, "previous command never completed.\n"); 635 bcm2835_dumpregs(host); 636 cmd->error = -EILSEQ; 637 bcm2835_finish_request(host); 638 return false; 639 } 640 641 if (!cmd->data && cmd->busy_timeout > 9000) 642 timeout = DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; 643 else 644 timeout = 10 * HZ; 645 schedule_delayed_work(&host->timeout_work, timeout); 646 647 host->cmd = cmd; 648 649 /* Clear any error flags */ 650 sdhsts = readl(host->ioaddr + SDHSTS); 651 if (sdhsts & SDHSTS_ERROR_MASK) 652 writel(sdhsts, host->ioaddr + SDHSTS); 653 654 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { 655 dev_err(dev, "unsupported response type!\n"); 656 cmd->error = -EINVAL; 657 bcm2835_finish_request(host); 658 return false; 659 } 660 661 bcm2835_prepare_data(host, cmd); 662 663 writel(cmd->arg, host->ioaddr + SDARG); 664 665 sdcmd = cmd->opcode & SDCMD_CMD_MASK; 666 667 host->use_busy = false; 668 if (!(cmd->flags & MMC_RSP_PRESENT)) { 669 sdcmd |= SDCMD_NO_RESPONSE; 670 } else { 671 if (cmd->flags & MMC_RSP_136) 672 sdcmd |= SDCMD_LONG_RESPONSE; 673 if (cmd->flags & MMC_RSP_BUSY) { 674 sdcmd |= SDCMD_BUSYWAIT; 675 host->use_busy = true; 676 } 677 } 678 679 if (cmd->data) { 680 if (cmd->data->flags & MMC_DATA_WRITE) 681 sdcmd |= SDCMD_WRITE_CMD; 682 if (cmd->data->flags & MMC_DATA_READ) 683 sdcmd |= SDCMD_READ_CMD; 684 } 685 686 writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD); 687 688 return true; 689 } 690 691 static void bcm2835_transfer_complete(struct bcm2835_host *host) 692 { 693 struct mmc_data *data; 694 695 WARN_ON(!host->data_complete); 696 697 data = host->data; 698 host->data = NULL; 699 700 /* Need to send CMD12 if - 701 * a) open-ended multiblock transfer (no CMD23) 702 * b) error in multiblock transfer 703 */ 704 if (host->mrq->stop && (data->error || !host->use_sbc)) { 705 if (bcm2835_send_command(host, host->mrq->stop)) { 706 /* No busy, so poll for completion */ 707 if (!host->use_busy) 708 bcm2835_finish_command(host); 709 } 710 } else { 711 bcm2835_wait_transfer_complete(host); 712 bcm2835_finish_request(host); 713 } 714 } 715 716 static void bcm2835_finish_data(struct bcm2835_host *host) 717 { 718 struct device *dev = &host->pdev->dev; 719 struct mmc_data *data; 720 721 data = host->data; 722 723 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 724 writel(host->hcfg, host->ioaddr + SDHCFG); 725 726 data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks); 727 728 host->data_complete = true; 729 730 if (host->cmd) { 731 /* Data managed to finish before the 732 * command completed. Make sure we do 733 * things in the proper order. 734 */ 735 dev_dbg(dev, "Finished early - HSTS %08x\n", 736 readl(host->ioaddr + SDHSTS)); 737 } else { 738 bcm2835_transfer_complete(host); 739 } 740 } 741 742 static void bcm2835_finish_command(struct bcm2835_host *host) 743 { 744 struct device *dev = &host->pdev->dev; 745 struct mmc_command *cmd = host->cmd; 746 u32 sdcmd; 747 748 sdcmd = bcm2835_read_wait_sdcmd(host, 100); 749 750 /* Check for errors */ 751 if (sdcmd & SDCMD_NEW_FLAG) { 752 dev_err(dev, "command never completed.\n"); 753 bcm2835_dumpregs(host); 754 host->cmd->error = -EIO; 755 bcm2835_finish_request(host); 756 return; 757 } else if (sdcmd & SDCMD_FAIL_FLAG) { 758 u32 sdhsts = readl(host->ioaddr + SDHSTS); 759 760 /* Clear the errors */ 761 writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS); 762 763 if (!(sdhsts & SDHSTS_CRC7_ERROR) || 764 (host->cmd->opcode != MMC_SEND_OP_COND)) { 765 u32 edm, fsm; 766 767 if (sdhsts & SDHSTS_CMD_TIME_OUT) { 768 host->cmd->error = -ETIMEDOUT; 769 } else { 770 dev_err(dev, "unexpected command %d error\n", 771 host->cmd->opcode); 772 bcm2835_dumpregs(host); 773 host->cmd->error = -EILSEQ; 774 } 775 edm = readl(host->ioaddr + SDEDM); 776 fsm = edm & SDEDM_FSM_MASK; 777 if (fsm == SDEDM_FSM_READWAIT || 778 fsm == SDEDM_FSM_WRITESTART1) 779 /* Kick the FSM out of its wait */ 780 writel(edm | SDEDM_FORCE_DATA_MODE, 781 host->ioaddr + SDEDM); 782 bcm2835_finish_request(host); 783 return; 784 } 785 } 786 787 if (cmd->flags & MMC_RSP_PRESENT) { 788 if (cmd->flags & MMC_RSP_136) { 789 int i; 790 791 for (i = 0; i < 4; i++) { 792 cmd->resp[3 - i] = 793 readl(host->ioaddr + SDRSP0 + i * 4); 794 } 795 } else { 796 cmd->resp[0] = readl(host->ioaddr + SDRSP0); 797 } 798 } 799 800 if (cmd == host->mrq->sbc) { 801 /* Finished CMD23, now send actual command. */ 802 host->cmd = NULL; 803 if (bcm2835_send_command(host, host->mrq->cmd)) { 804 if (host->data && host->dma_desc) 805 /* DMA transfer starts now, PIO starts 806 * after irq 807 */ 808 bcm2835_start_dma(host); 809 810 if (!host->use_busy) 811 bcm2835_finish_command(host); 812 } 813 } else if (cmd == host->mrq->stop) { 814 /* Finished CMD12 */ 815 bcm2835_finish_request(host); 816 } else { 817 /* Processed actual command. */ 818 host->cmd = NULL; 819 if (!host->data) 820 bcm2835_finish_request(host); 821 else if (host->data_complete) 822 bcm2835_transfer_complete(host); 823 } 824 } 825 826 static void bcm2835_timeout(struct work_struct *work) 827 { 828 struct delayed_work *d = to_delayed_work(work); 829 struct bcm2835_host *host = 830 container_of(d, struct bcm2835_host, timeout_work); 831 struct device *dev = &host->pdev->dev; 832 833 mutex_lock(&host->mutex); 834 835 if (host->mrq) { 836 dev_err(dev, "timeout waiting for hardware interrupt.\n"); 837 bcm2835_dumpregs(host); 838 839 bcm2835_reset(host->mmc); 840 841 if (host->data) { 842 host->data->error = -ETIMEDOUT; 843 bcm2835_finish_data(host); 844 } else { 845 if (host->cmd) 846 host->cmd->error = -ETIMEDOUT; 847 else 848 host->mrq->cmd->error = -ETIMEDOUT; 849 850 bcm2835_finish_request(host); 851 } 852 } 853 854 mutex_unlock(&host->mutex); 855 } 856 857 static bool bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask) 858 { 859 struct device *dev = &host->pdev->dev; 860 861 if (!(intmask & SDHSTS_ERROR_MASK)) 862 return false; 863 864 if (!host->cmd) 865 return true; 866 867 dev_err(dev, "sdhost_busy_irq: intmask %08x\n", intmask); 868 if (intmask & SDHSTS_CRC7_ERROR) { 869 host->cmd->error = -EILSEQ; 870 } else if (intmask & (SDHSTS_CRC16_ERROR | 871 SDHSTS_FIFO_ERROR)) { 872 if (host->mrq->data) 873 host->mrq->data->error = -EILSEQ; 874 else 875 host->cmd->error = -EILSEQ; 876 } else if (intmask & SDHSTS_REW_TIME_OUT) { 877 if (host->mrq->data) 878 host->mrq->data->error = -ETIMEDOUT; 879 else 880 host->cmd->error = -ETIMEDOUT; 881 } else if (intmask & SDHSTS_CMD_TIME_OUT) { 882 host->cmd->error = -ETIMEDOUT; 883 } 884 bcm2835_dumpregs(host); 885 return true; 886 } 887 888 static void bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask) 889 { 890 if (!host->data) 891 return; 892 if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR)) 893 host->data->error = -EILSEQ; 894 if (intmask & SDHSTS_REW_TIME_OUT) 895 host->data->error = -ETIMEDOUT; 896 } 897 898 static void bcm2835_busy_irq(struct bcm2835_host *host) 899 { 900 if (WARN_ON(!host->cmd)) { 901 bcm2835_dumpregs(host); 902 return; 903 } 904 905 if (WARN_ON(!host->use_busy)) { 906 bcm2835_dumpregs(host); 907 return; 908 } 909 host->use_busy = false; 910 911 bcm2835_finish_command(host); 912 } 913 914 static void bcm2835_data_irq(struct bcm2835_host *host, u32 intmask) 915 { 916 /* There are no dedicated data/space available interrupt 917 * status bits, so it is necessary to use the single shared 918 * data/space available FIFO status bits. It is therefore not 919 * an error to get here when there is no data transfer in 920 * progress. 921 */ 922 if (!host->data) 923 return; 924 925 bcm2835_check_data_error(host, intmask); 926 if (host->data->error) 927 goto finished; 928 929 if (host->data->flags & MMC_DATA_WRITE) { 930 /* Use the block interrupt for writes after the first block */ 931 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN); 932 host->hcfg |= SDHCFG_BLOCK_IRPT_EN; 933 writel(host->hcfg, host->ioaddr + SDHCFG); 934 bcm2835_transfer_pio(host); 935 } else { 936 bcm2835_transfer_pio(host); 937 host->blocks--; 938 if ((host->blocks == 0) || host->data->error) 939 goto finished; 940 } 941 return; 942 943 finished: 944 host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN); 945 writel(host->hcfg, host->ioaddr + SDHCFG); 946 } 947 948 static void bcm2835_data_threaded_irq(struct bcm2835_host *host) 949 { 950 if (!host->data) 951 return; 952 if ((host->blocks == 0) || host->data->error) 953 bcm2835_finish_data(host); 954 } 955 956 static void bcm2835_block_irq(struct bcm2835_host *host) 957 { 958 if (WARN_ON(!host->data)) { 959 bcm2835_dumpregs(host); 960 return; 961 } 962 963 if (!host->dma_desc) { 964 WARN_ON(!host->blocks); 965 if (host->data->error || (--host->blocks == 0)) 966 bcm2835_finish_data(host); 967 else 968 bcm2835_transfer_pio(host); 969 } else if (host->data->flags & MMC_DATA_WRITE) { 970 bcm2835_finish_data(host); 971 } 972 } 973 974 static irqreturn_t bcm2835_irq(int irq, void *dev_id) 975 { 976 irqreturn_t result = IRQ_NONE; 977 struct bcm2835_host *host = dev_id; 978 u32 intmask; 979 980 spin_lock(&host->lock); 981 982 intmask = readl(host->ioaddr + SDHSTS); 983 984 writel(SDHSTS_BUSY_IRPT | 985 SDHSTS_BLOCK_IRPT | 986 SDHSTS_SDIO_IRPT | 987 SDHSTS_DATA_FLAG, 988 host->ioaddr + SDHSTS); 989 990 if (intmask & SDHSTS_BLOCK_IRPT) { 991 bcm2835_check_data_error(host, intmask); 992 host->irq_block = true; 993 result = IRQ_WAKE_THREAD; 994 } 995 996 if (intmask & SDHSTS_BUSY_IRPT) { 997 if (!bcm2835_check_cmd_error(host, intmask)) { 998 host->irq_busy = true; 999 result = IRQ_WAKE_THREAD; 1000 } else { 1001 result = IRQ_HANDLED; 1002 } 1003 } 1004 1005 /* There is no true data interrupt status bit, so it is 1006 * necessary to qualify the data flag with the interrupt 1007 * enable bit. 1008 */ 1009 if ((intmask & SDHSTS_DATA_FLAG) && 1010 (host->hcfg & SDHCFG_DATA_IRPT_EN)) { 1011 bcm2835_data_irq(host, intmask); 1012 host->irq_data = true; 1013 result = IRQ_WAKE_THREAD; 1014 } 1015 1016 spin_unlock(&host->lock); 1017 1018 return result; 1019 } 1020 1021 static irqreturn_t bcm2835_threaded_irq(int irq, void *dev_id) 1022 { 1023 struct bcm2835_host *host = dev_id; 1024 unsigned long flags; 1025 bool block, busy, data; 1026 1027 spin_lock_irqsave(&host->lock, flags); 1028 1029 block = host->irq_block; 1030 busy = host->irq_busy; 1031 data = host->irq_data; 1032 host->irq_block = false; 1033 host->irq_busy = false; 1034 host->irq_data = false; 1035 1036 spin_unlock_irqrestore(&host->lock, flags); 1037 1038 mutex_lock(&host->mutex); 1039 1040 if (block) 1041 bcm2835_block_irq(host); 1042 if (busy) 1043 bcm2835_busy_irq(host); 1044 if (data) 1045 bcm2835_data_threaded_irq(host); 1046 1047 mutex_unlock(&host->mutex); 1048 1049 return IRQ_HANDLED; 1050 } 1051 1052 static void bcm2835_dma_complete_work(struct work_struct *work) 1053 { 1054 struct bcm2835_host *host = 1055 container_of(work, struct bcm2835_host, dma_work); 1056 struct mmc_data *data = host->data; 1057 1058 mutex_lock(&host->mutex); 1059 1060 if (host->dma_chan) { 1061 dma_unmap_sg(host->dma_chan->device->dev, 1062 data->sg, data->sg_len, 1063 host->dma_dir); 1064 1065 host->dma_chan = NULL; 1066 } 1067 1068 if (host->drain_words) { 1069 unsigned long flags; 1070 void *page; 1071 u32 *buf; 1072 1073 if (host->drain_offset & PAGE_MASK) { 1074 host->drain_page += host->drain_offset >> PAGE_SHIFT; 1075 host->drain_offset &= ~PAGE_MASK; 1076 } 1077 local_irq_save(flags); 1078 page = kmap_atomic(host->drain_page); 1079 buf = page + host->drain_offset; 1080 1081 while (host->drain_words) { 1082 u32 edm = readl(host->ioaddr + SDEDM); 1083 1084 if ((edm >> 4) & 0x1f) 1085 *(buf++) = readl(host->ioaddr + SDDATA); 1086 host->drain_words--; 1087 } 1088 1089 kunmap_atomic(page); 1090 local_irq_restore(flags); 1091 } 1092 1093 bcm2835_finish_data(host); 1094 1095 mutex_unlock(&host->mutex); 1096 } 1097 1098 static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock) 1099 { 1100 int div; 1101 1102 /* The SDCDIV register has 11 bits, and holds (div - 2). But 1103 * in data mode the max is 50MHz wihout a minimum, and only 1104 * the bottom 3 bits are used. Since the switch over is 1105 * automatic (unless we have marked the card as slow...), 1106 * chosen values have to make sense in both modes. Ident mode 1107 * must be 100-400KHz, so can range check the requested 1108 * clock. CMD15 must be used to return to data mode, so this 1109 * can be monitored. 1110 * 1111 * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz 1112 * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz 1113 * 1114 * 623->400KHz/27.8MHz 1115 * reset value (507)->491159/50MHz 1116 * 1117 * BUT, the 3-bit clock divisor in data mode is too small if 1118 * the core clock is higher than 250MHz, so instead use the 1119 * SLOW_CARD configuration bit to force the use of the ident 1120 * clock divisor at all times. 1121 */ 1122 1123 if (clock < 100000) { 1124 /* Can't stop the clock, but make it as slow as possible 1125 * to show willing 1126 */ 1127 host->cdiv = SDCDIV_MAX_CDIV; 1128 writel(host->cdiv, host->ioaddr + SDCDIV); 1129 return; 1130 } 1131 1132 div = host->max_clk / clock; 1133 if (div < 2) 1134 div = 2; 1135 if ((host->max_clk / div) > clock) 1136 div++; 1137 div -= 2; 1138 1139 if (div > SDCDIV_MAX_CDIV) 1140 div = SDCDIV_MAX_CDIV; 1141 1142 clock = host->max_clk / (div + 2); 1143 host->mmc->actual_clock = clock; 1144 1145 /* Calibrate some delays */ 1146 1147 host->ns_per_fifo_word = (1000000000 / clock) * 1148 ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32); 1149 1150 host->cdiv = div; 1151 writel(host->cdiv, host->ioaddr + SDCDIV); 1152 1153 /* Set the timeout to 500ms */ 1154 writel(host->mmc->actual_clock / 2, host->ioaddr + SDTOUT); 1155 } 1156 1157 static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq) 1158 { 1159 struct bcm2835_host *host = mmc_priv(mmc); 1160 struct device *dev = &host->pdev->dev; 1161 u32 edm, fsm; 1162 1163 /* Reset the error statuses in case this is a retry */ 1164 if (mrq->sbc) 1165 mrq->sbc->error = 0; 1166 if (mrq->cmd) 1167 mrq->cmd->error = 0; 1168 if (mrq->data) 1169 mrq->data->error = 0; 1170 if (mrq->stop) 1171 mrq->stop->error = 0; 1172 1173 if (mrq->data && !is_power_of_2(mrq->data->blksz)) { 1174 dev_err(dev, "unsupported block size (%d bytes)\n", 1175 mrq->data->blksz); 1176 1177 if (mrq->cmd) 1178 mrq->cmd->error = -EINVAL; 1179 1180 mmc_request_done(mmc, mrq); 1181 return; 1182 } 1183 1184 if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD)) 1185 bcm2835_prepare_dma(host, mrq->data); 1186 1187 mutex_lock(&host->mutex); 1188 1189 WARN_ON(host->mrq); 1190 host->mrq = mrq; 1191 1192 edm = readl(host->ioaddr + SDEDM); 1193 fsm = edm & SDEDM_FSM_MASK; 1194 1195 if ((fsm != SDEDM_FSM_IDENTMODE) && 1196 (fsm != SDEDM_FSM_DATAMODE)) { 1197 dev_err(dev, "previous command (%d) not complete (EDM %08x)\n", 1198 readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, 1199 edm); 1200 bcm2835_dumpregs(host); 1201 1202 if (mrq->cmd) 1203 mrq->cmd->error = -EILSEQ; 1204 1205 bcm2835_finish_request(host); 1206 mutex_unlock(&host->mutex); 1207 return; 1208 } 1209 1210 host->use_sbc = !!mrq->sbc && host->mrq->data && 1211 (host->mrq->data->flags & MMC_DATA_READ); 1212 if (host->use_sbc) { 1213 if (bcm2835_send_command(host, mrq->sbc)) { 1214 if (!host->use_busy) 1215 bcm2835_finish_command(host); 1216 } 1217 } else if (mrq->cmd && bcm2835_send_command(host, mrq->cmd)) { 1218 if (host->data && host->dma_desc) { 1219 /* DMA transfer starts now, PIO starts after irq */ 1220 bcm2835_start_dma(host); 1221 } 1222 1223 if (!host->use_busy) 1224 bcm2835_finish_command(host); 1225 } 1226 1227 mutex_unlock(&host->mutex); 1228 } 1229 1230 static void bcm2835_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1231 { 1232 struct bcm2835_host *host = mmc_priv(mmc); 1233 1234 mutex_lock(&host->mutex); 1235 1236 if (!ios->clock || ios->clock != host->clock) { 1237 bcm2835_set_clock(host, ios->clock); 1238 host->clock = ios->clock; 1239 } 1240 1241 /* set bus width */ 1242 host->hcfg &= ~SDHCFG_WIDE_EXT_BUS; 1243 if (ios->bus_width == MMC_BUS_WIDTH_4) 1244 host->hcfg |= SDHCFG_WIDE_EXT_BUS; 1245 1246 host->hcfg |= SDHCFG_WIDE_INT_BUS; 1247 1248 /* Disable clever clock switching, to cope with fast core clocks */ 1249 host->hcfg |= SDHCFG_SLOW_CARD; 1250 1251 writel(host->hcfg, host->ioaddr + SDHCFG); 1252 1253 mutex_unlock(&host->mutex); 1254 } 1255 1256 static const struct mmc_host_ops bcm2835_ops = { 1257 .request = bcm2835_request, 1258 .set_ios = bcm2835_set_ios, 1259 .hw_reset = bcm2835_reset, 1260 }; 1261 1262 static int bcm2835_add_host(struct bcm2835_host *host) 1263 { 1264 struct mmc_host *mmc = host->mmc; 1265 struct device *dev = &host->pdev->dev; 1266 char pio_limit_string[20]; 1267 int ret; 1268 1269 if (!mmc->f_max || mmc->f_max > host->max_clk) 1270 mmc->f_max = host->max_clk; 1271 mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; 1272 1273 mmc->max_busy_timeout = ~0 / (mmc->f_max / 1000); 1274 1275 dev_dbg(dev, "f_max %d, f_min %d, max_busy_timeout %d\n", 1276 mmc->f_max, mmc->f_min, mmc->max_busy_timeout); 1277 1278 /* host controller capabilities */ 1279 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | 1280 MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE | 1281 MMC_CAP_CMD23; 1282 1283 spin_lock_init(&host->lock); 1284 mutex_init(&host->mutex); 1285 1286 if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) { 1287 dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n"); 1288 host->use_dma = false; 1289 } else { 1290 host->use_dma = true; 1291 1292 host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1293 host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1294 host->dma_cfg_tx.slave_id = 13; /* DREQ channel */ 1295 host->dma_cfg_tx.direction = DMA_MEM_TO_DEV; 1296 host->dma_cfg_tx.src_addr = 0; 1297 host->dma_cfg_tx.dst_addr = host->phys_addr + SDDATA; 1298 1299 host->dma_cfg_rx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1300 host->dma_cfg_rx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1301 host->dma_cfg_rx.slave_id = 13; /* DREQ channel */ 1302 host->dma_cfg_rx.direction = DMA_DEV_TO_MEM; 1303 host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA; 1304 host->dma_cfg_rx.dst_addr = 0; 1305 1306 if (dmaengine_slave_config(host->dma_chan_rxtx, 1307 &host->dma_cfg_tx) != 0 || 1308 dmaengine_slave_config(host->dma_chan_rxtx, 1309 &host->dma_cfg_rx) != 0) 1310 host->use_dma = false; 1311 } 1312 1313 mmc->max_segs = 128; 1314 mmc->max_req_size = 524288; 1315 mmc->max_seg_size = mmc->max_req_size; 1316 mmc->max_blk_size = 1024; 1317 mmc->max_blk_count = 65535; 1318 1319 /* report supported voltage ranges */ 1320 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 1321 1322 INIT_WORK(&host->dma_work, bcm2835_dma_complete_work); 1323 INIT_DELAYED_WORK(&host->timeout_work, bcm2835_timeout); 1324 1325 /* Set interrupt enables */ 1326 host->hcfg = SDHCFG_BUSY_IRPT_EN; 1327 1328 bcm2835_reset_internal(host); 1329 1330 ret = request_threaded_irq(host->irq, bcm2835_irq, 1331 bcm2835_threaded_irq, 1332 0, mmc_hostname(mmc), host); 1333 if (ret) { 1334 dev_err(dev, "failed to request IRQ %d: %d\n", host->irq, ret); 1335 return ret; 1336 } 1337 1338 ret = mmc_add_host(mmc); 1339 if (ret) { 1340 free_irq(host->irq, host); 1341 return ret; 1342 } 1343 1344 pio_limit_string[0] = '\0'; 1345 if (host->use_dma && (PIO_THRESHOLD > 0)) 1346 sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD); 1347 dev_info(dev, "loaded - DMA %s%s\n", 1348 host->use_dma ? "enabled" : "disabled", pio_limit_string); 1349 1350 return 0; 1351 } 1352 1353 static int bcm2835_probe(struct platform_device *pdev) 1354 { 1355 struct device *dev = &pdev->dev; 1356 struct clk *clk; 1357 struct resource *iomem; 1358 struct bcm2835_host *host; 1359 struct mmc_host *mmc; 1360 const __be32 *regaddr_p; 1361 int ret; 1362 1363 dev_dbg(dev, "%s\n", __func__); 1364 mmc = mmc_alloc_host(sizeof(*host), dev); 1365 if (!mmc) 1366 return -ENOMEM; 1367 1368 mmc->ops = &bcm2835_ops; 1369 host = mmc_priv(mmc); 1370 host->mmc = mmc; 1371 host->pdev = pdev; 1372 spin_lock_init(&host->lock); 1373 1374 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1375 host->ioaddr = devm_ioremap_resource(dev, iomem); 1376 if (IS_ERR(host->ioaddr)) { 1377 ret = PTR_ERR(host->ioaddr); 1378 goto err; 1379 } 1380 1381 /* Parse OF address directly to get the physical address for 1382 * DMA to our registers. 1383 */ 1384 regaddr_p = of_get_address(pdev->dev.of_node, 0, NULL, NULL); 1385 if (!regaddr_p) { 1386 dev_err(dev, "Can't get phys address\n"); 1387 ret = -EINVAL; 1388 goto err; 1389 } 1390 1391 host->phys_addr = be32_to_cpup(regaddr_p); 1392 1393 host->dma_chan = NULL; 1394 host->dma_desc = NULL; 1395 1396 host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx"); 1397 1398 clk = devm_clk_get(dev, NULL); 1399 if (IS_ERR(clk)) { 1400 ret = PTR_ERR(clk); 1401 if (ret != -EPROBE_DEFER) 1402 dev_err(dev, "could not get clk: %d\n", ret); 1403 goto err; 1404 } 1405 1406 host->max_clk = clk_get_rate(clk); 1407 1408 host->irq = platform_get_irq(pdev, 0); 1409 if (host->irq <= 0) { 1410 dev_err(dev, "get IRQ failed\n"); 1411 ret = -EINVAL; 1412 goto err; 1413 } 1414 1415 ret = mmc_of_parse(mmc); 1416 if (ret) 1417 goto err; 1418 1419 ret = bcm2835_add_host(host); 1420 if (ret) 1421 goto err; 1422 1423 platform_set_drvdata(pdev, host); 1424 1425 dev_dbg(dev, "%s -> OK\n", __func__); 1426 1427 return 0; 1428 1429 err: 1430 dev_dbg(dev, "%s -> err %d\n", __func__, ret); 1431 mmc_free_host(mmc); 1432 1433 return ret; 1434 } 1435 1436 static int bcm2835_remove(struct platform_device *pdev) 1437 { 1438 struct bcm2835_host *host = platform_get_drvdata(pdev); 1439 1440 mmc_remove_host(host->mmc); 1441 1442 writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD); 1443 1444 free_irq(host->irq, host); 1445 1446 cancel_work_sync(&host->dma_work); 1447 cancel_delayed_work_sync(&host->timeout_work); 1448 1449 mmc_free_host(host->mmc); 1450 platform_set_drvdata(pdev, NULL); 1451 1452 return 0; 1453 } 1454 1455 static const struct of_device_id bcm2835_match[] = { 1456 { .compatible = "brcm,bcm2835-sdhost" }, 1457 { } 1458 }; 1459 MODULE_DEVICE_TABLE(of, bcm2835_match); 1460 1461 static struct platform_driver bcm2835_driver = { 1462 .probe = bcm2835_probe, 1463 .remove = bcm2835_remove, 1464 .driver = { 1465 .name = "sdhost-bcm2835", 1466 .of_match_table = bcm2835_match, 1467 }, 1468 }; 1469 module_platform_driver(bcm2835_driver); 1470 1471 MODULE_ALIAS("platform:sdhost-bcm2835"); 1472 MODULE_DESCRIPTION("BCM2835 SDHost driver"); 1473 MODULE_LICENSE("GPL v2"); 1474 MODULE_AUTHOR("Phil Elwell"); 1475